1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Stack allocation 11//===----------------------------------------------------------------------===// 12 13// The callseq_start node requires the hasSideEffects flag, even though these 14// instructions are noops on SystemZ. 15let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 16 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 17 [(callseq_start timm:$amt1, timm:$amt2)]>; 18 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 19 [(callseq_end timm:$amt1, timm:$amt2)]>; 20} 21 22// Takes as input the value of the stack pointer after a dynamic allocation 23// has been made. Sets the output to the address of the dynamically- 24// allocated area itself, skipping the outgoing arguments. 25// 26// This expands to an LA or LAY instruction. We restrict the offset 27// to the range of LA and keep the LAY range in reserve for when 28// the size of the outgoing arguments is added. 29def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 30 [(set GR64:$dst, dynalloc12only:$src)]>; 31 32let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 33 usesCustomInserter = 1 in 34 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 35 (ins GR64:$oldSP, GR64:$space), 36 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 37 38let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 39 hasSideEffects = 1 in 40 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 41 42//===----------------------------------------------------------------------===// 43// Branch instructions 44//===----------------------------------------------------------------------===// 45 46// Conditional branches. 47let isBranch = 1, isTerminator = 1, Uses = [CC] in { 48 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 49 // with the condition-code mask being the first operand. It seems friendlier 50 // to use mnemonic forms like JE and JLH when writing out the assembly though. 51 let isCodeGenOnly = 1 in { 52 // An assembler extended mnemonic for BRC. 53 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 54 // An assembler extended mnemonic for BRCL. (The extension is "G" 55 // rather than "L" because "JL" is "Jump if Less".) 56 def BRCL : CondBranchRIL<"jg#", 0xC04>; 57 let isIndirectBranch = 1 in { 58 def BC : CondBranchRX<"b#", 0x47>; 59 def BCR : CondBranchRR<"b#r", 0x07>; 60 def BIC : CondBranchRXY<"bi#", 0xe347>, 61 Requires<[FeatureMiscellaneousExtensions2]>; 62 } 63 } 64 65 // Allow using the raw forms directly from the assembler (and occasional 66 // special code generation needs) as well. 67 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 68 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 69 let isIndirectBranch = 1 in { 70 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 71 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 72 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 73 Requires<[FeatureMiscellaneousExtensions2]>; 74 } 75 76 // Define AsmParser extended mnemonics for each general condition-code mask 77 // (integer or floating-point) 78 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 79 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 80 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 81 def JGAsm#V : FixedCondBranchRIL<CV<V>, "jg#", 0xC04>; 82 let isIndirectBranch = 1 in { 83 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 84 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 85 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 86 Requires<[FeatureMiscellaneousExtensions2]>; 87 } 88 } 89} 90 91// Unconditional branches. These are in fact simply variants of the 92// conditional branches with the condition mask set to "always". 93let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 94 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 95 def JG : FixedCondBranchRIL<CondAlways, "jg", 0xC04>; 96 let isIndirectBranch = 1 in { 97 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 98 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 99 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 100 Requires<[FeatureMiscellaneousExtensions2]>; 101 } 102} 103 104// NOPs. These are again variants of the conditional branches, with the 105// condition mask set to "never". NOP_bare can't be an InstAlias since it 106// would need R0D hard coded which is not part of ADDR64BitRegClass. 107def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 108let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 109 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 110def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 111def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 112 113// An alias of BRC 0, label 114def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 115 116// An alias of BRCL 0, label 117def JGNOP : InstAlias<"jgnop\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 118 119// Fused compare-and-branch instructions. 120// 121// These instructions do not use or clobber the condition codes. 122// We nevertheless pretend that the relative compare-and-branch 123// instructions clobber CC, so that we can lower them to separate 124// comparisons and BRCLs if the branch ends up being out of range. 125let isBranch = 1, isTerminator = 1 in { 126 // As for normal branches, we handle these instructions internally in 127 // their raw CRJ-like form, but use assembly macros like CRJE when writing 128 // them out. Using the *Pair multiclasses, we also create the raw forms. 129 let Defs = [CC] in { 130 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 131 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 132 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 133 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 134 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 135 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 136 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 137 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 138 } 139 let isIndirectBranch = 1 in { 140 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 141 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 142 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 143 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 144 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 145 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 146 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 147 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 148 } 149 150 // Define AsmParser mnemonics for each integer condition-code mask. 151 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 152 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 153 let Defs = [CC] in { 154 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 155 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 156 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 157 imm32sx8>; 158 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 159 imm64sx8>; 160 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 161 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 162 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 163 imm32zx8>; 164 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 165 imm64zx8>; 166 } 167 let isIndirectBranch = 1 in { 168 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 169 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 170 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 171 imm32sx8>; 172 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 173 imm64sx8>; 174 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 175 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 176 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 177 imm32zx8>; 178 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 179 imm64zx8>; 180 } 181 } 182} 183 184// Decrement a register and branch if it is nonzero. These don't clobber CC, 185// but we might need to split long relative branches into sequences that do. 186let isBranch = 1, isTerminator = 1 in { 187 let Defs = [CC] in { 188 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 189 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 190 } 191 // This doesn't need to clobber CC since we never need to split it. 192 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 193 Requires<[FeatureHighWord]>; 194 195 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 196 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 197 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 198 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 199} 200 201let isBranch = 1, isTerminator = 1 in { 202 let Defs = [CC] in { 203 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 204 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 205 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 206 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 207 } 208 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 209 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 210 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 211 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 212} 213 214//===----------------------------------------------------------------------===// 215// Trap instructions 216//===----------------------------------------------------------------------===// 217 218// Unconditional trap. 219let hasCtrlDep = 1, hasSideEffects = 1 in 220 def Trap : Alias<4, (outs), (ins), [(trap)]>; 221 222// Conditional trap. 223let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 224 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 225 226// Fused compare-and-trap instructions. 227let hasCtrlDep = 1, hasSideEffects = 1 in { 228 // These patterns work the same way as for compare-and-branch. 229 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 230 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 231 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 232 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 233 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 234 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 235 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 236 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 237 let Predicates = [FeatureMiscellaneousExtensions] in { 238 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 239 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 240 } 241 242 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 243 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 244 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 245 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 246 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 247 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 248 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 249 imm32sx16>; 250 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 251 imm64sx16>; 252 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 253 imm32zx16>; 254 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 255 imm64zx16>; 256 let Predicates = [FeatureMiscellaneousExtensions] in { 257 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 258 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 259 } 260 } 261} 262 263//===----------------------------------------------------------------------===// 264// Call and return instructions 265//===----------------------------------------------------------------------===// 266 267// Define the general form of the call instructions for the asm parser. 268// These instructions don't hard-code %r14 as the return address register. 269let isCall = 1, Defs = [CC] in { 270 def BRAS : CallRI <"bras", 0xA75>; 271 def BRASL : CallRIL<"brasl", 0xC05>; 272 def BAS : CallRX <"bas", 0x4D>; 273 def BASR : CallRR <"basr", 0x0D>; 274} 275 276// Regular calls. 277let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 278 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 279 [(z_call pcrel32:$I2)]>; 280 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 281 [(z_call ADDR64:$R2)]>; 282} 283 284// TLS calls. These will be lowered into a call to __tls_get_offset, 285// with an extra relocation specifying the TLS symbol. 286let isCall = 1, Defs = [R14D, CC] in { 287 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 288 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 289 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 290 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 291} 292 293// Sibling calls. 294let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 295 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 296 [(z_sibcall pcrel32:$I2)]>; 297 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 298 [(z_sibcall ADDR64:$R2)]>; 299} 300 301// Conditional sibling calls. 302let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 303 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 304 pcrel32:$I2), []>; 305 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 306 ADDR64:$R2), []>; 307} 308 309// Fused compare and conditional sibling calls. 310let isCall = 1, isTerminator = 1, isReturn = 1 in { 311 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 312 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 313 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 314 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 315 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 316 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 317 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 318 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 319} 320 321// A return instruction (br %r14). 322let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 323 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 324 325// A conditional return instruction (bcr <cond>, %r14). 326let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 327 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 328 329// Fused compare and conditional returns. 330let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 331 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 332 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 333 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 334 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 335 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 336 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 337 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 338 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 339} 340 341//===----------------------------------------------------------------------===// 342// Select instructions 343//===----------------------------------------------------------------------===// 344 345def Select32 : SelectWrapper<i32, GR32>, 346 Requires<[FeatureNoLoadStoreOnCond]>; 347def Select64 : SelectWrapper<i64, GR64>, 348 Requires<[FeatureNoLoadStoreOnCond]>; 349 350// We don't define 32-bit Mux stores if we don't have STOCFH, because the 351// low-only STOC should then always be used if possible. 352defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 353 nonvolatile_anyextloadi8, bdxaddr20only>, 354 Requires<[FeatureHighWord]>; 355defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 356 nonvolatile_anyextloadi16, bdxaddr20only>, 357 Requires<[FeatureHighWord]>; 358defm CondStore32Mux : CondStores<GRX32, simple_store, 359 simple_load, bdxaddr20only>, 360 Requires<[FeatureLoadStoreOnCond2]>; 361defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 362 nonvolatile_anyextloadi8, bdxaddr20only>; 363defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 364 nonvolatile_anyextloadi16, bdxaddr20only>; 365defm CondStore32 : CondStores<GR32, simple_store, 366 simple_load, bdxaddr20only>; 367 368defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 369 nonvolatile_anyextloadi8, bdxaddr20only>; 370defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 371 nonvolatile_anyextloadi16, bdxaddr20only>; 372defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 373 nonvolatile_anyextloadi32, bdxaddr20only>; 374defm CondStore64 : CondStores<GR64, simple_store, 375 simple_load, bdxaddr20only>; 376 377//===----------------------------------------------------------------------===// 378// Move instructions 379//===----------------------------------------------------------------------===// 380 381// Register moves. 382def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 383def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 384 385let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 386 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 387 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 388} 389 390let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 391 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 392 393// Immediate moves. 394let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 395 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 396 // deopending on the choice of register. 397 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 398 Requires<[FeatureHighWord]>; 399 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 400 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 401 402 // Other 16-bit immediates. 403 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 404 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 405 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 406 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 407 408 // 32-bit immediates. 409 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 410 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 411 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 412} 413 414// Register loads. 415let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 416 // Expands to L, LY or LFH, depending on the choice of register. 417 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 418 Requires<[FeatureHighWord]>; 419 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 420 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 421 Requires<[FeatureHighWord]>; 422 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 423 424 // These instructions are split after register allocation, so we don't 425 // want a custom inserter. 426 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 427 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 428 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 429 } 430} 431let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 432 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 433 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 434} 435 436let canFoldAsLoad = 1 in { 437 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 438 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 439} 440 441// Load and zero rightmost byte. 442let Predicates = [FeatureLoadAndZeroRightmostByte] in { 443 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 444 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 445 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 446 (LZRF bdxaddr20only:$src)>; 447 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 448 (LZRG bdxaddr20only:$src)>; 449} 450 451// Load and trap. 452let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 453 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 454 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 455 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 456} 457 458// Register stores. 459let SimpleBDXStore = 1, mayStore = 1 in { 460 // Expands to ST, STY or STFH, depending on the choice of register. 461 def STMux : StoreRXYPseudo<store, GRX32, 4>, 462 Requires<[FeatureHighWord]>; 463 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 464 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 465 Requires<[FeatureHighWord]>; 466 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 467 468 // These instructions are split after register allocation, so we don't 469 // want a custom inserter. 470 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 471 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 472 [(store GR128:$src, bdxaddr20only128:$dst)]>; 473 } 474} 475def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 476def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 477 478// 8-bit immediate stores to 8-bit fields. 479defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 480 481// 16-bit immediate stores to 16-, 32- or 64-bit fields. 482def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 483def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 484def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 485 486// Memory-to-memory moves. 487let mayLoad = 1, mayStore = 1 in 488 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>; 489let mayLoad = 1, mayStore = 1, Defs = [CC] in { 490 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 491 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 492 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 493} 494 495// Move right. 496let Predicates = [FeatureMiscellaneousExtensions3], 497 mayLoad = 1, mayStore = 1, Uses = [R0L] in 498 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 499 500// String moves. 501let mayLoad = 1, mayStore = 1, Defs = [CC] in 502 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 503 504//===----------------------------------------------------------------------===// 505// Conditional move instructions 506//===----------------------------------------------------------------------===// 507 508let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 509 // Select. 510 let isCommutable = 1 in { 511 // Expands to SELR or SELFHR or a branch-and-move sequence, 512 // depending on the choice of registers. 513 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 514 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 515 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 516 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 517 } 518 519 // Define AsmParser extended mnemonics for each general condition-code mask. 520 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 521 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 522 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 523 GR32, GR32, GR32>; 524 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 525 GRH32, GRH32, GRH32>; 526 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 527 GR64, GR64, GR64>; 528 } 529} 530 531let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 532 // Load immediate on condition. Matched via DAG pattern and created 533 // by the PeepholeOptimizer via FoldImmediate. 534 535 // Expands to LOCHI or LOCHHI, depending on the choice of register. 536 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 537 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 538 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 539 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 540 541 // Move register on condition. Matched via DAG pattern and 542 // created by early if-conversion. 543 let isCommutable = 1 in { 544 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 545 // depending on the choice of registers. 546 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 547 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 548 } 549 550 // Load on condition. Matched via DAG pattern. 551 // Expands to LOC or LOCFH, depending on the choice of register. 552 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 553 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 554 555 // Store on condition. Expanded from CondStore* pseudos. 556 // Expands to STOC or STOCFH, depending on the choice of register. 557 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 558 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 559 560 // Define AsmParser extended mnemonics for each general condition-code mask. 561 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 562 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 563 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 564 imm32sx16>; 565 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 566 imm64sx16>; 567 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 568 imm32sx16>; 569 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 570 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 571 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 572 } 573} 574 575let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 576 // Move register on condition. Matched via DAG pattern and 577 // created by early if-conversion. 578 let isCommutable = 1 in { 579 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 580 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 581 } 582 583 // Load on condition. Matched via DAG pattern. 584 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 585 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 586 587 // Store on condition. Expanded from CondStore* pseudos. 588 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 589 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 590 591 // Define AsmParser extended mnemonics for each general condition-code mask. 592 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 593 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 594 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 595 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 596 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 597 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 598 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 599 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 600 } 601} 602//===----------------------------------------------------------------------===// 603// Sign extensions 604//===----------------------------------------------------------------------===// 605// 606// Note that putting these before zero extensions mean that we will prefer 607// them for anyextload*. There's not really much to choose between the two 608// either way, but signed-extending loads have a short LH and a long LHY, 609// while zero-extending loads have only the long LLH. 610// 611//===----------------------------------------------------------------------===// 612 613// 32-bit extensions from registers. 614def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 615def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 616 617// 64-bit extensions from registers. 618def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 619def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 620def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 621 622let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 623 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 624 625// Match 32-to-64-bit sign extensions in which the source is already 626// in a 64-bit register. 627def : Pat<(sext_inreg GR64:$src, i32), 628 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 629 630// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 631// depending on the choice of register. 632def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 633 Requires<[FeatureHighWord]>; 634def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 635def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 636 Requires<[FeatureHighWord]>; 637 638// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 639// depending on the choice of register. 640def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 641 Requires<[FeatureHighWord]>; 642defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 643def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 644 Requires<[FeatureHighWord]>; 645def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 646 647// 64-bit extensions from memory. 648def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 649def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 650def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 651def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 652def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 653let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 654 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 655 656//===----------------------------------------------------------------------===// 657// Zero extensions 658//===----------------------------------------------------------------------===// 659 660// 32-bit extensions from registers. 661 662// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 663def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 664 Requires<[FeatureHighWord]>; 665def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 666// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 667def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 668 Requires<[FeatureHighWord]>; 669def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 670 671// 64-bit extensions from registers. 672def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 673def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 674def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 675 676// Match 32-to-64-bit zero extensions in which the source is already 677// in a 64-bit register. 678def : Pat<(and GR64:$src, 0xffffffff), 679 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 680 681// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 682// depending on the choice of register. 683def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 684 Requires<[FeatureHighWord]>; 685def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 686def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 687 Requires<[FeatureHighWord]>; 688 689// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 690// depending on the choice of register. 691def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 692 Requires<[FeatureHighWord]>; 693def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 694def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 695 Requires<[FeatureHighWord]>; 696def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 697 698// 64-bit extensions from memory. 699def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 700def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 701def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 702def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 703def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 704 705// 31-to-64-bit zero extensions. 706def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 707def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 708def : Pat<(and GR64:$src, 0x7fffffff), 709 (LLGTR GR64:$src)>; 710def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 711 (LLGT bdxaddr20only:$src)>; 712 713// Load and zero rightmost byte. 714let Predicates = [FeatureLoadAndZeroRightmostByte] in { 715 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 716 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 717 (LLZRGF bdxaddr20only:$src)>; 718} 719 720// Load and trap. 721let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 722 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 723 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 724} 725 726// Extend GR64s to GR128s. 727let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 728 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 729 730//===----------------------------------------------------------------------===// 731// "Any" extensions 732//===----------------------------------------------------------------------===// 733 734// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 735def : Pat<(i64 (anyext GR32:$src)), 736 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 737 738// Extend GR64s to GR128s. 739let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 740 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 741 742//===----------------------------------------------------------------------===// 743// Truncations 744//===----------------------------------------------------------------------===// 745 746// Truncations of 64-bit registers to 32-bit registers. 747def : Pat<(i32 (trunc GR64:$src)), 748 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 749 750// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 751// STC, STCY or STCH, depending on the choice of register. 752def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 753 Requires<[FeatureHighWord]>; 754defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 755def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 756 Requires<[FeatureHighWord]>; 757 758// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 759// STH, STHY or STHH, depending on the choice of register. 760def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 761 Requires<[FeatureHighWord]>; 762defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 763def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 764 Requires<[FeatureHighWord]>; 765def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 766 767// Truncations of 64-bit registers to memory. 768defm : StoreGR64Pair<STC, STCY, truncstorei8>; 769defm : StoreGR64Pair<STH, STHY, truncstorei16>; 770def : StoreGR64PC<STHRL, aligned_truncstorei16>; 771defm : StoreGR64Pair<ST, STY, truncstorei32>; 772def : StoreGR64PC<STRL, aligned_truncstorei32>; 773 774// Store characters under mask -- not (yet) used for codegen. 775defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 776def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 777 778//===----------------------------------------------------------------------===// 779// Multi-register moves 780//===----------------------------------------------------------------------===// 781 782// Multi-register loads. 783defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 784def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 785def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 786def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 787 788// Multi-register stores. 789defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 790def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 791def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 792 793//===----------------------------------------------------------------------===// 794// Byte swaps 795//===----------------------------------------------------------------------===// 796 797// Byte-swapping register moves. 798def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 799def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 800 801// Byte-swapping loads. 802def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 803def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 804def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 805 806// Byte-swapping stores. 807def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 808def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 809def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 810 811// Byte-swapping memory-to-memory moves. 812let mayLoad = 1, mayStore = 1 in 813 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 814 815//===----------------------------------------------------------------------===// 816// Load address instructions 817//===----------------------------------------------------------------------===// 818 819// Load BDX-style addresses. 820let isAsCheapAsAMove = 1, isReMaterializable = 1 in 821 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 822 823// Load a PC-relative address. There's no version of this instruction 824// with a 16-bit offset, so there's no relaxation. 825let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 826 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 827 828// Load the Global Offset Table address. This will be lowered into a 829// larl $R1, _GLOBAL_OFFSET_TABLE_ 830// instruction. 831def GOT : Alias<6, (outs GR64:$R1), (ins), 832 [(set GR64:$R1, (global_offset_table))]>; 833 834//===----------------------------------------------------------------------===// 835// Absolute and Negation 836//===----------------------------------------------------------------------===// 837 838let Defs = [CC] in { 839 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 840 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 841 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 842 } 843 let CCValues = 0xE, CompareZeroCCMask = 0xE in 844 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 845} 846defm : SXU<abs, LPGFR>; 847 848let Defs = [CC] in { 849 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 850 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 851 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 852 } 853 let CCValues = 0xE, CompareZeroCCMask = 0xE in 854 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 855} 856defm : SXU<z_inegabs, LNGFR>; 857 858let Defs = [CC] in { 859 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 860 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 861 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 862 } 863 let CCValues = 0xE, CompareZeroCCMask = 0xE in 864 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 865} 866defm : SXU<ineg, LCGFR>; 867 868//===----------------------------------------------------------------------===// 869// Insertion 870//===----------------------------------------------------------------------===// 871 872let isCodeGenOnly = 1 in 873 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 874defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 875 876defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 877defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 878 879defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 880defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 881 882// Insert characters under mask -- not (yet) used for codegen. 883let Defs = [CC] in { 884 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 885 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 886} 887 888// Insertions of a 16-bit immediate, leaving other bits unaffected. 889// We don't have or_as_insert equivalents of these operations because 890// OI is available instead. 891// 892// IIxMux expands to II[LH]x, depending on the choice of register. 893def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 894 Requires<[FeatureHighWord]>; 895def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 896 Requires<[FeatureHighWord]>; 897def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 898def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 899def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 900def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 901def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 902def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 903def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 904def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 905 906// ...likewise for 32-bit immediates. For GR32s this is a general 907// full-width move. (We use IILF rather than something like LLILF 908// for 32-bit moves because IILF leaves the upper 32 bits of the 909// GR64 unchanged.) 910let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 911 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 912 Requires<[FeatureHighWord]>; 913 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 914 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 915} 916def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 917def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 918 919// An alternative model of inserthf, with the first operand being 920// a zero-extended value. 921def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 922 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 923 imm64hf32:$imm)>; 924 925//===----------------------------------------------------------------------===// 926// Addition 927//===----------------------------------------------------------------------===// 928 929// Addition producing a signed overflow flag. 930let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 931 // Addition of a register. 932 let isCommutable = 1 in { 933 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 934 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 935 } 936 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 937 938 // Addition to a high register. 939 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 940 Requires<[FeatureHighWord]>; 941 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 942 Requires<[FeatureHighWord]>; 943 944 // Addition of signed 16-bit immediates. 945 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 946 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 947 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 948 949 // Addition of signed 32-bit immediates. 950 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 951 Requires<[FeatureHighWord]>; 952 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 953 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 954 Requires<[FeatureHighWord]>; 955 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 956 957 // Addition of memory. 958 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 959 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 960 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 961 Requires<[FeatureMiscellaneousExtensions2]>; 962 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 963 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 964 965 // Addition to memory. 966 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 967 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 968} 969defm : SXB<z_sadd, GR64, AGFR>; 970 971// Addition producing a carry. 972let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 973 // Addition of a register. 974 let isCommutable = 1 in { 975 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 976 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 977 } 978 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 979 980 // Addition to a high register. 981 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 982 Requires<[FeatureHighWord]>; 983 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 984 Requires<[FeatureHighWord]>; 985 986 // Addition of signed 16-bit immediates. 987 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 988 Requires<[FeatureDistinctOps]>; 989 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 990 Requires<[FeatureDistinctOps]>; 991 992 // Addition of unsigned 32-bit immediates. 993 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 994 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 995 996 // Addition of signed 32-bit immediates. 997 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 998 Requires<[FeatureHighWord]>; 999 1000 // Addition of memory. 1001 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1002 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1003 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1004 1005 // Addition to memory. 1006 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1007 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1008} 1009defm : ZXB<z_uadd, GR64, ALGFR>; 1010 1011// Addition producing and using a carry. 1012let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1013 // Addition of a register. 1014 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1015 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1016 1017 // Addition of memory. 1018 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1019 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1020} 1021 1022// Addition that does not modify the condition code. 1023def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1024 Requires<[FeatureHighWord]>; 1025 1026 1027//===----------------------------------------------------------------------===// 1028// Subtraction 1029//===----------------------------------------------------------------------===// 1030 1031// Subtraction producing a signed overflow flag. 1032let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1033 CCIfNoSignedWrap = 1 in { 1034 // Subtraction of a register. 1035 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1036 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1037 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1038 1039 // Subtraction from a high register. 1040 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1041 Requires<[FeatureHighWord]>; 1042 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1043 Requires<[FeatureHighWord]>; 1044 1045 // Subtraction of memory. 1046 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1047 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1048 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1049 Requires<[FeatureMiscellaneousExtensions2]>; 1050 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1051 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1052} 1053defm : SXB<z_ssub, GR64, SGFR>; 1054 1055// Subtracting an immediate is the same as adding the negated immediate. 1056let AddedComplexity = 1 in { 1057 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1058 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1059 Requires<[FeatureHighWord]>; 1060 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1061 (AFIMux GR32:$src1, simm32n:$src2)>, 1062 Requires<[FeatureHighWord]>; 1063 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1064 (AHI GR32:$src1, imm32sx16n:$src2)>; 1065 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1066 (AFI GR32:$src1, simm32n:$src2)>; 1067 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1068 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1069 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1070 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1071} 1072 1073// And vice versa in one special case, where we need to load a 1074// constant into a register in any case, but the negated constant 1075// requires fewer instructions to load. 1076def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1077 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1078def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1079 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1080 1081// Subtraction producing a carry. 1082let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1083 // Subtraction of a register. 1084 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1085 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1086 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1087 1088 // Subtraction from a high register. 1089 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1090 Requires<[FeatureHighWord]>; 1091 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1092 Requires<[FeatureHighWord]>; 1093 1094 // Subtraction of unsigned 32-bit immediates. 1095 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1096 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1097 1098 // Subtraction of memory. 1099 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1100 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1101 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1102} 1103defm : ZXB<z_usub, GR64, SLGFR>; 1104 1105// Subtracting an immediate is the same as adding the negated immediate. 1106let AddedComplexity = 1 in { 1107 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1108 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1109 Requires<[FeatureDistinctOps]>; 1110 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1111 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1112 Requires<[FeatureDistinctOps]>; 1113} 1114 1115// And vice versa in one special case (but we prefer addition). 1116def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1117 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1118 1119// Subtraction producing and using a carry. 1120let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1121 // Subtraction of a register. 1122 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1123 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1124 1125 // Subtraction of memory. 1126 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1127 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1128} 1129 1130 1131//===----------------------------------------------------------------------===// 1132// AND 1133//===----------------------------------------------------------------------===// 1134 1135let Defs = [CC] in { 1136 // ANDs of a register. 1137 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1138 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1139 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1140 } 1141 1142 let isConvertibleToThreeAddress = 1 in { 1143 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1144 // The CC result only reflects the 16-bit field, not the full register. 1145 // 1146 // NIxMux expands to NI[LH]x, depending on the choice of register. 1147 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1148 Requires<[FeatureHighWord]>; 1149 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1150 Requires<[FeatureHighWord]>; 1151 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1152 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1153 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1154 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1155 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1156 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1157 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1158 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1159 1160 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1161 // The CC result only reflects the 32-bit field, which means we can 1162 // use it as a zero indicator for i32 operations but not otherwise. 1163 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1164 // Expands to NILF or NIHF, depending on the choice of register. 1165 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1166 Requires<[FeatureHighWord]>; 1167 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1168 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1169 } 1170 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1171 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1172 } 1173 1174 // ANDs of memory. 1175 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1176 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1177 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1178 } 1179 1180 // AND to memory 1181 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1182 1183 // Block AND. 1184 let mayLoad = 1, mayStore = 1 in 1185 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>; 1186} 1187defm : RMWIByte<and, bdaddr12pair, NI>; 1188defm : RMWIByte<and, bdaddr20pair, NIY>; 1189 1190//===----------------------------------------------------------------------===// 1191// OR 1192//===----------------------------------------------------------------------===// 1193 1194let Defs = [CC] in { 1195 // ORs of a register. 1196 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1197 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1198 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1199 } 1200 1201 // ORs of a 16-bit immediate, leaving other bits unaffected. 1202 // The CC result only reflects the 16-bit field, not the full register. 1203 // 1204 // OIxMux expands to OI[LH]x, depending on the choice of register. 1205 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1206 Requires<[FeatureHighWord]>; 1207 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1208 Requires<[FeatureHighWord]>; 1209 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1210 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1211 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1212 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1213 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1214 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1215 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1216 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1217 1218 // ORs of a 32-bit immediate, leaving other bits unaffected. 1219 // The CC result only reflects the 32-bit field, which means we can 1220 // use it as a zero indicator for i32 operations but not otherwise. 1221 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1222 // Expands to OILF or OIHF, depending on the choice of register. 1223 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1224 Requires<[FeatureHighWord]>; 1225 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1226 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1227 } 1228 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1229 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1230 1231 // ORs of memory. 1232 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1233 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1234 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1235 } 1236 1237 // OR to memory 1238 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1239 1240 // Block OR. 1241 let mayLoad = 1, mayStore = 1 in 1242 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>; 1243} 1244defm : RMWIByte<or, bdaddr12pair, OI>; 1245defm : RMWIByte<or, bdaddr20pair, OIY>; 1246 1247//===----------------------------------------------------------------------===// 1248// XOR 1249//===----------------------------------------------------------------------===// 1250 1251let Defs = [CC] in { 1252 // XORs of a register. 1253 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1254 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1255 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1256 } 1257 1258 // XORs of a 32-bit immediate, leaving other bits unaffected. 1259 // The CC result only reflects the 32-bit field, which means we can 1260 // use it as a zero indicator for i32 operations but not otherwise. 1261 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1262 // Expands to XILF or XIHF, depending on the choice of register. 1263 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1264 Requires<[FeatureHighWord]>; 1265 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1266 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1267 } 1268 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1269 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1270 1271 // XORs of memory. 1272 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1273 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1274 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1275 } 1276 1277 // XOR to memory 1278 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1279 1280 // Block XOR. 1281 let mayLoad = 1, mayStore = 1 in 1282 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>; 1283} 1284defm : RMWIByte<xor, bdaddr12pair, XI>; 1285defm : RMWIByte<xor, bdaddr20pair, XIY>; 1286 1287//===----------------------------------------------------------------------===// 1288// Combined logical operations 1289//===----------------------------------------------------------------------===// 1290 1291let Predicates = [FeatureMiscellaneousExtensions3], 1292 Defs = [CC] in { 1293 // AND with complement. 1294 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1295 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1296 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1297 } 1298 1299 // OR with complement. 1300 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1301 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1302 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1303 } 1304 1305 // NAND. 1306 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1307 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1308 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1309 } 1310 1311 // NOR. 1312 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1313 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1314 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1315 } 1316 1317 // NXOR. 1318 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1319 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1320 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1321 } 1322} 1323 1324//===----------------------------------------------------------------------===// 1325// Multiplication 1326//===----------------------------------------------------------------------===// 1327 1328// Multiplication of a register, setting the condition code. We prefer these 1329// over MS(G)R if available, even though we cannot use the condition code, 1330// since they are three-operand instructions. 1331let Predicates = [FeatureMiscellaneousExtensions2], 1332 Defs = [CC], isCommutable = 1 in { 1333 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1334 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1335} 1336 1337// Multiplication of a register. 1338let isCommutable = 1 in { 1339 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1340 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1341} 1342def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1343defm : SXB<mul, GR64, MSGFR>; 1344 1345// Multiplication of a signed 16-bit immediate. 1346def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1347def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1348 1349// Multiplication of a signed 32-bit immediate. 1350def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1351def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1352 1353// Multiplication of memory. 1354defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1355defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1356def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1357 Requires<[FeatureMiscellaneousExtensions2]>; 1358def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1359def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1360 1361// Multiplication of memory, setting the condition code. 1362let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1363 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1364 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1365} 1366 1367// Multiplication of a register, producing two results. 1368def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1369def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1370 Requires<[FeatureMiscellaneousExtensions2]>; 1371def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1372def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1373 1374def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1375 (MGRK GR64:$src1, GR64:$src2)>; 1376def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1377 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1378 1379// Multiplication of memory, producing two results. 1380def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1381def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1382def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1383 Requires<[FeatureMiscellaneousExtensions2]>; 1384def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1385def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1386 1387def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1388 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1389def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1390 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1391 1392//===----------------------------------------------------------------------===// 1393// Division and remainder 1394//===----------------------------------------------------------------------===// 1395 1396let hasSideEffects = 1 in { // Do not speculatively execute. 1397 // Division and remainder, from registers. 1398 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1399 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1400 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1401 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1402 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1403 1404 // Division and remainder, from memory. 1405 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1406 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1407 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1408 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1409 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1410} 1411def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1412 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1413def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1414 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1415def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1416 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1417def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1418 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1419 1420def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1421 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1422 subreg_l32)), GR32:$src2)>; 1423def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1424 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1425 subreg_l32)), bdxaddr20only:$src2)>; 1426def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1427 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1428def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1429 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1430 1431//===----------------------------------------------------------------------===// 1432// Shifts 1433//===----------------------------------------------------------------------===// 1434 1435// Logical shift left. 1436defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1437def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1438def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1439 1440// Arithmetic shift left. 1441let Defs = [CC] in { 1442 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1443 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1444 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1445} 1446 1447// Logical shift right. 1448defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1449def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1450def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1451 1452// Arithmetic shift right. 1453let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1454 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1455 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1456 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1457} 1458 1459// Rotate left. 1460def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1461def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1462 1463// Rotate second operand left and inserted selected bits into first operand. 1464// These can act like 32-bit operands provided that the constant start and 1465// end bits (operands 2 and 3) are in the range [32, 64). 1466let Defs = [CC] in { 1467 let isCodeGenOnly = 1 in 1468 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1469 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1470 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1471} 1472 1473// On zEC12 we have a variant of RISBG that does not set CC. 1474let Predicates = [FeatureMiscellaneousExtensions] in 1475 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1476 1477// Forms of RISBG that only affect one word of the destination register. 1478// They do not set CC. 1479let Predicates = [FeatureHighWord] in { 1480 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1481 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1482 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1483 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1484 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1485 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1486 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1487} 1488 1489// Rotate second operand left and perform a logical operation with selected 1490// bits of the first operand. The CC result only describes the selected bits, 1491// so isn't useful for a full comparison against zero. 1492let Defs = [CC] in { 1493 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1494 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1495 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1496} 1497 1498//===----------------------------------------------------------------------===// 1499// Comparison 1500//===----------------------------------------------------------------------===// 1501 1502// Signed comparisons. We put these before the unsigned comparisons because 1503// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1504// of the unsigned forms do. 1505let Defs = [CC], CCValues = 0xE in { 1506 // Comparison with a register. 1507 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1508 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1509 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1510 1511 // Comparison with a high register. 1512 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1513 Requires<[FeatureHighWord]>; 1514 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1515 Requires<[FeatureHighWord]>; 1516 1517 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1518 // depending on the choice of register. 1519 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1520 Requires<[FeatureHighWord]>; 1521 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1522 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1523 1524 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1525 // depending on the choice of register. 1526 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1527 Requires<[FeatureHighWord]>; 1528 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1529 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1530 Requires<[FeatureHighWord]>; 1531 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1532 1533 // Comparison with memory. 1534 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1535 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1536 Requires<[FeatureHighWord]>; 1537 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1538 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1539 Requires<[FeatureHighWord]>; 1540 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1541 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1542 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1543 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1544 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1545 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1546 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1547 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1548 1549 // Comparison between memory and a signed 16-bit immediate. 1550 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1551 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1552 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1553} 1554defm : SXB<z_scmp, GR64, CGFR>; 1555 1556// Unsigned comparisons. 1557let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1558 // Comparison with a register. 1559 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1560 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1561 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1562 1563 // Comparison with a high register. 1564 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1565 Requires<[FeatureHighWord]>; 1566 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1567 Requires<[FeatureHighWord]>; 1568 1569 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1570 // or CLIH, depending on the choice of register. 1571 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1572 Requires<[FeatureHighWord]>; 1573 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1574 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1575 Requires<[FeatureHighWord]>; 1576 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1577 1578 // Comparison with memory. 1579 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1580 Requires<[FeatureHighWord]>; 1581 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1582 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1583 Requires<[FeatureHighWord]>; 1584 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1585 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1586 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1587 aligned_azextloadi16>; 1588 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1589 aligned_load>; 1590 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1591 aligned_azextloadi16>; 1592 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1593 aligned_azextloadi32>; 1594 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1595 aligned_load>; 1596 1597 // Comparison between memory and an unsigned 8-bit immediate. 1598 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1599 1600 // Comparison between memory and an unsigned 16-bit immediate. 1601 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1602 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1603 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1604} 1605defm : ZXB<z_ucmp, GR64, CLGFR>; 1606 1607// Memory-to-memory comparison. 1608let mayLoad = 1, Defs = [CC] in { 1609 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc, z_clc_loop>; 1610 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1611 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1612 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1613} 1614 1615// String comparison. 1616let mayLoad = 1, Defs = [CC] in 1617 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1618 1619// Test under mask. 1620let Defs = [CC] in { 1621 // TMxMux expands to TM[LH]x, depending on the choice of register. 1622 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1623 Requires<[FeatureHighWord]>; 1624 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1625 Requires<[FeatureHighWord]>; 1626 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1627 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1628 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1629 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1630 1631 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1632 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1633 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1634 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1635 1636 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1637} 1638 1639def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1640def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1641 1642// Compare logical characters under mask -- not (yet) used for codegen. 1643let Defs = [CC] in { 1644 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1645 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1646} 1647 1648//===----------------------------------------------------------------------===// 1649// Prefetch and execution hint 1650//===----------------------------------------------------------------------===// 1651 1652let mayLoad = 1, mayStore = 1 in { 1653 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1654 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1655} 1656 1657let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1658 // Branch Prediction Preload 1659 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1660 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1661 1662 // Next Instruction Access Intent 1663 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1664} 1665 1666//===----------------------------------------------------------------------===// 1667// Atomic operations 1668//===----------------------------------------------------------------------===// 1669 1670// A serialization instruction that acts as a barrier for all memory 1671// accesses, which expands to "bcr 14, 0". 1672let hasSideEffects = 1 in 1673def Serialize : Alias<2, (outs), (ins), []>; 1674 1675// A pseudo instruction that serves as a compiler barrier. 1676let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1677def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1678 1679let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1680 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1681 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1682 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1683 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1684 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1685 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1686 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1687 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1688 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1689 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1690} 1691 1692def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1693def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1694def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1695 1696def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1697def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1698let Predicates = [FeatureNoInterlockedAccess1] in { 1699 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1700 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1701 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1702 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1703 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1704 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1705} 1706 1707def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1708def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1709def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1710 1711def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1712def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1713let Predicates = [FeatureNoInterlockedAccess1] in { 1714 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1715 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1716 imm32ll16c>; 1717 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1718 imm32lh16c>; 1719 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1720 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1721 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1722 imm64ll16c>; 1723 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1724 imm64lh16c>; 1725 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1726 imm64hl16c>; 1727 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1728 imm64hh16c>; 1729 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1730 imm64lf32c>; 1731 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1732 imm64hf32c>; 1733} 1734 1735def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1736def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1737let Predicates = [FeatureNoInterlockedAccess1] in { 1738 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1739 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1740 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1741 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1742 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1743 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1744 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1745 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1746 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1747 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1748 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1749} 1750 1751def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1752def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1753let Predicates = [FeatureNoInterlockedAccess1] in { 1754 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1755 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1756 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1757 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1758 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1759} 1760 1761def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1762def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1763 imm32lh16c>; 1764def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1765def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1766 imm32ll16c>; 1767def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1768 imm32lh16c>; 1769def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1770def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1771def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1772 imm64ll16c>; 1773def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1774 imm64lh16c>; 1775def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1776 imm64hl16c>; 1777def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1778 imm64hh16c>; 1779def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1780 imm64lf32c>; 1781def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1782 imm64hf32c>; 1783 1784def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1785def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1786def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1787 1788def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1789def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1790def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1791 1792def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1793def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1794def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1795 1796def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1797def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1798def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1799 1800def ATOMIC_CMP_SWAPW 1801 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1802 ADDR32:$bitshift, ADDR32:$negbitshift, 1803 uimm32:$bitsize), 1804 [(set GR32:$dst, 1805 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1806 ADDR32:$bitshift, ADDR32:$negbitshift, 1807 uimm32:$bitsize))]> { 1808 let Defs = [CC]; 1809 let mayLoad = 1; 1810 let mayStore = 1; 1811 let usesCustomInserter = 1; 1812 let hasNoSchedulingInfo = 1; 1813} 1814 1815// Test and set. 1816let mayLoad = 1, Defs = [CC] in 1817 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1818 1819// Compare and swap. 1820let Defs = [CC] in { 1821 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1822 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1823} 1824 1825// Compare double and swap. 1826let Defs = [CC] in { 1827 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1828 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1829} 1830 1831// Compare and swap and store. 1832let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1833 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1834 1835// Perform locked operation. 1836let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1837 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1838 1839// Load/store pair from/to quadword. 1840def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1841def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1842 1843// Load pair disjoint. 1844let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1845 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1846 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1847} 1848 1849//===----------------------------------------------------------------------===// 1850// Translate and convert 1851//===----------------------------------------------------------------------===// 1852 1853let mayLoad = 1, mayStore = 1 in 1854 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1855 1856let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1857 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1858 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1859} 1860 1861let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1862 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1863 1864let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1865 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1866 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1867} 1868 1869let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1870 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1871 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1872 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1873 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1874} 1875 1876let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1877 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1878 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1879 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1880 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1881 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1882 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1883 1884 let isAsmParserOnly = 1 in { 1885 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1886 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1887 } 1888} 1889 1890//===----------------------------------------------------------------------===// 1891// Message-security assist 1892//===----------------------------------------------------------------------===// 1893 1894let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1895 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1896 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1897 1898 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1899 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1900 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1901 1902 let Predicates = [FeatureMessageSecurityAssist4] in { 1903 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1904 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1905 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1906 GR128, GR128, GR128>; 1907 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1908 } 1909 1910 let Predicates = [FeatureMessageSecurityAssist5] in 1911 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1912 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1913 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1914 1915 let Predicates = [FeatureMessageSecurityAssist8] in 1916 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1917 GR128, GR128, GR128>; 1918 1919 let Predicates = [FeatureMessageSecurityAssist9] in 1920 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1921} 1922 1923//===----------------------------------------------------------------------===// 1924// Guarded storage 1925//===----------------------------------------------------------------------===// 1926 1927// These instructions use and/or modify the guarded storage control 1928// registers, which we do not otherwise model, so they should have 1929// hasSideEffects. 1930let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1931 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1932 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1933 1934 let mayLoad = 1 in 1935 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1936 let mayStore = 1 in 1937 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1938} 1939 1940//===----------------------------------------------------------------------===// 1941// Decimal arithmetic 1942//===----------------------------------------------------------------------===// 1943 1944defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1945def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1946 1947defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1948def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1949 1950let mayLoad = 1, mayStore = 1 in { 1951 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1952 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1953 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1954 1955 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1956 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1957 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1958 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1959 let Defs = [CC] in { 1960 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1961 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1962 } 1963} 1964 1965let mayLoad = 1, mayStore = 1 in { 1966 let Defs = [CC] in { 1967 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1968 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1969 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1970 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1971 } 1972 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1973 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1974 let Defs = [CC] in { 1975 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1976 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1977 } 1978} 1979 1980let Defs = [CC] in { 1981 def CP : CompareSSb<"cp", 0xF9>; 1982 def TP : TestRSL<"tp", 0xEBC0>; 1983} 1984 1985//===----------------------------------------------------------------------===// 1986// Access registers 1987//===----------------------------------------------------------------------===// 1988 1989// Read a 32-bit access register into a GR32. As with all GR32 operations, 1990// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1991// when a 64-bit address is stored in a pair of access registers. 1992def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1993 1994// Set access register. 1995def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1996 1997// Copy access register. 1998def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1999 2000// Load address extended. 2001defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2002 2003// Load access multiple. 2004defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2005 2006// Store access multiple. 2007defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2008 2009//===----------------------------------------------------------------------===// 2010// Program mask and addressing mode 2011//===----------------------------------------------------------------------===// 2012 2013// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2014let Uses = [CC] in 2015 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2016 2017// Set CC and program mask from a register. 2018let hasSideEffects = 1, Defs = [CC] in 2019 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2020 2021// Branch and link - like BAS, but also extracts CC and program mask. 2022let isCall = 1, Uses = [CC], Defs = [CC] in { 2023 def BAL : CallRX<"bal", 0x45>; 2024 def BALR : CallRR<"balr", 0x05>; 2025} 2026 2027// Test addressing mode. 2028let Defs = [CC] in 2029 def TAM : SideEffectInherentE<"tam", 0x010B>; 2030 2031// Set addressing mode. 2032let hasSideEffects = 1 in { 2033 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2034 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2035 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2036} 2037 2038// Branch and set mode. Not really a call, but also sets an output register. 2039let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2040 def BSM : CallRR<"bsm", 0x0B>; 2041 2042// Branch and save and set mode. 2043let isCall = 1, Defs = [CC] in 2044 def BASSM : CallRR<"bassm", 0x0C>; 2045 2046//===----------------------------------------------------------------------===// 2047// Transactional execution 2048//===----------------------------------------------------------------------===// 2049 2050let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2051 // Transaction Begin 2052 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2053 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2054 let hasNoSchedulingInfo = 1 in 2055 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2056 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2057 int_s390_tbeginc, imm32zx16>; 2058 } 2059 2060 // Transaction End 2061 let Defs = [CC] in 2062 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2063 2064 // Transaction Abort 2065 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2066 hasSideEffects = 1 in 2067 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2068 2069 // Nontransactional Store 2070 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2071 2072 // Extract Transaction Nesting Depth 2073 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2074} 2075 2076//===----------------------------------------------------------------------===// 2077// Processor assist 2078//===----------------------------------------------------------------------===// 2079 2080let Predicates = [FeatureProcessorAssist] in { 2081 let hasSideEffects = 1 in 2082 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2083 def : Pat<(int_s390_ppa_txassist GR32:$src), 2084 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2085 zero_reg, 1)>; 2086} 2087 2088//===----------------------------------------------------------------------===// 2089// Miscellaneous Instructions. 2090//===----------------------------------------------------------------------===// 2091 2092// Find leftmost one, AKA count leading zeros. The instruction actually 2093// returns a pair of GR64s, the first giving the number of leading zeros 2094// and the second giving a copy of the source with the leftmost one bit 2095// cleared. We only use the first result here. 2096let Defs = [CC] in 2097 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2098def : Pat<(i64 (ctlz GR64:$src)), 2099 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2100 2101// Population count. Counts bits set per byte or doubleword. 2102let Predicates = [FeatureMiscellaneousExtensions3] in { 2103 let Defs = [CC] in 2104 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2105 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2106} 2107let Predicates = [FeaturePopulationCount], Defs = [CC] in 2108 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2109 2110// Search a block of memory for a character. 2111let mayLoad = 1, Defs = [CC] in 2112 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2113let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2114 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2115 2116// Compare until substring equal. 2117let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2118 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2119 2120// Compare and form codeword. 2121let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2122 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2123 2124// Update tree. 2125let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2126 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2127 def UPT : SideEffectInherentE<"upt", 0x0102>; 2128 2129// Checksum. 2130let mayLoad = 1, Defs = [CC] in 2131 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2132 2133// Compression call. 2134let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2135 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2136 2137// Sort lists. 2138let Predicates = [FeatureEnhancedSort], 2139 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2140 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2141 2142// Deflate conversion call. 2143let Predicates = [FeatureDeflateConversion], 2144 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2145 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2146 GR128, GR128, GR64>; 2147 2148// Execute. 2149let hasSideEffects = 1 in { 2150 def EX : SideEffectBinaryRX<"ex", 0x44, GR64>; 2151 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, GR64>; 2152} 2153 2154//===----------------------------------------------------------------------===// 2155// .insn directive instructions 2156//===----------------------------------------------------------------------===// 2157 2158let isCodeGenOnly = 1, hasSideEffects = 1 in { 2159 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2160 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2161 imm32sx16:$I2), 2162 ".insn ri,$enc,$R1,$I2", []>; 2163 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2164 AnyReg:$R3, brtarget16:$I2), 2165 ".insn rie,$enc,$R1,$R3,$I2", []>; 2166 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2167 brtarget32:$I2), 2168 ".insn ril,$enc,$R1,$I2", []>; 2169 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2170 uimm32:$I2), 2171 ".insn rilu,$enc,$R1,$I2", []>; 2172 def InsnRIS : DirectiveInsnRIS<(outs), 2173 (ins imm64zx48:$enc, AnyReg:$R1, 2174 imm32sx8:$I2, imm32zx4:$M3, 2175 bdaddr12only:$BD4), 2176 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2177 def InsnRR : DirectiveInsnRR<(outs), 2178 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2179 ".insn rr,$enc,$R1,$R2", []>; 2180 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2181 AnyReg:$R1, AnyReg:$R2), 2182 ".insn rre,$enc,$R1,$R2", []>; 2183 def InsnRRF : DirectiveInsnRRF<(outs), 2184 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2185 AnyReg:$R3, imm32zx4:$M4), 2186 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2187 def InsnRRS : DirectiveInsnRRS<(outs), 2188 (ins imm64zx48:$enc, AnyReg:$R1, 2189 AnyReg:$R2, imm32zx4:$M3, 2190 bdaddr12only:$BD4), 2191 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2192 def InsnRS : DirectiveInsnRS<(outs), 2193 (ins imm64zx32:$enc, AnyReg:$R1, 2194 AnyReg:$R3, bdaddr12only:$BD2), 2195 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2196 def InsnRSE : DirectiveInsnRSE<(outs), 2197 (ins imm64zx48:$enc, AnyReg:$R1, 2198 AnyReg:$R3, bdaddr12only:$BD2), 2199 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2200 def InsnRSI : DirectiveInsnRSI<(outs), 2201 (ins imm64zx48:$enc, AnyReg:$R1, 2202 AnyReg:$R3, brtarget16:$RI2), 2203 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2204 def InsnRSY : DirectiveInsnRSY<(outs), 2205 (ins imm64zx48:$enc, AnyReg:$R1, 2206 AnyReg:$R3, bdaddr20only:$BD2), 2207 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2208 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2209 bdxaddr12only:$XBD2), 2210 ".insn rx,$enc,$R1,$XBD2", []>; 2211 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2212 bdxaddr12only:$XBD2), 2213 ".insn rxe,$enc,$R1,$XBD2", []>; 2214 def InsnRXF : DirectiveInsnRXF<(outs), 2215 (ins imm64zx48:$enc, AnyReg:$R1, 2216 AnyReg:$R3, bdxaddr12only:$XBD2), 2217 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2218 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2219 bdxaddr20only:$XBD2), 2220 ".insn rxy,$enc,$R1,$XBD2", []>; 2221 def InsnS : DirectiveInsnS<(outs), 2222 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2223 ".insn s,$enc,$BD2", []>; 2224 def InsnSI : DirectiveInsnSI<(outs), 2225 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2226 imm32sx8:$I2), 2227 ".insn si,$enc,$BD1,$I2", []>; 2228 def InsnSIY : DirectiveInsnSIY<(outs), 2229 (ins imm64zx48:$enc, 2230 bdaddr20only:$BD1, imm32zx8:$I2), 2231 ".insn siy,$enc,$BD1,$I2", []>; 2232 def InsnSIL : DirectiveInsnSIL<(outs), 2233 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2234 imm32zx16:$I2), 2235 ".insn sil,$enc,$BD1,$I2", []>; 2236 def InsnSS : DirectiveInsnSS<(outs), 2237 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2238 bdaddr12only:$BD2, AnyReg:$R3), 2239 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2240 def InsnSSE : DirectiveInsnSSE<(outs), 2241 (ins imm64zx48:$enc, 2242 bdaddr12only:$BD1,bdaddr12only:$BD2), 2243 ".insn sse,$enc,$BD1,$BD2", []>; 2244 def InsnSSF : DirectiveInsnSSF<(outs), 2245 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2246 bdaddr12only:$BD2, AnyReg:$R3), 2247 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2248 def InsnVRI : DirectiveInsnVRI<(outs), 2249 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2250 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2251 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2252 def InsnVRR : DirectiveInsnVRR<(outs), 2253 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2254 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2255 imm32zx4:$M6), 2256 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2257 def InsnVRS : DirectiveInsnVRS<(outs), 2258 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2259 bdaddr12only:$BD2, imm32zx4:$M4), 2260 ".insn vrs,$enc,$BD2,$M4", []>; 2261 def InsnVRV : DirectiveInsnVRV<(outs), 2262 (ins imm64zx48:$enc, VR128:$V1, 2263 bdvaddr12only:$VBD2, imm32zx4:$M3), 2264 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2265 def InsnVRX : DirectiveInsnVRX<(outs), 2266 (ins imm64zx48:$enc, VR128:$V1, 2267 bdxaddr12only:$XBD2, imm32zx4:$M3), 2268 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2269 def InsnVSI : DirectiveInsnVSI<(outs), 2270 (ins imm64zx48:$enc, VR128:$V1, 2271 bdaddr12only:$BD2, imm32zx8:$I3), 2272 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2273} 2274 2275//===----------------------------------------------------------------------===// 2276// Peepholes. 2277//===----------------------------------------------------------------------===// 2278 2279// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2280// equivalent to (and (xor x, -1), y) 2281def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2282 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2283 2284// Shift/rotate instructions only use the last 6 bits of the second operand 2285// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2286// last 16 bits. 2287// Complexity is added so that we match this before we match NILF on the AND 2288// operation alone. 2289let AddedComplexity = 4 in { 2290 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2291 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2292 2293 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2294 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2295 2296 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2297 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2298 2299 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2300 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2301 2302 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2303 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2304 2305 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2306 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2307 2308 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2309 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2310 2311 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2312 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2313} 2314 2315// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2316// use the last 6 bits of the second operand register (making it modulo 64). 2317let AddedComplexity = 4 in { 2318 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2319 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2320 2321 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2322 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2323 2324 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2325 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2326 2327 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2328 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2329} 2330 2331// Peepholes for turning scalar operations into block operations. 2332defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence, 2333 XCSequence, 1>; 2334defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence, 2335 XCSequence, 2>; 2336defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence, 2337 XCSequence, 4>; 2338defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence, 2339 OCSequence, XCSequence, 1>; 2340defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence, 2341 XCSequence, 2>; 2342defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence, 2343 XCSequence, 4>; 2344defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence, 2345 XCSequence, 8>; 2346 2347//===----------------------------------------------------------------------===// 2348// Mnemonic Aliases 2349//===----------------------------------------------------------------------===// 2350 2351def JCT : MnemonicAlias<"jct", "brct">; 2352def JCTG : MnemonicAlias<"jctg", "brctg">; 2353def JAS : MnemonicAlias<"jas", "bras">; 2354def JASL : MnemonicAlias<"jasl", "brasl">; 2355def JXH : MnemonicAlias<"jxh", "brxh">; 2356def JXLE : MnemonicAlias<"jxle", "brxle">; 2357def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2358def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2359 2360def BRU : MnemonicAlias<"bru", "j">; 2361def BRUL : MnemonicAlias<"brul", "jg">; 2362 2363foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2364 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2365 def BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2366 def BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#">; 2367} 2368