1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the SystemZ implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 14 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 15 16 #include "SystemZ.h" 17 #include "SystemZRegisterInfo.h" 18 #include "llvm/ADT/ArrayRef.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include <cstdint> 24 25 #define GET_INSTRINFO_HEADER 26 #include "SystemZGenInstrInfo.inc" 27 28 namespace llvm { 29 30 class SystemZSubtarget; 31 32 namespace SystemZII { 33 34 enum { 35 // See comments in SystemZInstrFormats.td. 36 SimpleBDXLoad = (1 << 0), 37 SimpleBDXStore = (1 << 1), 38 Has20BitOffset = (1 << 2), 39 HasIndex = (1 << 3), 40 Is128Bit = (1 << 4), 41 AccessSizeMask = (31 << 5), 42 AccessSizeShift = 5, 43 CCValuesMask = (15 << 10), 44 CCValuesShift = 10, 45 CompareZeroCCMaskMask = (15 << 14), 46 CompareZeroCCMaskShift = 14, 47 CCMaskFirst = (1 << 18), 48 CCMaskLast = (1 << 19), 49 IsLogical = (1 << 20) 50 }; 51 52 static inline unsigned getAccessSize(unsigned int Flags) { 53 return (Flags & AccessSizeMask) >> AccessSizeShift; 54 } 55 56 static inline unsigned getCCValues(unsigned int Flags) { 57 return (Flags & CCValuesMask) >> CCValuesShift; 58 } 59 60 static inline unsigned getCompareZeroCCMask(unsigned int Flags) { 61 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift; 62 } 63 64 // SystemZ MachineOperand target flags. 65 enum { 66 // Masks out the bits for the access model. 67 MO_SYMBOL_MODIFIER = (3 << 0), 68 69 // @GOT (aka @GOTENT) 70 MO_GOT = (1 << 0), 71 72 // @INDNTPOFF 73 MO_INDNTPOFF = (2 << 0) 74 }; 75 76 // Classifies a branch. 77 enum BranchType { 78 // An instruction that branches on the current value of CC. 79 BranchNormal, 80 81 // An instruction that peforms a 32-bit signed comparison and branches 82 // on the result. 83 BranchC, 84 85 // An instruction that peforms a 32-bit unsigned comparison and branches 86 // on the result. 87 BranchCL, 88 89 // An instruction that peforms a 64-bit signed comparison and branches 90 // on the result. 91 BranchCG, 92 93 // An instruction that peforms a 64-bit unsigned comparison and branches 94 // on the result. 95 BranchCLG, 96 97 // An instruction that decrements a 32-bit register and branches if 98 // the result is nonzero. 99 BranchCT, 100 101 // An instruction that decrements a 64-bit register and branches if 102 // the result is nonzero. 103 BranchCTG, 104 105 // An instruction representing an asm goto statement. 106 AsmGoto 107 }; 108 109 // Information about a branch instruction. 110 class Branch { 111 // The target of the branch. In case of INLINEASM_BR, this is nullptr. 112 const MachineOperand *Target; 113 114 public: 115 // The type of the branch. 116 BranchType Type; 117 118 // CCMASK_<N> is set if CC might be equal to N. 119 unsigned CCValid; 120 121 // CCMASK_<N> is set if the branch should be taken when CC == N. 122 unsigned CCMask; 123 124 Branch(BranchType type, unsigned ccValid, unsigned ccMask, 125 const MachineOperand *target) 126 : Target(target), Type(type), CCValid(ccValid), CCMask(ccMask) {} 127 128 bool isIndirect() { return Target != nullptr && Target->isReg(); } 129 bool hasMBBTarget() { return Target != nullptr && Target->isMBB(); } 130 MachineBasicBlock *getMBBTarget() { 131 return hasMBBTarget() ? Target->getMBB() : nullptr; 132 } 133 }; 134 135 // Kinds of fused compares in compare-and-* instructions. Together with type 136 // of the converted compare, this identifies the compare-and-* 137 // instruction. 138 enum FusedCompareType { 139 // Relative branch - CRJ etc. 140 CompareAndBranch, 141 142 // Indirect branch, used for return - CRBReturn etc. 143 CompareAndReturn, 144 145 // Indirect branch, used for sibcall - CRBCall etc. 146 CompareAndSibcall, 147 148 // Trap 149 CompareAndTrap 150 }; 151 152 } // end namespace SystemZII 153 154 namespace SystemZ { 155 int getTwoOperandOpcode(uint16_t Opcode); 156 int getTargetMemOpcode(uint16_t Opcode); 157 } 158 159 class SystemZInstrInfo : public SystemZGenInstrInfo { 160 const SystemZRegisterInfo RI; 161 SystemZSubtarget &STI; 162 163 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const; 164 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const; 165 void expandRIPseudo(MachineInstr &MI, unsigned LowOpcode, unsigned HighOpcode, 166 bool ConvertHigh) const; 167 void expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode, 168 unsigned LowOpcodeK, unsigned HighOpcode) const; 169 void expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode, 170 unsigned HighOpcode) const; 171 void expandLOCPseudo(MachineInstr &MI, unsigned LowOpcode, 172 unsigned HighOpcode) const; 173 void expandLOCRPseudo(MachineInstr &MI, unsigned LowOpcode, 174 unsigned HighOpcode) const; 175 void expandSELRPseudo(MachineInstr &MI, unsigned LowOpcode, 176 unsigned HighOpcode, unsigned MixedOpcode) const; 177 void expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode, 178 unsigned Size) const; 179 void expandLoadStackGuard(MachineInstr *MI) const; 180 181 MachineInstrBuilder 182 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 183 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 184 unsigned LowLowOpcode, unsigned Size, bool KillSrc, 185 bool UndefSrc) const; 186 187 virtual void anchor(); 188 189 protected: 190 /// Commutes the operands in the given instruction by changing the operands 191 /// order and/or changing the instruction's opcode and/or the immediate value 192 /// operand. 193 /// 194 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands 195 /// to be commuted. 196 /// 197 /// Do not call this method for a non-commutable instruction or 198 /// non-commutable operands. 199 /// Even though the instruction is commutable, the method may still 200 /// fail to commute the operands, null pointer is returned in such cases. 201 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 202 unsigned CommuteOpIdx1, 203 unsigned CommuteOpIdx2) const override; 204 205 public: 206 explicit SystemZInstrInfo(SystemZSubtarget &STI); 207 208 // Override TargetInstrInfo. 209 unsigned isLoadFromStackSlot(const MachineInstr &MI, 210 int &FrameIndex) const override; 211 unsigned isStoreToStackSlot(const MachineInstr &MI, 212 int &FrameIndex) const override; 213 bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, 214 int &SrcFrameIndex) const override; 215 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 216 MachineBasicBlock *&FBB, 217 SmallVectorImpl<MachineOperand> &Cond, 218 bool AllowModify) const override; 219 unsigned removeBranch(MachineBasicBlock &MBB, 220 int *BytesRemoved = nullptr) const override; 221 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 222 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 223 const DebugLoc &DL, 224 int *BytesAdded = nullptr) const override; 225 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, 226 unsigned &SrcReg2, int &Mask, int &Value) const override; 227 bool canInsertSelect(const MachineBasicBlock&, ArrayRef<MachineOperand> Cond, 228 unsigned, unsigned, int&, int&, int&) const override; 229 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 230 const DebugLoc &DL, unsigned DstReg, 231 ArrayRef<MachineOperand> Cond, unsigned TrueReg, 232 unsigned FalseReg) const override; 233 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg, 234 MachineRegisterInfo *MRI) const override; 235 bool isPredicable(const MachineInstr &MI) const override; 236 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 237 unsigned ExtraPredCycles, 238 BranchProbability Probability) const override; 239 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 240 unsigned NumCyclesT, unsigned ExtraPredCyclesT, 241 MachineBasicBlock &FMBB, 242 unsigned NumCyclesF, unsigned ExtraPredCyclesF, 243 BranchProbability Probability) const override; 244 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 245 BranchProbability Probability) const override; 246 bool PredicateInstruction(MachineInstr &MI, 247 ArrayRef<MachineOperand> Pred) const override; 248 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 249 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 250 bool KillSrc) const override; 251 void storeRegToStackSlot(MachineBasicBlock &MBB, 252 MachineBasicBlock::iterator MBBI, 253 unsigned SrcReg, bool isKill, int FrameIndex, 254 const TargetRegisterClass *RC, 255 const TargetRegisterInfo *TRI) const override; 256 void loadRegFromStackSlot(MachineBasicBlock &MBB, 257 MachineBasicBlock::iterator MBBI, 258 unsigned DestReg, int FrameIdx, 259 const TargetRegisterClass *RC, 260 const TargetRegisterInfo *TRI) const override; 261 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 262 MachineInstr &MI, 263 LiveVariables *LV) const override; 264 MachineInstr * 265 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, 266 ArrayRef<unsigned> Ops, 267 MachineBasicBlock::iterator InsertPt, int FrameIndex, 268 LiveIntervals *LIS = nullptr, 269 VirtRegMap *VRM = nullptr) const override; 270 MachineInstr *foldMemoryOperandImpl( 271 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, 272 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, 273 LiveIntervals *LIS = nullptr) const override; 274 bool expandPostRAPseudo(MachineInstr &MBBI) const override; 275 bool reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const 276 override; 277 278 // Return the SystemZRegisterInfo, which this class owns. 279 const SystemZRegisterInfo &getRegisterInfo() const { return RI; } 280 281 // Return the size in bytes of MI. 282 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 283 284 // Return true if MI is a conditional or unconditional branch. 285 // When returning true, set Cond to the mask of condition-code 286 // values on which the instruction will branch, and set Target 287 // to the operand that contains the branch target. This target 288 // can be a register or a basic block. 289 SystemZII::Branch getBranchInfo(const MachineInstr &MI) const; 290 291 // Get the load and store opcodes for a given register class. 292 void getLoadStoreOpcodes(const TargetRegisterClass *RC, 293 unsigned &LoadOpcode, unsigned &StoreOpcode) const; 294 295 // Opcode is the opcode of an instruction that has an address operand, 296 // and the caller wants to perform that instruction's operation on an 297 // address that has displacement Offset. Return the opcode of a suitable 298 // instruction (which might be Opcode itself) or 0 if no such instruction 299 // exists. 300 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const; 301 302 // If Opcode is a load instruction that has a LOAD AND TEST form, 303 // return the opcode for the testing form, otherwise return 0. 304 unsigned getLoadAndTest(unsigned Opcode) const; 305 306 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits 307 // Mask of the R2 operand, given that only the low BitSize bits of Mask are 308 // significant. Set Start and End to the I3 and I4 operands if so. 309 bool isRxSBGMask(uint64_t Mask, unsigned BitSize, 310 unsigned &Start, unsigned &End) const; 311 312 // If Opcode is a COMPARE opcode for which an associated fused COMPARE AND * 313 // operation exists, return the opcode for the latter, otherwise return 0. 314 // MI, if nonnull, is the compare instruction. 315 unsigned getFusedCompare(unsigned Opcode, 316 SystemZII::FusedCompareType Type, 317 const MachineInstr *MI = nullptr) const; 318 319 // If Opcode is a LOAD opcode for with an associated LOAD AND TRAP 320 // operation exists, returh the opcode for the latter, otherwise return 0. 321 unsigned getLoadAndTrap(unsigned Opcode) const; 322 323 // Emit code before MBBI in MI to move immediate value Value into 324 // physical register Reg. 325 void loadImmediate(MachineBasicBlock &MBB, 326 MachineBasicBlock::iterator MBBI, 327 unsigned Reg, uint64_t Value) const; 328 329 // Sometimes, it is possible for the target to tell, even without 330 // aliasing information, that two MIs access different memory 331 // addresses. This function returns true if two MIs access different 332 // memory addresses and false otherwise. 333 bool 334 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 335 const MachineInstr &MIb, 336 AliasAnalysis *AA = nullptr) const override; 337 }; 338 339 } // end namespace llvm 340 341 #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H 342