1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Basic SystemZ instruction definition 11//===----------------------------------------------------------------------===// 12 13class InstSystemZ<int size, dag outs, dag ins, string asmstr, 14 list<dag> pattern> : Instruction { 15 let Namespace = "SystemZ"; 16 17 dag OutOperandList = outs; 18 dag InOperandList = ins; 19 let Size = size; 20 let Pattern = pattern; 21 let AsmString = asmstr; 22 23 let hasSideEffects = 0; 24 let mayLoad = 0; 25 let mayStore = 0; 26 27 // Some instructions come in pairs, one having a 12-bit displacement 28 // and the other having a 20-bit displacement. Both instructions in 29 // the pair have the same DispKey and their DispSizes are "12" and "20" 30 // respectively. 31 string DispKey = ""; 32 string DispSize = "none"; 33 34 // Many register-based <INSN>R instructions have a memory-based <INSN> 35 // counterpart. OpKey uniquely identifies <INSN>R, while OpType is 36 // "reg" for <INSN>R and "mem" for <INSN>. 37 string OpKey = ""; 38 string OpType = "none"; 39 40 // MemKey identifies a targe reg-mem opcode, while MemType can be either 41 // "pseudo" or "target". This is used to map a pseduo memory instruction to 42 // its corresponding target opcode. See comment at MemFoldPseudo. 43 string MemKey = ""; 44 string MemType = "none"; 45 46 // Many distinct-operands instructions have older 2-operand equivalents. 47 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs, 48 // with NumOpsValue being "2" or "3" as appropriate. 49 string NumOpsKey = ""; 50 string NumOpsValue = "none"; 51 52 // True if this instruction is a simple D(X,B) load of a register 53 // (with no sign or zero extension). 54 bit SimpleBDXLoad = 0; 55 56 // True if this instruction is a simple D(X,B) store of a register 57 // (with no truncation). 58 bit SimpleBDXStore = 0; 59 60 // True if this instruction has a 20-bit displacement field. 61 bit Has20BitOffset = 0; 62 63 // True if addresses in this instruction have an index register. 64 bit HasIndex = 0; 65 66 // True if this is a 128-bit pseudo instruction that combines two 64-bit 67 // operations. 68 bit Is128Bit = 0; 69 70 // The access size of all memory operands in bytes, or 0 if not known. 71 bits<5> AccessBytes = 0; 72 73 // If the instruction sets CC to a useful value, this gives the mask 74 // of all possible CC results. The mask has the same form as 75 // SystemZ::CCMASK_*. 76 bits<4> CCValues = 0; 77 78 // The subset of CCValues that have the same meaning as they would after a 79 // comparison of the first operand against zero. "Logical" instructions 80 // leave this blank as they set CC in a different way. 81 bits<4> CompareZeroCCMask = 0; 82 83 // True if the instruction is conditional and if the CC mask operand 84 // comes first (as for BRC, etc.). 85 bit CCMaskFirst = 0; 86 87 // Similar, but true if the CC mask operand comes last (as for LOC, etc.). 88 bit CCMaskLast = 0; 89 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 92 // instruction sets this flag along with a non-zero CCValues field, it is 93 // assumed to set CC to either CCMASK_LOGICAL_ZERO or 94 // CCMASK_LOGICAL_NONZERO. 95 bit IsLogical = 0; 96 97 // True if the (add or sub) instruction sets CC like a compare of the 98 // result against zero, but only if the 'nsw' flag is set. 99 bit CCIfNoSignedWrap = 0; 100 101 let TSFlags{0} = SimpleBDXLoad; 102 let TSFlags{1} = SimpleBDXStore; 103 let TSFlags{2} = Has20BitOffset; 104 let TSFlags{3} = HasIndex; 105 let TSFlags{4} = Is128Bit; 106 let TSFlags{9-5} = AccessBytes; 107 let TSFlags{13-10} = CCValues; 108 let TSFlags{17-14} = CompareZeroCCMask; 109 let TSFlags{18} = CCMaskFirst; 110 let TSFlags{19} = CCMaskLast; 111 let TSFlags{20} = IsLogical; 112 let TSFlags{21} = CCIfNoSignedWrap; 113} 114 115//===----------------------------------------------------------------------===// 116// Mappings between instructions 117//===----------------------------------------------------------------------===// 118 119// Return the version of an instruction that has an unsigned 12-bit 120// displacement. 121def getDisp12Opcode : InstrMapping { 122 let FilterClass = "InstSystemZ"; 123 let RowFields = ["DispKey"]; 124 let ColFields = ["DispSize"]; 125 let KeyCol = ["20"]; 126 let ValueCols = [["12"]]; 127} 128 129// Return the version of an instruction that has a signed 20-bit displacement. 130def getDisp20Opcode : InstrMapping { 131 let FilterClass = "InstSystemZ"; 132 let RowFields = ["DispKey"]; 133 let ColFields = ["DispSize"]; 134 let KeyCol = ["12"]; 135 let ValueCols = [["20"]]; 136} 137 138// Return the memory form of a register instruction. Note that this may 139// return a MemFoldPseudo instruction (see below). 140def getMemOpcode : InstrMapping { 141 let FilterClass = "InstSystemZ"; 142 let RowFields = ["OpKey"]; 143 let ColFields = ["OpType"]; 144 let KeyCol = ["reg"]; 145 let ValueCols = [["mem"]]; 146} 147 148// Return the target memory instruction for a MemFoldPseudo. 149def getTargetMemOpcode : InstrMapping { 150 let FilterClass = "InstSystemZ"; 151 let RowFields = ["MemKey"]; 152 let ColFields = ["MemType"]; 153 let KeyCol = ["pseudo"]; 154 let ValueCols = [["target"]]; 155} 156 157// Return the 2-operand form of a 3-operand instruction. 158def getTwoOperandOpcode : InstrMapping { 159 let FilterClass = "InstSystemZ"; 160 let RowFields = ["NumOpsKey"]; 161 let ColFields = ["NumOpsValue"]; 162 let KeyCol = ["3"]; 163 let ValueCols = [["2"]]; 164} 165 166//===----------------------------------------------------------------------===// 167// Instruction formats 168//===----------------------------------------------------------------------===// 169// 170// Formats are specified using operand field declarations of the form: 171// 172// bits<4> Rn : register input or output for operand n 173// bits<5> Vn : vector register input or output for operand n 174// bits<m> In : immediate value of width m for operand n 175// bits<4> BDn : address operand n, which has a base and a displacement 176// bits<m> XBDn : address operand n, which has an index, a base and a 177// displacement 178// bits<m> VBDn : address operand n, which has a vector index, a base and a 179// displacement 180// bits<4> Xn : index register for address operand n 181// bits<4> Mn : mode value for operand n 182// 183// The operand numbers ("n" in the list above) follow the architecture manual. 184// Assembly operands sometimes have a different order; in particular, R3 often 185// is often written between operands 1 and 2. 186// 187//===----------------------------------------------------------------------===// 188 189class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 190 : InstSystemZ<2, outs, ins, asmstr, pattern> { 191 field bits<16> Inst; 192 field bits<16> SoftFail = 0; 193 194 let Inst = op; 195} 196 197class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 198 : InstSystemZ<2, outs, ins, asmstr, pattern> { 199 field bits<16> Inst; 200 field bits<16> SoftFail = 0; 201 202 bits<8> I1; 203 204 let Inst{15-8} = op; 205 let Inst{7-0} = I1; 206} 207 208class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 209 : InstSystemZ<4, outs, ins, asmstr, pattern> { 210 field bits<32> Inst; 211 field bits<32> SoftFail = 0; 212 213 bits<4> I1; 214 bits<4> I2; 215 216 let Inst{31-16} = op; 217 let Inst{15-8} = 0; 218 let Inst{7-4} = I1; 219 let Inst{3-0} = I2; 220} 221 222class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 223 : InstSystemZ<6, outs, ins, asmstr, pattern> { 224 field bits<48> Inst; 225 field bits<48> SoftFail = 0; 226 227 bits<4> M1; 228 bits<12> RI2; 229 bits<24> RI3; 230 231 let Inst{47-40} = op; 232 let Inst{39-36} = M1; 233 let Inst{35-24} = RI2; 234 let Inst{23-0} = RI3; 235} 236 237class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 238 : InstSystemZ<4, outs, ins, asmstr, pattern> { 239 field bits<32> Inst; 240 field bits<32> SoftFail = 0; 241 242 bits<4> R1; 243 bits<16> I2; 244 245 let Inst{31-24} = op{11-4}; 246 let Inst{23-20} = R1; 247 let Inst{19-16} = op{3-0}; 248 let Inst{15-0} = I2; 249} 250 251class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 252 : InstSystemZ<4, outs, ins, asmstr, pattern> { 253 field bits<32> Inst; 254 field bits<32> SoftFail = 0; 255 256 bits<4> R1; 257 bits<16> RI2; 258 259 let Inst{31-24} = op{11-4}; 260 let Inst{23-20} = R1; 261 let Inst{19-16} = op{3-0}; 262 let Inst{15-0} = RI2; 263} 264 265class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 266 : InstSystemZ<4, outs, ins, asmstr, pattern> { 267 field bits<32> Inst; 268 field bits<32> SoftFail = 0; 269 270 bits<4> M1; 271 bits<16> RI2; 272 273 let Inst{31-24} = op{11-4}; 274 let Inst{23-20} = M1; 275 let Inst{19-16} = op{3-0}; 276 let Inst{15-0} = RI2; 277} 278 279class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 280 : InstSystemZ<6, outs, ins, asmstr, pattern> { 281 field bits<48> Inst; 282 field bits<48> SoftFail = 0; 283 284 bits<4> R1; 285 bits<16> I2; 286 bits<4> M3; 287 288 let Inst{47-40} = op{15-8}; 289 let Inst{39-36} = R1; 290 let Inst{35-32} = 0; 291 let Inst{31-16} = I2; 292 let Inst{15-12} = M3; 293 let Inst{11-8} = 0; 294 let Inst{7-0} = op{7-0}; 295} 296 297class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 298 : InstSystemZ<6, outs, ins, asmstr, pattern> { 299 field bits<48> Inst; 300 field bits<48> SoftFail = 0; 301 302 bits<4> R1; 303 bits<4> R2; 304 bits<4> M3; 305 bits<16> RI4; 306 307 let Inst{47-40} = op{15-8}; 308 let Inst{39-36} = R1; 309 let Inst{35-32} = R2; 310 let Inst{31-16} = RI4; 311 let Inst{15-12} = M3; 312 let Inst{11-8} = 0; 313 let Inst{7-0} = op{7-0}; 314} 315 316class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 317 : InstSystemZ<6, outs, ins, asmstr, pattern> { 318 field bits<48> Inst; 319 field bits<48> SoftFail = 0; 320 321 bits<4> R1; 322 bits<8> I2; 323 bits<4> M3; 324 bits<16> RI4; 325 326 let Inst{47-40} = op{15-8}; 327 let Inst{39-36} = R1; 328 let Inst{35-32} = M3; 329 let Inst{31-16} = RI4; 330 let Inst{15-8} = I2; 331 let Inst{7-0} = op{7-0}; 332} 333 334class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 335 : InstSystemZ<6, outs, ins, asmstr, pattern> { 336 field bits<48> Inst; 337 field bits<48> SoftFail = 0; 338 339 bits<4> R1; 340 bits<4> R3; 341 bits<16> I2; 342 343 let Inst{47-40} = op{15-8}; 344 let Inst{39-36} = R1; 345 let Inst{35-32} = R3; 346 let Inst{31-16} = I2; 347 let Inst{15-8} = 0; 348 let Inst{7-0} = op{7-0}; 349} 350 351class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 352 : InstSystemZ<6, outs, ins, asmstr, pattern> { 353 field bits<48> Inst; 354 field bits<48> SoftFail = 0; 355 356 bits<4> R1; 357 bits<4> R3; 358 bits<16> RI2; 359 360 let Inst{47-40} = op{15-8}; 361 let Inst{39-36} = R1; 362 let Inst{35-32} = R3; 363 let Inst{31-16} = RI2; 364 let Inst{15-8} = 0; 365 let Inst{7-0} = op{7-0}; 366} 367 368class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 369 : InstSystemZ<6, outs, ins, asmstr, pattern> { 370 field bits<48> Inst; 371 field bits<48> SoftFail = 0; 372 373 bits<4> R1; 374 bits<4> R2; 375 bits<8> I3; 376 bits<8> I4; 377 bits<8> I5; 378 379 let Inst{47-40} = op{15-8}; 380 let Inst{39-36} = R1; 381 let Inst{35-32} = R2; 382 let Inst{31-24} = I3; 383 let Inst{23-16} = I4; 384 let Inst{15-8} = I5; 385 let Inst{7-0} = op{7-0}; 386} 387 388class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 389 : InstSystemZ<6, outs, ins, asmstr, pattern> { 390 field bits<48> Inst; 391 field bits<48> SoftFail = 0; 392 393 bits<4> R1; 394 bits<4> M3; 395 bits<16> I2; 396 397 let Inst{47-40} = op{15-8}; 398 let Inst{39-36} = R1; 399 let Inst{35-32} = M3; 400 let Inst{31-16} = I2; 401 let Inst{15-8} = 0; 402 let Inst{7-0} = op{7-0}; 403} 404 405class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 406 : InstSystemZ<6, outs, ins, asmstr, pattern> { 407 field bits<48> Inst; 408 field bits<48> SoftFail = 0; 409 410 bits<4> R1; 411 bits<32> I2; 412 413 let Inst{47-40} = op{11-4}; 414 let Inst{39-36} = R1; 415 let Inst{35-32} = op{3-0}; 416 let Inst{31-0} = I2; 417} 418 419class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 420 : InstSystemZ<6, outs, ins, asmstr, pattern> { 421 field bits<48> Inst; 422 field bits<48> SoftFail = 0; 423 424 bits<4> R1; 425 bits<32> RI2; 426 427 let Inst{47-40} = op{11-4}; 428 let Inst{39-36} = R1; 429 let Inst{35-32} = op{3-0}; 430 let Inst{31-0} = RI2; 431} 432 433class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 434 : InstSystemZ<6, outs, ins, asmstr, pattern> { 435 field bits<48> Inst; 436 field bits<48> SoftFail = 0; 437 438 bits<4> M1; 439 bits<32> RI2; 440 441 let Inst{47-40} = op{11-4}; 442 let Inst{39-36} = M1; 443 let Inst{35-32} = op{3-0}; 444 let Inst{31-0} = RI2; 445} 446 447class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 448 : InstSystemZ<6, outs, ins, asmstr, pattern> { 449 field bits<48> Inst; 450 field bits<48> SoftFail = 0; 451 452 bits<4> R1; 453 bits<8> I2; 454 bits<4> M3; 455 bits<16> BD4; 456 457 let Inst{47-40} = op{15-8}; 458 let Inst{39-36} = R1; 459 let Inst{35-32} = M3; 460 let Inst{31-16} = BD4; 461 let Inst{15-8} = I2; 462 let Inst{7-0} = op{7-0}; 463} 464 465class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 466 : InstSystemZ<2, outs, ins, asmstr, pattern> { 467 field bits<16> Inst; 468 field bits<16> SoftFail = 0; 469 470 bits<4> R1; 471 bits<4> R2; 472 473 let Inst{15-8} = op; 474 let Inst{7-4} = R1; 475 let Inst{3-0} = R2; 476} 477 478class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 479 : InstSystemZ<4, outs, ins, asmstr, pattern> { 480 field bits<32> Inst; 481 field bits<32> SoftFail = 0; 482 483 bits<4> R1; 484 bits<4> R3; 485 bits<4> R2; 486 487 let Inst{31-16} = op; 488 let Inst{15-12} = R1; 489 let Inst{11-8} = 0; 490 let Inst{7-4} = R3; 491 let Inst{3-0} = R2; 492} 493 494class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 495 : InstSystemZ<4, outs, ins, asmstr, pattern> { 496 field bits<32> Inst; 497 field bits<32> SoftFail = 0; 498 499 bits<4> R1; 500 bits<4> R2; 501 502 let Inst{31-16} = op; 503 let Inst{15-8} = 0; 504 let Inst{7-4} = R1; 505 let Inst{3-0} = R2; 506} 507 508class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 509 : InstSystemZ<4, outs, ins, asmstr, pattern> { 510 field bits<32> Inst; 511 field bits<32> SoftFail = 0; 512 513 bits<4> R1; 514 bits<4> R2; 515 bits<4> R3; 516 bits<4> M4; 517 518 let Inst{31-16} = op; 519 let Inst{15-12} = R3; 520 let Inst{11-8} = M4; 521 let Inst{7-4} = R1; 522 let Inst{3-0} = R2; 523} 524 525class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 526 : InstSystemZ<4, outs, ins, asmstr, pattern> { 527 field bits<32> Inst; 528 field bits<32> SoftFail = 0; 529 530 bits<4> R1; 531 bits<4> R2; 532 bits<4> R3; 533 bits<4> M4; 534 535 let Inst{31-16} = op; 536 let Inst{15-12} = R3; 537 let Inst{11-8} = M4; 538 let Inst{7-4} = R1; 539 let Inst{3-0} = R2; 540} 541 542class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 543 : InstSystemZ<4, outs, ins, asmstr, pattern> { 544 field bits<32> Inst; 545 field bits<32> SoftFail = 0; 546 547 bits<4> R1; 548 bits<4> R2; 549 bits<4> M3; 550 551 let Inst{31-16} = op; 552 let Inst{15-12} = M3; 553 let Inst{11-8} = 0; 554 let Inst{7-4} = R1; 555 let Inst{3-0} = R2; 556} 557 558class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 559 : InstSystemZ<4, outs, ins, asmstr, pattern> { 560 field bits<32> Inst; 561 field bits<32> SoftFail = 0; 562 563 bits<4> R1; 564 bits<4> R2; 565 bits<4> M4; 566 567 let Inst{31-16} = op; 568 let Inst{15-12} = 0; 569 let Inst{11-8} = M4; 570 let Inst{7-4} = R1; 571 let Inst{3-0} = R2; 572} 573 574class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 575 : InstSystemZ<4, outs, ins, asmstr, pattern> { 576 field bits<32> Inst; 577 field bits<32> SoftFail = 0; 578 579 bits<4> R1; 580 bits<4> R2; 581 bits<4> M3; 582 bits<4> M4; 583 584 let Inst{31-16} = op; 585 let Inst{15-12} = M3; 586 let Inst{11-8} = M4; 587 let Inst{7-4} = R1; 588 let Inst{3-0} = R2; 589} 590 591class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 592 : InstSystemZ<6, outs, ins, asmstr, pattern> { 593 field bits<48> Inst; 594 field bits<48> SoftFail = 0; 595 596 bits<4> R1; 597 bits<4> R2; 598 bits<4> M3; 599 bits<16> BD4; 600 601 let Inst{47-40} = op{15-8}; 602 let Inst{39-36} = R1; 603 let Inst{35-32} = R2; 604 let Inst{31-16} = BD4; 605 let Inst{15-12} = M3; 606 let Inst{11-8} = 0; 607 let Inst{7-0} = op{7-0}; 608} 609 610class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 611 : InstSystemZ<4, outs, ins, asmstr, pattern> { 612 field bits<32> Inst; 613 field bits<32> SoftFail = 0; 614 615 bits<4> R1; 616 bits<20> XBD2; 617 618 let Inst{31-24} = op; 619 let Inst{23-20} = R1; 620 let Inst{19-0} = XBD2; 621 622 let HasIndex = 1; 623} 624 625class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 626 : InstSystemZ<4, outs, ins, asmstr, pattern> { 627 field bits<32> Inst; 628 field bits<32> SoftFail = 0; 629 630 bits<4> M1; 631 bits<20> XBD2; 632 633 let Inst{31-24} = op; 634 let Inst{23-20} = M1; 635 let Inst{19-0} = XBD2; 636 637 let HasIndex = 1; 638} 639 640class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 641 : InstSystemZ<6, outs, ins, asmstr, pattern> { 642 field bits<48> Inst; 643 field bits<48> SoftFail = 0; 644 645 bits<4> R1; 646 bits<20> XBD2; 647 bits<4> M3; 648 649 let Inst{47-40} = op{15-8}; 650 let Inst{39-36} = R1; 651 let Inst{35-16} = XBD2; 652 let Inst{15-12} = M3; 653 let Inst{11-8} = 0; 654 let Inst{7-0} = op{7-0}; 655 656 let HasIndex = 1; 657} 658 659class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 660 : InstSystemZ<6, outs, ins, asmstr, pattern> { 661 field bits<48> Inst; 662 field bits<48> SoftFail = 0; 663 664 bits<4> R1; 665 bits<4> R3; 666 bits<20> XBD2; 667 668 let Inst{47-40} = op{15-8}; 669 let Inst{39-36} = R3; 670 let Inst{35-16} = XBD2; 671 let Inst{15-12} = R1; 672 let Inst{11-8} = 0; 673 let Inst{7-0} = op{7-0}; 674 675 let HasIndex = 1; 676} 677 678class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 679 : InstSystemZ<6, outs, ins, asmstr, pattern> { 680 field bits<48> Inst; 681 field bits<48> SoftFail = 0; 682 683 bits<4> R1; 684 bits<28> XBD2; 685 686 let Inst{47-40} = op{15-8}; 687 let Inst{39-36} = R1; 688 let Inst{35-8} = XBD2; 689 let Inst{7-0} = op{7-0}; 690 691 let Has20BitOffset = 1; 692 let HasIndex = 1; 693} 694 695class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 696 : InstSystemZ<6, outs, ins, asmstr, pattern> { 697 field bits<48> Inst; 698 field bits<48> SoftFail = 0; 699 700 bits<4> M1; 701 bits<28> XBD2; 702 703 let Inst{47-40} = op{15-8}; 704 let Inst{39-36} = M1; 705 let Inst{35-8} = XBD2; 706 let Inst{7-0} = op{7-0}; 707 708 let Has20BitOffset = 1; 709 let HasIndex = 1; 710} 711 712class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 713 : InstSystemZ<4, outs, ins, asmstr, pattern> { 714 field bits<32> Inst; 715 field bits<32> SoftFail = 0; 716 717 bits<4> R1; 718 bits<4> R3; 719 bits<16> BD2; 720 721 let Inst{31-24} = op; 722 let Inst{23-20} = R1; 723 let Inst{19-16} = R3; 724 let Inst{15-0} = BD2; 725} 726 727class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 728 : InstSystemZ<4, outs, ins, asmstr, pattern> { 729 field bits<32> Inst; 730 field bits<32> SoftFail = 0; 731 732 bits<4> R1; 733 bits<4> M3; 734 bits<16> BD2; 735 736 let Inst{31-24} = op; 737 let Inst{23-20} = R1; 738 let Inst{19-16} = M3; 739 let Inst{15-0} = BD2; 740} 741 742class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 743 : InstSystemZ<4, outs, ins, asmstr, pattern> { 744 field bits<32> Inst; 745 field bits<32> SoftFail = 0; 746 747 bits<4> R1; 748 bits<4> R3; 749 bits<16> RI2; 750 751 let Inst{31-24} = op; 752 let Inst{23-20} = R1; 753 let Inst{19-16} = R3; 754 let Inst{15-0} = RI2; 755} 756 757class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 758 : InstSystemZ<6, outs, ins, asmstr, pattern> { 759 field bits<48> Inst; 760 field bits<48> SoftFail = 0; 761 762 bits<20> BDL1; 763 764 let Inst{47-40} = op{15-8}; 765 let Inst{39-36} = BDL1{19-16}; 766 let Inst{35-32} = 0; 767 let Inst{31-16} = BDL1{15-0}; 768 let Inst{15-8} = 0; 769 let Inst{7-0} = op{7-0}; 770} 771 772class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 773 : InstSystemZ<6, outs, ins, asmstr, pattern> { 774 field bits<48> Inst; 775 field bits<48> SoftFail = 0; 776 777 bits<4> R1; 778 bits<24> BDL2; 779 bits<4> M3; 780 781 let Inst{47-40} = op{15-8}; 782 let Inst{39-16} = BDL2; 783 let Inst{15-12} = R1; 784 let Inst{11-8} = M3; 785 let Inst{7-0} = op{7-0}; 786} 787 788class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 789 : InstSystemZ<6, outs, ins, asmstr, pattern> { 790 field bits<48> Inst; 791 field bits<48> SoftFail = 0; 792 793 bits<4> R1; 794 bits<4> R3; 795 bits<24> BD2; 796 797 let Inst{47-40} = op{15-8}; 798 let Inst{39-36} = R1; 799 let Inst{35-32} = R3; 800 let Inst{31-8} = BD2; 801 let Inst{7-0} = op{7-0}; 802 803 let Has20BitOffset = 1; 804} 805 806class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 807 : InstSystemZ<6, outs, ins, asmstr, pattern> { 808 field bits<48> Inst; 809 field bits<48> SoftFail = 0; 810 811 bits<4> R1; 812 bits<4> M3; 813 bits<24> BD2; 814 815 let Inst{47-40} = op{15-8}; 816 let Inst{39-36} = R1; 817 let Inst{35-32} = M3; 818 let Inst{31-8} = BD2; 819 let Inst{7-0} = op{7-0}; 820 821 let Has20BitOffset = 1; 822} 823 824class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 825 : InstSystemZ<4, outs, ins, asmstr, pattern> { 826 field bits<32> Inst; 827 field bits<32> SoftFail = 0; 828 829 bits<16> BD1; 830 bits<8> I2; 831 832 let Inst{31-24} = op; 833 let Inst{23-16} = I2; 834 let Inst{15-0} = BD1; 835} 836 837class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 838 : InstSystemZ<6, outs, ins, asmstr, pattern> { 839 field bits<48> Inst; 840 field bits<48> SoftFail = 0; 841 842 bits<16> BD1; 843 bits<16> I2; 844 845 let Inst{47-32} = op; 846 let Inst{31-16} = BD1; 847 let Inst{15-0} = I2; 848} 849 850class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 851 : InstSystemZ<6, outs, ins, asmstr, pattern> { 852 field bits<48> Inst; 853 field bits<48> SoftFail = 0; 854 855 bits<24> BD1; 856 bits<8> I2; 857 858 let Inst{47-40} = op{15-8}; 859 let Inst{39-32} = I2; 860 let Inst{31-8} = BD1; 861 let Inst{7-0} = op{7-0}; 862 863 let Has20BitOffset = 1; 864} 865 866class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 867 : InstSystemZ<6, outs, ins, asmstr, pattern> { 868 field bits<48> Inst; 869 field bits<48> SoftFail = 0; 870 871 bits<4> M1; 872 bits<16> RI2; 873 bits<16> BD3; 874 875 let Inst{47-40} = op; 876 let Inst{39-36} = M1; 877 let Inst{35-32} = 0; 878 let Inst{31-16} = BD3; 879 let Inst{15-0} = RI2; 880} 881 882class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 883 : InstSystemZ<6, outs, ins, asmstr, pattern> { 884 field bits<48> Inst; 885 field bits<48> SoftFail = 0; 886 887 bits<24> BDL1; 888 bits<16> BD2; 889 890 let Inst{47-40} = op; 891 let Inst{39-16} = BDL1; 892 let Inst{15-0} = BD2; 893} 894 895class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 896 : InstSystemZ<6, outs, ins, asmstr, pattern> { 897 field bits<48> Inst; 898 field bits<48> SoftFail = 0; 899 900 bits<20> BDL1; 901 bits<20> BDL2; 902 903 let Inst{47-40} = op; 904 let Inst{39-36} = BDL1{19-16}; 905 let Inst{35-32} = BDL2{19-16}; 906 let Inst{31-16} = BDL1{15-0}; 907 let Inst{15-0} = BDL2{15-0}; 908} 909 910class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 911 : InstSystemZ<6, outs, ins, asmstr, pattern> { 912 field bits<48> Inst; 913 field bits<48> SoftFail = 0; 914 915 bits<20> BDL1; 916 bits<16> BD2; 917 bits<4> I3; 918 919 let Inst{47-40} = op; 920 let Inst{39-36} = BDL1{19-16}; 921 let Inst{35-32} = I3; 922 let Inst{31-16} = BDL1{15-0}; 923 let Inst{15-0} = BD2; 924} 925 926class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 927 : InstSystemZ<6, outs, ins, asmstr, pattern> { 928 field bits<48> Inst; 929 field bits<48> SoftFail = 0; 930 931 bits<20> RBD1; 932 bits<16> BD2; 933 bits<4> R3; 934 935 let Inst{47-40} = op; 936 let Inst{39-36} = RBD1{19-16}; 937 let Inst{35-32} = R3; 938 let Inst{31-16} = RBD1{15-0}; 939 let Inst{15-0} = BD2; 940} 941 942class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 943 : InstSystemZ<6, outs, ins, asmstr, pattern> { 944 field bits<48> Inst; 945 field bits<48> SoftFail = 0; 946 947 bits<4> R1; 948 bits<16> BD2; 949 bits<4> R3; 950 bits<16> BD4; 951 952 let Inst{47-40} = op; 953 let Inst{39-36} = R1; 954 let Inst{35-32} = R3; 955 let Inst{31-16} = BD2; 956 let Inst{15-0} = BD4; 957} 958 959class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 960 : InstSystemZ<6, outs, ins, asmstr, pattern> { 961 field bits<48> Inst; 962 field bits<48> SoftFail = 0; 963 964 bits<16> BD1; 965 bits<24> BDL2; 966 967 let Inst{47-40} = op; 968 let Inst{39-32} = BDL2{23-16}; 969 let Inst{31-16} = BD1; 970 let Inst{15-0} = BDL2{15-0}; 971} 972 973class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 974 : InstSystemZ<6, outs, ins, asmstr, pattern> { 975 field bits<48> Inst; 976 field bits<48> SoftFail = 0; 977 978 bits<16> BD1; 979 bits<16> BD2; 980 981 let Inst{47-32} = op; 982 let Inst{31-16} = BD1; 983 let Inst{15-0} = BD2; 984} 985 986class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 987 : InstSystemZ<6, outs, ins, asmstr, pattern> { 988 field bits<48> Inst; 989 field bits<48> SoftFail = 0; 990 991 bits<16> BD1; 992 bits<16> BD2; 993 bits<4> R3; 994 995 let Inst{47-40} = op{11-4}; 996 let Inst{39-36} = R3; 997 let Inst{35-32} = op{3-0}; 998 let Inst{31-16} = BD1; 999 let Inst{15-0} = BD2; 1000} 1001 1002class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1003 : InstSystemZ<4, outs, ins, asmstr, pattern> { 1004 field bits<32> Inst; 1005 field bits<32> SoftFail = 0; 1006 1007 bits<16> BD2; 1008 1009 let Inst{31-16} = op; 1010 let Inst{15-0} = BD2; 1011} 1012 1013class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1014 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1015 field bits<48> Inst; 1016 field bits<48> SoftFail = 0; 1017 1018 bits<5> V1; 1019 bits<16> I2; 1020 bits<4> M3; 1021 1022 let Inst{47-40} = op{15-8}; 1023 let Inst{39-36} = V1{3-0}; 1024 let Inst{35-32} = 0; 1025 let Inst{31-16} = I2; 1026 let Inst{15-12} = M3; 1027 let Inst{11} = V1{4}; 1028 let Inst{10-8} = 0; 1029 let Inst{7-0} = op{7-0}; 1030} 1031 1032class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1033 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1034 field bits<48> Inst; 1035 field bits<48> SoftFail = 0; 1036 1037 bits<5> V1; 1038 bits<8> I2; 1039 bits<8> I3; 1040 bits<4> M4; 1041 1042 let Inst{47-40} = op{15-8}; 1043 let Inst{39-36} = V1{3-0}; 1044 let Inst{35-32} = 0; 1045 let Inst{31-24} = I2; 1046 let Inst{23-16} = I3; 1047 let Inst{15-12} = M4; 1048 let Inst{11} = V1{4}; 1049 let Inst{10-8} = 0; 1050 let Inst{7-0} = op{7-0}; 1051} 1052 1053class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1054 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1055 field bits<48> Inst; 1056 field bits<48> SoftFail = 0; 1057 1058 bits<5> V1; 1059 bits<5> V3; 1060 bits<16> I2; 1061 bits<4> M4; 1062 1063 let Inst{47-40} = op{15-8}; 1064 let Inst{39-36} = V1{3-0}; 1065 let Inst{35-32} = V3{3-0}; 1066 let Inst{31-16} = I2; 1067 let Inst{15-12} = M4; 1068 let Inst{11} = V1{4}; 1069 let Inst{10} = V3{4}; 1070 let Inst{9-8} = 0; 1071 let Inst{7-0} = op{7-0}; 1072} 1073 1074class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1075 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1076 field bits<48> Inst; 1077 field bits<48> SoftFail = 0; 1078 1079 bits<5> V1; 1080 bits<5> V2; 1081 bits<5> V3; 1082 bits<8> I4; 1083 bits<4> M5; 1084 1085 let Inst{47-40} = op{15-8}; 1086 let Inst{39-36} = V1{3-0}; 1087 let Inst{35-32} = V2{3-0}; 1088 let Inst{31-28} = V3{3-0}; 1089 let Inst{27-24} = 0; 1090 let Inst{23-16} = I4; 1091 let Inst{15-12} = M5; 1092 let Inst{11} = V1{4}; 1093 let Inst{10} = V2{4}; 1094 let Inst{9} = V3{4}; 1095 let Inst{8} = 0; 1096 let Inst{7-0} = op{7-0}; 1097} 1098 1099class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1100 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1101 field bits<48> Inst; 1102 field bits<48> SoftFail = 0; 1103 1104 bits<5> V1; 1105 bits<5> V2; 1106 bits<12> I3; 1107 bits<4> M4; 1108 bits<4> M5; 1109 1110 let Inst{47-40} = op{15-8}; 1111 let Inst{39-36} = V1{3-0}; 1112 let Inst{35-32} = V2{3-0}; 1113 let Inst{31-20} = I3; 1114 let Inst{19-16} = M5; 1115 let Inst{15-12} = M4; 1116 let Inst{11} = V1{4}; 1117 let Inst{10} = V2{4}; 1118 let Inst{9-8} = 0; 1119 let Inst{7-0} = op{7-0}; 1120} 1121 1122class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1123 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1124 field bits<48> Inst; 1125 field bits<48> SoftFail = 0; 1126 1127 bits<5> V1; 1128 bits<5> V2; 1129 bits<5> V3; 1130 bits<8> I4; 1131 bits<4> M5; 1132 1133 let Inst{47-40} = op{15-8}; 1134 let Inst{39-36} = V1{3-0}; 1135 let Inst{35-32} = V2{3-0}; 1136 let Inst{31-28} = V3{3-0}; 1137 let Inst{27-24} = 0; 1138 let Inst{23-20} = M5; 1139 let Inst{19-12} = I4; 1140 let Inst{11} = V1{4}; 1141 let Inst{10} = V2{4}; 1142 let Inst{9} = V3{4}; 1143 let Inst{8} = 0; 1144 let Inst{7-0} = op{7-0}; 1145} 1146 1147class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1148 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1149 field bits<48> Inst; 1150 field bits<48> SoftFail = 0; 1151 1152 bits<5> V1; 1153 bits<5> V2; 1154 bits<8> I3; 1155 bits<8> I4; 1156 bits<4> M5; 1157 1158 let Inst{47-40} = op{15-8}; 1159 let Inst{39-36} = V1{3-0}; 1160 let Inst{35-32} = V2{3-0}; 1161 let Inst{31-24} = I4; 1162 let Inst{23-20} = M5; 1163 let Inst{19-12} = I3; 1164 let Inst{11} = V1{4}; 1165 let Inst{10} = V2{4}; 1166 let Inst{9-8} = 0; 1167 let Inst{7-0} = op{7-0}; 1168} 1169 1170class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1171 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1172 field bits<48> Inst; 1173 field bits<48> SoftFail = 0; 1174 1175 bits<5> V1; 1176 bits<16> I2; 1177 bits<4> I3; 1178 1179 let Inst{47-40} = op{15-8}; 1180 let Inst{39-36} = V1{3-0}; 1181 let Inst{35-32} = 0; 1182 let Inst{31-16} = I2; 1183 let Inst{15-12} = I3; 1184 let Inst{11} = V1{4}; 1185 let Inst{10-8} = 0; 1186 let Inst{7-0} = op{7-0}; 1187} 1188 1189class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1190 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1191 field bits<48> Inst; 1192 field bits<48> SoftFail = 0; 1193 1194 bits<5> V1; 1195 bits<4> R2; 1196 bits<8> I3; 1197 bits<4> M4; 1198 1199 let Inst{47-40} = op{15-8}; 1200 let Inst{39-36} = V1{3-0}; 1201 let Inst{35-32} = R2; 1202 let Inst{31-24} = 0; 1203 let Inst{23-20} = M4; 1204 let Inst{19-12} = I3; 1205 let Inst{11} = V1{4}; 1206 let Inst{10-8} = 0; 1207 let Inst{7-0} = op{7-0}; 1208} 1209 1210// Depending on the instruction mnemonic, certain bits may be or-ed into 1211// the M4 value provided as explicit operand. These are passed as m4or. 1212class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1213 bits<4> m4or = 0> 1214 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1215 field bits<48> Inst; 1216 field bits<48> SoftFail = 0; 1217 1218 bits<5> V1; 1219 bits<5> V2; 1220 bits<4> M3; 1221 bits<4> M4; 1222 bits<4> M5; 1223 1224 let Inst{47-40} = op{15-8}; 1225 let Inst{39-36} = V1{3-0}; 1226 let Inst{35-32} = V2{3-0}; 1227 let Inst{31-24} = 0; 1228 let Inst{23-20} = M5; 1229 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3}); 1230 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2}); 1231 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1}); 1232 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0}); 1233 let Inst{15-12} = M3; 1234 let Inst{11} = V1{4}; 1235 let Inst{10} = V2{4}; 1236 let Inst{9-8} = 0; 1237 let Inst{7-0} = op{7-0}; 1238} 1239 1240// Depending on the instruction mnemonic, certain bits may be or-ed into 1241// the M5 value provided as explicit operand. These are passed as m5or. 1242class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1243 bits<4> m5or = 0> 1244 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1245 field bits<48> Inst; 1246 field bits<48> SoftFail = 0; 1247 1248 bits<5> V1; 1249 bits<5> V2; 1250 bits<5> V3; 1251 bits<4> M4; 1252 bits<4> M5; 1253 1254 let Inst{47-40} = op{15-8}; 1255 let Inst{39-36} = V1{3-0}; 1256 let Inst{35-32} = V2{3-0}; 1257 let Inst{31-28} = V3{3-0}; 1258 let Inst{27-24} = 0; 1259 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3}); 1260 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2}); 1261 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1}); 1262 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0}); 1263 let Inst{19-16} = 0; 1264 let Inst{15-12} = M4; 1265 let Inst{11} = V1{4}; 1266 let Inst{10} = V2{4}; 1267 let Inst{9} = V3{4}; 1268 let Inst{8} = 0; 1269 let Inst{7-0} = op{7-0}; 1270} 1271 1272class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1273 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1274 field bits<48> Inst; 1275 field bits<48> SoftFail = 0; 1276 1277 bits<5> V1; 1278 bits<5> V2; 1279 bits<5> V3; 1280 bits<4> M4; 1281 bits<4> M5; 1282 bits<4> M6; 1283 1284 let Inst{47-40} = op{15-8}; 1285 let Inst{39-36} = V1{3-0}; 1286 let Inst{35-32} = V2{3-0}; 1287 let Inst{31-28} = V3{3-0}; 1288 let Inst{27-24} = 0; 1289 let Inst{23-20} = M6; 1290 let Inst{19-16} = M5; 1291 let Inst{15-12} = M4; 1292 let Inst{11} = V1{4}; 1293 let Inst{10} = V2{4}; 1294 let Inst{9} = V3{4}; 1295 let Inst{8} = 0; 1296 let Inst{7-0} = op{7-0}; 1297} 1298 1299// Depending on the instruction mnemonic, certain bits may be or-ed into 1300// the M6 value provided as explicit operand. These are passed as m6or. 1301class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1302 bits<4> m6or = 0> 1303 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1304 field bits<48> Inst; 1305 field bits<48> SoftFail = 0; 1306 1307 bits<5> V1; 1308 bits<5> V2; 1309 bits<5> V3; 1310 bits<5> V4; 1311 bits<4> M5; 1312 bits<4> M6; 1313 1314 let Inst{47-40} = op{15-8}; 1315 let Inst{39-36} = V1{3-0}; 1316 let Inst{35-32} = V2{3-0}; 1317 let Inst{31-28} = V3{3-0}; 1318 let Inst{27-24} = M5; 1319 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3}); 1320 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2}); 1321 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1}); 1322 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0}); 1323 let Inst{19-16} = 0; 1324 let Inst{15-12} = V4{3-0}; 1325 let Inst{11} = V1{4}; 1326 let Inst{10} = V2{4}; 1327 let Inst{9} = V3{4}; 1328 let Inst{8} = V4{4}; 1329 let Inst{7-0} = op{7-0}; 1330} 1331 1332class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1333 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1334 field bits<48> Inst; 1335 field bits<48> SoftFail = 0; 1336 1337 bits<5> V1; 1338 bits<5> V2; 1339 bits<5> V3; 1340 bits<5> V4; 1341 bits<4> M5; 1342 bits<4> M6; 1343 1344 let Inst{47-40} = op{15-8}; 1345 let Inst{39-36} = V1{3-0}; 1346 let Inst{35-32} = V2{3-0}; 1347 let Inst{31-28} = V3{3-0}; 1348 let Inst{27-24} = M6; 1349 let Inst{23-20} = 0; 1350 let Inst{19-16} = M5; 1351 let Inst{15-12} = V4{3-0}; 1352 let Inst{11} = V1{4}; 1353 let Inst{10} = V2{4}; 1354 let Inst{9} = V3{4}; 1355 let Inst{8} = V4{4}; 1356 let Inst{7-0} = op{7-0}; 1357} 1358 1359class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1360 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1361 field bits<48> Inst; 1362 field bits<48> SoftFail = 0; 1363 1364 bits<5> V1; 1365 bits<4> R2; 1366 bits<4> R3; 1367 1368 let Inst{47-40} = op{15-8}; 1369 let Inst{39-36} = V1{3-0}; 1370 let Inst{35-32} = R2; 1371 let Inst{31-28} = R3; 1372 let Inst{27-12} = 0; 1373 let Inst{11} = V1{4}; 1374 let Inst{10-8} = 0; 1375 let Inst{7-0} = op{7-0}; 1376} 1377 1378class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1379 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1380 field bits<48> Inst; 1381 field bits<48> SoftFail = 0; 1382 1383 bits<5> V1; 1384 1385 let Inst{47-40} = op{15-8}; 1386 let Inst{39-36} = 0; 1387 let Inst{35-32} = V1{3-0}; 1388 let Inst{31-12} = 0; 1389 let Inst{11} = 0; 1390 let Inst{10} = V1{4}; 1391 let Inst{9-8} = 0; 1392 let Inst{7-0} = op{7-0}; 1393} 1394 1395class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1396 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1397 field bits<48> Inst; 1398 field bits<48> SoftFail = 0; 1399 1400 bits<5> V1; 1401 bits<5> V2; 1402 bits<4> M3; 1403 1404 let Inst{47-40} = op{15-8}; 1405 let Inst{39-36} = 0; 1406 let Inst{35-32} = V1{3-0}; 1407 let Inst{31-28} = V2{3-0}; 1408 let Inst{27-24} = 0; 1409 let Inst{23-20} = M3; 1410 let Inst{19-12} = 0; 1411 let Inst{11} = 0; 1412 let Inst{10} = V1{4}; 1413 let Inst{9} = V2{4}; 1414 let Inst{8} = 0; 1415 let Inst{7-0} = op{7-0}; 1416} 1417 1418class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1419 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1420 field bits<48> Inst; 1421 field bits<48> SoftFail = 0; 1422 1423 bits<4> R1; 1424 bits<5> V2; 1425 bits<4> M3; 1426 bits<4> M4; 1427 1428 let Inst{47-40} = op{15-8}; 1429 let Inst{39-36} = R1; 1430 let Inst{35-32} = V2{3-0}; 1431 let Inst{31-24} = 0; 1432 let Inst{23-20} = M3; 1433 let Inst{19-16} = M4; 1434 let Inst{15-12} = 0; 1435 let Inst{11} = 0; 1436 let Inst{10} = V2{4}; 1437 let Inst{9-8} = 0; 1438 let Inst{7-0} = op{7-0}; 1439} 1440 1441class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1442 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1443 field bits<48> Inst; 1444 field bits<48> SoftFail = 0; 1445 1446 bits<5> V1; 1447 bits<16> BD2; 1448 bits<5> V3; 1449 bits<4> M4; 1450 1451 let Inst{47-40} = op{15-8}; 1452 let Inst{39-36} = V1{3-0}; 1453 let Inst{35-32} = V3{3-0}; 1454 let Inst{31-16} = BD2; 1455 let Inst{15-12} = M4; 1456 let Inst{11} = V1{4}; 1457 let Inst{10} = V3{4}; 1458 let Inst{9-8} = 0; 1459 let Inst{7-0} = op{7-0}; 1460} 1461 1462class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1463 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1464 field bits<48> Inst; 1465 field bits<48> SoftFail = 0; 1466 1467 bits<5> V1; 1468 bits<16> BD2; 1469 bits<4> R3; 1470 bits<4> M4; 1471 1472 let Inst{47-40} = op{15-8}; 1473 let Inst{39-36} = V1{3-0}; 1474 let Inst{35-32} = R3; 1475 let Inst{31-16} = BD2; 1476 let Inst{15-12} = M4; 1477 let Inst{11} = V1{4}; 1478 let Inst{10-8} = 0; 1479 let Inst{7-0} = op{7-0}; 1480} 1481 1482class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1483 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1484 field bits<48> Inst; 1485 field bits<48> SoftFail = 0; 1486 1487 bits<4> R1; 1488 bits<16> BD2; 1489 bits<5> V3; 1490 bits<4> M4; 1491 1492 let Inst{47-40} = op{15-8}; 1493 let Inst{39-36} = R1; 1494 let Inst{35-32} = V3{3-0}; 1495 let Inst{31-16} = BD2; 1496 let Inst{15-12} = M4; 1497 let Inst{11} = 0; 1498 let Inst{10} = V3{4}; 1499 let Inst{9-8} = 0; 1500 let Inst{7-0} = op{7-0}; 1501} 1502 1503class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1504 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1505 field bits<48> Inst; 1506 field bits<48> SoftFail = 0; 1507 1508 bits<5> V1; 1509 bits<16> BD2; 1510 bits<4> R3; 1511 1512 let Inst{47-40} = op{15-8}; 1513 let Inst{39-36} = 0; 1514 let Inst{35-32} = R3; 1515 let Inst{31-16} = BD2; 1516 let Inst{15-12} = V1{3-0}; 1517 let Inst{11-9} = 0; 1518 let Inst{8} = V1{4}; 1519 let Inst{7-0} = op{7-0}; 1520} 1521 1522class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1523 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1524 field bits<48> Inst; 1525 field bits<48> SoftFail = 0; 1526 1527 bits<5> V1; 1528 bits<21> VBD2; 1529 bits<4> M3; 1530 1531 let Inst{47-40} = op{15-8}; 1532 let Inst{39-36} = V1{3-0}; 1533 let Inst{35-16} = VBD2{19-0}; 1534 let Inst{15-12} = M3; 1535 let Inst{11} = V1{4}; 1536 let Inst{10} = VBD2{20}; 1537 let Inst{9-8} = 0; 1538 let Inst{7-0} = op{7-0}; 1539} 1540 1541class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1542 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1543 field bits<48> Inst; 1544 field bits<48> SoftFail = 0; 1545 1546 bits<5> V1; 1547 bits<20> XBD2; 1548 bits<4> M3; 1549 1550 let Inst{47-40} = op{15-8}; 1551 let Inst{39-36} = V1{3-0}; 1552 let Inst{35-16} = XBD2; 1553 let Inst{15-12} = M3; 1554 let Inst{11} = V1{4}; 1555 let Inst{10-8} = 0; 1556 let Inst{7-0} = op{7-0}; 1557} 1558 1559class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1560 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1561 field bits<48> Inst; 1562 field bits<48> SoftFail = 0; 1563 1564 bits<5> V1; 1565 bits<16> BD2; 1566 bits<8> I3; 1567 1568 let Inst{47-40} = op{15-8}; 1569 let Inst{39-32} = I3; 1570 let Inst{31-16} = BD2; 1571 let Inst{15-12} = V1{3-0}; 1572 let Inst{11-9} = 0; 1573 let Inst{8} = V1{4}; 1574 let Inst{7-0} = op{7-0}; 1575} 1576 1577//===----------------------------------------------------------------------===// 1578// Instruction classes for .insn directives 1579//===----------------------------------------------------------------------===// 1580 1581class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern> 1582 : InstE<0, outs, ins, asmstr, pattern> { 1583 bits<16> enc; 1584 1585 let Inst = enc; 1586} 1587 1588class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern> 1589 : InstRIa<0, outs, ins, asmstr, pattern> { 1590 bits<32> enc; 1591 1592 let Inst{31-24} = enc{31-24}; 1593 let Inst{19-16} = enc{19-16}; 1594} 1595 1596class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern> 1597 : InstRIEd<0, outs, ins, asmstr, pattern> { 1598 bits<48> enc; 1599 1600 let Inst{47-40} = enc{47-40}; 1601 let Inst{7-0} = enc{7-0}; 1602} 1603 1604class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern> 1605 : InstRILa<0, outs, ins, asmstr, pattern> { 1606 bits<48> enc; 1607 string type; 1608 1609 let Inst{47-40} = enc{47-40}; 1610 let Inst{35-32} = enc{35-32}; 1611} 1612 1613class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern> 1614 : InstRIS<0, outs, ins, asmstr, pattern> { 1615 bits<48> enc; 1616 1617 let Inst{47-40} = enc{47-40}; 1618 let Inst{7-0} = enc{7-0}; 1619} 1620 1621class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern> 1622 : InstRR<0, outs, ins, asmstr, pattern> { 1623 bits<16> enc; 1624 1625 let Inst{15-8} = enc{15-8}; 1626} 1627 1628class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern> 1629 : InstRRE<0, outs, ins, asmstr, pattern> { 1630 bits<32> enc; 1631 1632 let Inst{31-16} = enc{31-16}; 1633} 1634 1635class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern> 1636 : InstRRFa<0, outs, ins, asmstr, pattern> { 1637 bits<32> enc; 1638 1639 let Inst{31-16} = enc{31-16}; 1640} 1641 1642class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern> 1643 : InstRRS<0, outs, ins, asmstr, pattern> { 1644 bits<48> enc; 1645 1646 let Inst{47-40} = enc{47-40}; 1647 let Inst{7-0} = enc{7-0}; 1648} 1649 1650class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern> 1651 : InstRSa<0, outs, ins, asmstr, pattern> { 1652 bits<32> enc; 1653 1654 let Inst{31-24} = enc{31-24}; 1655} 1656 1657// RSE is like RSY except with a 12 bit displacement (instead of 20). 1658class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern> 1659 : InstRSYa<6, outs, ins, asmstr, pattern> { 1660 bits <48> enc; 1661 1662 let Inst{47-40} = enc{47-40}; 1663 let Inst{31-16} = BD2{15-0}; 1664 let Inst{15-8} = 0; 1665 let Inst{7-0} = enc{7-0}; 1666} 1667 1668class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern> 1669 : InstRSI<0, outs, ins, asmstr, pattern> { 1670 bits<32> enc; 1671 1672 let Inst{31-24} = enc{31-24}; 1673} 1674 1675class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern> 1676 : InstRSYa<0, outs, ins, asmstr, pattern> { 1677 bits<48> enc; 1678 1679 let Inst{47-40} = enc{47-40}; 1680 let Inst{7-0} = enc{7-0}; 1681} 1682 1683class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern> 1684 : InstRXa<0, outs, ins, asmstr, pattern> { 1685 bits<32> enc; 1686 1687 let Inst{31-24} = enc{31-24}; 1688} 1689 1690class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern> 1691 : InstRXE<0, outs, ins, asmstr, pattern> { 1692 bits<48> enc; 1693 1694 let M3 = 0; 1695 1696 let Inst{47-40} = enc{47-40}; 1697 let Inst{7-0} = enc{7-0}; 1698} 1699 1700class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern> 1701 : InstRXF<0, outs, ins, asmstr, pattern> { 1702 bits<48> enc; 1703 1704 let Inst{47-40} = enc{47-40}; 1705 let Inst{7-0} = enc{7-0}; 1706} 1707 1708class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern> 1709 : InstRXYa<0, outs, ins, asmstr, pattern> { 1710 bits<48> enc; 1711 1712 let Inst{47-40} = enc{47-40}; 1713 let Inst{7-0} = enc{7-0}; 1714} 1715 1716class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern> 1717 : InstS<0, outs, ins, asmstr, pattern> { 1718 bits<32> enc; 1719 1720 let Inst{31-16} = enc{31-16}; 1721} 1722 1723class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern> 1724 : InstSI<0, outs, ins, asmstr, pattern> { 1725 bits<32> enc; 1726 1727 let Inst{31-24} = enc{31-24}; 1728} 1729 1730class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern> 1731 : InstSIY<0, outs, ins, asmstr, pattern> { 1732 bits<48> enc; 1733 1734 let Inst{47-40} = enc{47-40}; 1735 let Inst{7-0} = enc{7-0}; 1736} 1737 1738class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern> 1739 : InstSIL<0, outs, ins, asmstr, pattern> { 1740 bits<48> enc; 1741 1742 let Inst{47-32} = enc{47-32}; 1743} 1744 1745class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern> 1746 : InstSSd<0, outs, ins, asmstr, pattern> { 1747 bits<48> enc; 1748 1749 let Inst{47-40} = enc{47-40}; 1750} 1751 1752class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern> 1753 : InstSSE<0, outs, ins, asmstr, pattern> { 1754 bits<48> enc; 1755 1756 let Inst{47-32} = enc{47-32}; 1757} 1758 1759class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern> 1760 : InstSSF<0, outs, ins, asmstr, pattern> { 1761 bits<48> enc; 1762 1763 let Inst{47-40} = enc{47-40}; 1764 let Inst{35-32} = enc{35-32}; 1765} 1766 1767//===----------------------------------------------------------------------===// 1768// Variants of instructions with condition mask 1769//===----------------------------------------------------------------------===// 1770// 1771// For instructions using a condition mask (e.g. conditional branches, 1772// compare-and-branch instructions, or conditional move instructions), 1773// we generally need to create multiple instruction patterns: 1774// 1775// - One used for code generation, which encodes the condition mask as an 1776// MI operand, but writes out an extended mnemonic for better readability. 1777// - One pattern for the base form of the instruction with an explicit 1778// condition mask (encoded as a plain integer MI operand). 1779// - Specific patterns for each extended mnemonic, where the condition mask 1780// is implied by the pattern name and not otherwise encoded at all. 1781// 1782// We need the latter primarily for the assembler and disassembler, since the 1783// assembler parser is not able to decode part of an instruction mnemonic 1784// into an operand. Thus we provide separate patterns for each mnemonic. 1785// 1786// Note that in some cases there are two different mnemonics for the same 1787// condition mask. In this case we cannot have both instructions available 1788// to the disassembler at the same time since the encodings are not distinct. 1789// Therefore the alternate forms are marked isAsmParserOnly. 1790// 1791// We don't make one of the two names an alias of the other because 1792// we need the custom parsing routines to select the correct register class. 1793// 1794// This section provides helpers for generating the specific forms. 1795// 1796//===----------------------------------------------------------------------===// 1797 1798// A class to describe a variant of an instruction with condition mask. 1799class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> { 1800 // The fixed condition mask to use. 1801 bits<4> ccmask = ccmaskin; 1802 1803 // The suffix to use for the extended assembler mnemonic. 1804 string suffix = suffixin; 1805 1806 // Whether this is an alternate that needs to be marked isAsmParserOnly. 1807 bit alternate = alternatein; 1808} 1809 1810// Condition mask 15 means "always true", which is used to define 1811// unconditional branches as a variant of conditional branches. 1812def CondAlways : CondVariant<15, "", 0>; 1813 1814// Condition masks for general instructions that can set all 4 bits. 1815def CondVariantO : CondVariant<1, "o", 0>; 1816def CondVariantH : CondVariant<2, "h", 0>; 1817def CondVariantP : CondVariant<2, "p", 1>; 1818def CondVariantNLE : CondVariant<3, "nle", 0>; 1819def CondVariantL : CondVariant<4, "l", 0>; 1820def CondVariantM : CondVariant<4, "m", 1>; 1821def CondVariantNHE : CondVariant<5, "nhe", 0>; 1822def CondVariantLH : CondVariant<6, "lh", 0>; 1823def CondVariantNE : CondVariant<7, "ne", 0>; 1824def CondVariantNZ : CondVariant<7, "nz", 1>; 1825def CondVariantE : CondVariant<8, "e", 0>; 1826def CondVariantZ : CondVariant<8, "z", 1>; 1827def CondVariantNLH : CondVariant<9, "nlh", 0>; 1828def CondVariantHE : CondVariant<10, "he", 0>; 1829def CondVariantNL : CondVariant<11, "nl", 0>; 1830def CondVariantNM : CondVariant<11, "nm", 1>; 1831def CondVariantLE : CondVariant<12, "le", 0>; 1832def CondVariantNH : CondVariant<13, "nh", 0>; 1833def CondVariantNP : CondVariant<13, "np", 1>; 1834def CondVariantNO : CondVariant<14, "no", 0>; 1835 1836// A helper class to look up one of the above by name. 1837class CV<string name> 1838 : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask, 1839 !cast<CondVariant>("CondVariant"#name).suffix, 1840 !cast<CondVariant>("CondVariant"#name).alternate>; 1841 1842// Condition masks for integer instructions (e.g. compare-and-branch). 1843// This is like the list above, except that condition 3 is not possible 1844// and that the low bit of the mask is therefore always 0. This means 1845// that each condition has two names. Conditions "o" and "no" are not used. 1846def IntCondVariantH : CondVariant<2, "h", 0>; 1847def IntCondVariantNLE : CondVariant<2, "nle", 1>; 1848def IntCondVariantL : CondVariant<4, "l", 0>; 1849def IntCondVariantNHE : CondVariant<4, "nhe", 1>; 1850def IntCondVariantLH : CondVariant<6, "lh", 0>; 1851def IntCondVariantNE : CondVariant<6, "ne", 1>; 1852def IntCondVariantE : CondVariant<8, "e", 0>; 1853def IntCondVariantNLH : CondVariant<8, "nlh", 1>; 1854def IntCondVariantHE : CondVariant<10, "he", 0>; 1855def IntCondVariantNL : CondVariant<10, "nl", 1>; 1856def IntCondVariantLE : CondVariant<12, "le", 0>; 1857def IntCondVariantNH : CondVariant<12, "nh", 1>; 1858 1859// A helper class to look up one of the above by name. 1860class ICV<string name> 1861 : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask, 1862 !cast<CondVariant>("IntCondVariant"#name).suffix, 1863 !cast<CondVariant>("IntCondVariant"#name).alternate>; 1864 1865//===----------------------------------------------------------------------===// 1866// Instruction definitions with semantics 1867//===----------------------------------------------------------------------===// 1868// 1869// These classes have the form [Cond]<Category><Format>, where <Format> is one 1870// of the formats defined above and where <Category> describes the inputs 1871// and outputs. "Cond" is used if the instruction is conditional, 1872// in which case the 4-bit condition-code mask is added as a final operand. 1873// <Category> can be one of: 1874// 1875// Inherent: 1876// One register output operand and no input operands. 1877// 1878// InherentDual: 1879// Two register output operands and no input operands. 1880// 1881// StoreInherent: 1882// One address operand. The instruction stores to the address. 1883// 1884// SideEffectInherent: 1885// No input or output operands, but causes some side effect. 1886// 1887// Branch: 1888// One branch target. The instruction branches to the target. 1889// 1890// Call: 1891// One output operand and one branch target. The instruction stores 1892// the return address to the output operand and branches to the target. 1893// 1894// CmpBranch: 1895// Two input operands and one optional branch target. The instruction 1896// compares the two input operands and branches or traps on the result. 1897// 1898// BranchUnary: 1899// One register output operand, one register input operand and one branch 1900// target. The instructions stores a modified form of the source register 1901// in the destination register and branches on the result. 1902// 1903// BranchBinary: 1904// One register output operand, two register input operands and one branch 1905// target. The instructions stores a modified form of one of the source 1906// registers in the destination register and branches on the result. 1907// 1908// LoadMultiple: 1909// One address input operand and two explicit output operands. 1910// The instruction loads a range of registers from the address, 1911// with the explicit operands giving the first and last register 1912// to load. Other loaded registers are added as implicit definitions. 1913// 1914// StoreMultiple: 1915// Two explicit input register operands and an address operand. 1916// The instruction stores a range of registers to the address, 1917// with the explicit operands giving the first and last register 1918// to store. Other stored registers are added as implicit uses. 1919// 1920// StoreLength: 1921// One value operand, one length operand and one address operand. 1922// The instruction stores the value operand to the address but 1923// doesn't write more than the number of bytes specified by the 1924// length operand. 1925// 1926// LoadAddress: 1927// One register output operand and one address operand. 1928// 1929// SideEffectAddress: 1930// One address operand. No output operands, but causes some side effect. 1931// 1932// Unary: 1933// One register output operand and one input operand. 1934// 1935// Store: 1936// One address operand and one other input operand. The instruction 1937// stores to the address. 1938// 1939// SideEffectUnary: 1940// One input operand. No output operands, but causes some side effect. 1941// 1942// Binary: 1943// One register output operand and two input operands. 1944// 1945// StoreBinary: 1946// One address operand and two other input operands. The instruction 1947// stores to the address. 1948// 1949// SideEffectBinary: 1950// Two input operands. No output operands, but causes some side effect. 1951// 1952// Compare: 1953// Two input operands and an implicit CC output operand. 1954// 1955// Test: 1956// One or two input operands and an implicit CC output operand. If 1957// present, the second input operand is an "address" operand used as 1958// a test class mask. 1959// 1960// Ternary: 1961// One register output operand and three input operands. 1962// 1963// SideEffectTernary: 1964// Three input operands. No output operands, but causes some side effect. 1965// 1966// Quaternary: 1967// One register output operand and four input operands. 1968// 1969// LoadAndOp: 1970// One output operand and two input operands, one of which is an address. 1971// The instruction both reads from and writes to the address. 1972// 1973// CmpSwap: 1974// One output operand and three input operands, one of which is an address. 1975// The instruction both reads from and writes to the address. 1976// 1977// RotateSelect: 1978// One output operand and five input operands. The first two operands 1979// are registers and the other three are immediates. 1980// 1981// Prefetch: 1982// One 4-bit immediate operand and one address operand. The immediate 1983// operand is 1 for a load prefetch and 2 for a store prefetch. 1984// 1985// BranchPreload: 1986// One 4-bit immediate operand and two address operands. 1987// 1988// The format determines which input operands are tied to output operands, 1989// and also determines the shape of any address operand. 1990// 1991// Multiclasses of the form <Category><Format>Pair define two instructions, 1992// one with <Category><Format> and one with <Category><Format>Y. The name 1993// of the first instruction has no suffix, the name of the second has 1994// an extra "y". 1995// 1996//===----------------------------------------------------------------------===// 1997 1998class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 1999 SDPatternOperator operator> 2000 : InstRRE<opcode, (outs cls:$R1), (ins), 2001 mnemonic#"\t$R1", 2002 [(set cls:$R1, (operator))]> { 2003 let R2 = 0; 2004} 2005 2006class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 2007 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins), 2008 mnemonic#"\t$R1, $R2", []>; 2009 2010class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value> 2011 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> { 2012 let I2 = value; 2013 let M3 = 0; 2014} 2015 2016class StoreInherentS<string mnemonic, bits<16> opcode, 2017 SDPatternOperator operator, bits<5> bytes> 2018 : InstS<opcode, (outs), (ins bdaddr12only:$BD2), 2019 mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> { 2020 let mayStore = 1; 2021 let AccessBytes = bytes; 2022} 2023 2024class SideEffectInherentE<string mnemonic, bits<16>opcode> 2025 : InstE<opcode, (outs), (ins), mnemonic, []>; 2026 2027class SideEffectInherentS<string mnemonic, bits<16> opcode, 2028 SDPatternOperator operator> 2029 : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> { 2030 let BD2 = 0; 2031} 2032 2033class SideEffectInherentRRE<string mnemonic, bits<16> opcode> 2034 : InstRRE<opcode, (outs), (ins), mnemonic, []> { 2035 let R1 = 0; 2036 let R2 = 0; 2037} 2038 2039// Allow an optional TLS marker symbol to generate TLS call relocations. 2040class CallRI<string mnemonic, bits<12> opcode> 2041 : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2), 2042 mnemonic#"\t$R1, $RI2", []>; 2043 2044// Allow an optional TLS marker symbol to generate TLS call relocations. 2045class CallRIL<string mnemonic, bits<12> opcode> 2046 : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2), 2047 mnemonic#"\t$R1, $RI2", []>; 2048 2049class CallRR<string mnemonic, bits<8> opcode> 2050 : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2), 2051 mnemonic#"\t$R1, $R2", []>; 2052 2053class CallRX<string mnemonic, bits<8> opcode> 2054 : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2), 2055 mnemonic#"\t$R1, $XBD2", []>; 2056 2057class CondBranchRI<string mnemonic, bits<12> opcode, 2058 SDPatternOperator operator = null_frag> 2059 : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2), 2060 !subst("#", "${M1}", mnemonic)#"\t$RI2", 2061 [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> { 2062 let CCMaskFirst = 1; 2063} 2064 2065class AsmCondBranchRI<string mnemonic, bits<12> opcode> 2066 : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2), 2067 mnemonic#"\t$M1, $RI2", []>; 2068 2069class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode, 2070 SDPatternOperator operator = null_frag> 2071 : InstRIc<opcode, (outs), (ins brtarget16:$RI2), 2072 !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> { 2073 let isAsmParserOnly = V.alternate; 2074 let M1 = V.ccmask; 2075} 2076 2077class CondBranchRIL<string mnemonic, bits<12> opcode> 2078 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2), 2079 !subst("#", "${M1}", mnemonic)#"\t$RI2", []> { 2080 let CCMaskFirst = 1; 2081} 2082 2083class AsmCondBranchRIL<string mnemonic, bits<12> opcode> 2084 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2), 2085 mnemonic#"\t$M1, $RI2", []>; 2086 2087class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode> 2088 : InstRILc<opcode, (outs), (ins brtarget32:$RI2), 2089 !subst("#", V.suffix, mnemonic)#"\t$RI2", []> { 2090 let isAsmParserOnly = V.alternate; 2091 let M1 = V.ccmask; 2092} 2093 2094class CondBranchRR<string mnemonic, bits<8> opcode> 2095 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2), 2096 !subst("#", "${R1}", mnemonic)#"\t$R2", []> { 2097 let CCMaskFirst = 1; 2098} 2099 2100class AsmCondBranchRR<string mnemonic, bits<8> opcode> 2101 : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2), 2102 mnemonic#"\t$R1, $R2", []>; 2103 2104class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode, 2105 SDPatternOperator operator = null_frag> 2106 : InstRR<opcode, (outs), (ins ADDR64:$R2), 2107 !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> { 2108 let isAsmParserOnly = V.alternate; 2109 let R1 = V.ccmask; 2110} 2111 2112class CondBranchRX<string mnemonic, bits<8> opcode> 2113 : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2), 2114 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> { 2115 let CCMaskFirst = 1; 2116} 2117 2118class AsmCondBranchRX<string mnemonic, bits<8> opcode> 2119 : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2), 2120 mnemonic#"\t$M1, $XBD2", []>; 2121 2122class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode> 2123 : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2), 2124 !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> { 2125 let isAsmParserOnly = V.alternate; 2126 let M1 = V.ccmask; 2127} 2128 2129class CondBranchRXY<string mnemonic, bits<16> opcode> 2130 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2), 2131 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> { 2132 let CCMaskFirst = 1; 2133 let mayLoad = 1; 2134} 2135 2136class AsmCondBranchRXY<string mnemonic, bits<16> opcode> 2137 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2), 2138 mnemonic#"\t$M1, $XBD2", []> { 2139 let mayLoad = 1; 2140} 2141 2142class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode, 2143 SDPatternOperator operator = null_frag> 2144 : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2), 2145 !subst("#", V.suffix, mnemonic)#"\t$XBD2", 2146 [(operator (load bdxaddr20only:$XBD2))]> { 2147 let isAsmParserOnly = V.alternate; 2148 let M1 = V.ccmask; 2149 let mayLoad = 1; 2150} 2151 2152class CmpBranchRIEa<string mnemonic, bits<16> opcode, 2153 RegisterOperand cls, ImmOpWithPattern imm> 2154 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3), 2155 mnemonic#"$M3\t$R1, $I2", []>; 2156 2157class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode, 2158 RegisterOperand cls, ImmOpWithPattern imm> 2159 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3), 2160 mnemonic#"\t$R1, $I2, $M3", []>; 2161 2162class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode, 2163 RegisterOperand cls, ImmOpWithPattern imm> 2164 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2), 2165 mnemonic#V.suffix#"\t$R1, $I2", []> { 2166 let isAsmParserOnly = V.alternate; 2167 let M3 = V.ccmask; 2168} 2169 2170multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode, 2171 RegisterOperand cls, ImmOpWithPattern imm> { 2172 let isCodeGenOnly = 1 in 2173 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>; 2174 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>; 2175} 2176 2177class CmpBranchRIEb<string mnemonic, bits<16> opcode, 2178 RegisterOperand cls> 2179 : InstRIEb<opcode, (outs), 2180 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4), 2181 mnemonic#"$M3\t$R1, $R2, $RI4", []>; 2182 2183class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode, 2184 RegisterOperand cls> 2185 : InstRIEb<opcode, (outs), 2186 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4), 2187 mnemonic#"\t$R1, $R2, $M3, $RI4", []>; 2188 2189class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode, 2190 RegisterOperand cls> 2191 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4), 2192 mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> { 2193 let isAsmParserOnly = V.alternate; 2194 let M3 = V.ccmask; 2195} 2196 2197multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode, 2198 RegisterOperand cls> { 2199 let isCodeGenOnly = 1 in 2200 def "" : CmpBranchRIEb<mnemonic, opcode, cls>; 2201 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>; 2202} 2203 2204class CmpBranchRIEc<string mnemonic, bits<16> opcode, 2205 RegisterOperand cls, ImmOpWithPattern imm> 2206 : InstRIEc<opcode, (outs), 2207 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4), 2208 mnemonic#"$M3\t$R1, $I2, $RI4", []>; 2209 2210class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode, 2211 RegisterOperand cls, ImmOpWithPattern imm> 2212 : InstRIEc<opcode, (outs), 2213 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4), 2214 mnemonic#"\t$R1, $I2, $M3, $RI4", []>; 2215 2216class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode, 2217 RegisterOperand cls, ImmOpWithPattern imm> 2218 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4), 2219 mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> { 2220 let isAsmParserOnly = V.alternate; 2221 let M3 = V.ccmask; 2222} 2223 2224multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode, 2225 RegisterOperand cls, ImmOpWithPattern imm> { 2226 let isCodeGenOnly = 1 in 2227 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>; 2228 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>; 2229} 2230 2231class CmpBranchRRFc<string mnemonic, bits<16> opcode, 2232 RegisterOperand cls> 2233 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3), 2234 mnemonic#"$M3\t$R1, $R2", []>; 2235 2236class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode, 2237 RegisterOperand cls> 2238 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3), 2239 mnemonic#"\t$R1, $R2, $M3", []>; 2240 2241multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode, 2242 RegisterOperand cls> { 2243 let isCodeGenOnly = 1 in 2244 def "" : CmpBranchRRFc<mnemonic, opcode, cls>; 2245 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>; 2246} 2247 2248class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode, 2249 RegisterOperand cls> 2250 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2), 2251 mnemonic#V.suffix#"\t$R1, $R2", []> { 2252 let isAsmParserOnly = V.alternate; 2253 let M3 = V.ccmask; 2254} 2255 2256class CmpBranchRRS<string mnemonic, bits<16> opcode, 2257 RegisterOperand cls> 2258 : InstRRS<opcode, (outs), 2259 (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4), 2260 mnemonic#"$M3\t$R1, $R2, $BD4", []>; 2261 2262class AsmCmpBranchRRS<string mnemonic, bits<16> opcode, 2263 RegisterOperand cls> 2264 : InstRRS<opcode, (outs), 2265 (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4), 2266 mnemonic#"\t$R1, $R2, $M3, $BD4", []>; 2267 2268class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode, 2269 RegisterOperand cls> 2270 : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4), 2271 mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> { 2272 let isAsmParserOnly = V.alternate; 2273 let M3 = V.ccmask; 2274} 2275 2276multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode, 2277 RegisterOperand cls> { 2278 let isCodeGenOnly = 1 in 2279 def "" : CmpBranchRRS<mnemonic, opcode, cls>; 2280 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>; 2281} 2282 2283class CmpBranchRIS<string mnemonic, bits<16> opcode, 2284 RegisterOperand cls, ImmOpWithPattern imm> 2285 : InstRIS<opcode, (outs), 2286 (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4), 2287 mnemonic#"$M3\t$R1, $I2, $BD4", []>; 2288 2289class AsmCmpBranchRIS<string mnemonic, bits<16> opcode, 2290 RegisterOperand cls, ImmOpWithPattern imm> 2291 : InstRIS<opcode, (outs), 2292 (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4), 2293 mnemonic#"\t$R1, $I2, $M3, $BD4", []>; 2294 2295class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode, 2296 RegisterOperand cls, ImmOpWithPattern imm> 2297 : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4), 2298 mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> { 2299 let isAsmParserOnly = V.alternate; 2300 let M3 = V.ccmask; 2301} 2302 2303multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode, 2304 RegisterOperand cls, ImmOpWithPattern imm> { 2305 let isCodeGenOnly = 1 in 2306 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>; 2307 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>; 2308} 2309 2310class CmpBranchRSYb<string mnemonic, bits<16> opcode, 2311 RegisterOperand cls> 2312 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3), 2313 mnemonic#"$M3\t$R1, $BD2", []>; 2314 2315class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode, 2316 RegisterOperand cls> 2317 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3), 2318 mnemonic#"\t$R1, $M3, $BD2", []>; 2319 2320multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode, 2321 RegisterOperand cls> { 2322 let isCodeGenOnly = 1 in 2323 def "" : CmpBranchRSYb<mnemonic, opcode, cls>; 2324 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>; 2325} 2326 2327class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode, 2328 RegisterOperand cls> 2329 : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2), 2330 mnemonic#V.suffix#"\t$R1, $BD2", []> { 2331 let isAsmParserOnly = V.alternate; 2332 let M3 = V.ccmask; 2333} 2334 2335class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls> 2336 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2), 2337 mnemonic##"\t$R1, $RI2", []> { 2338 let Constraints = "$R1 = $R1src"; 2339 let DisableEncoding = "$R1src"; 2340} 2341 2342class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls> 2343 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2), 2344 mnemonic##"\t$R1, $RI2", []> { 2345 let Constraints = "$R1 = $R1src"; 2346 let DisableEncoding = "$R1src"; 2347} 2348 2349class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls> 2350 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2), 2351 mnemonic##"\t$R1, $R2", []> { 2352 let Constraints = "$R1 = $R1src"; 2353 let DisableEncoding = "$R1src"; 2354} 2355 2356class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 2357 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2), 2358 mnemonic##"\t$R1, $R2", []> { 2359 let Constraints = "$R1 = $R1src"; 2360 let DisableEncoding = "$R1src"; 2361} 2362 2363class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls> 2364 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2), 2365 mnemonic##"\t$R1, $XBD2", []> { 2366 let Constraints = "$R1 = $R1src"; 2367 let DisableEncoding = "$R1src"; 2368} 2369 2370class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls> 2371 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2), 2372 mnemonic##"\t$R1, $XBD2", []> { 2373 let Constraints = "$R1 = $R1src"; 2374 let DisableEncoding = "$R1src"; 2375} 2376 2377class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls> 2378 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2), 2379 mnemonic##"\t$R1, $R3, $RI2", []> { 2380 let Constraints = "$R1 = $R1src"; 2381 let DisableEncoding = "$R1src"; 2382} 2383 2384class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls> 2385 : InstRIEe<opcode, (outs cls:$R1), 2386 (ins cls:$R1src, cls:$R3, brtarget16:$RI2), 2387 mnemonic##"\t$R1, $R3, $RI2", []> { 2388 let Constraints = "$R1 = $R1src"; 2389 let DisableEncoding = "$R1src"; 2390} 2391 2392class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls> 2393 : InstRSa<opcode, (outs cls:$R1), 2394 (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2), 2395 mnemonic##"\t$R1, $R3, $BD2", []> { 2396 let Constraints = "$R1 = $R1src"; 2397 let DisableEncoding = "$R1src"; 2398} 2399 2400class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 2401 : InstRSYa<opcode, 2402 (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2), 2403 mnemonic##"\t$R1, $R3, $BD2", []> { 2404 let Constraints = "$R1 = $R1src"; 2405 let DisableEncoding = "$R1src"; 2406} 2407 2408class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 2409 AddressingMode mode = bdaddr12only> 2410 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2), 2411 mnemonic#"\t$R1, $R3, $BD2", []> { 2412 let mayLoad = 1; 2413} 2414 2415class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 2416 AddressingMode mode = bdaddr20only> 2417 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2), 2418 mnemonic#"\t$R1, $R3, $BD2", []> { 2419 let mayLoad = 1; 2420} 2421 2422multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode, 2423 bits<16> rsyOpcode, RegisterOperand cls> { 2424 let DispKey = mnemonic ## #cls in { 2425 let DispSize = "12" in 2426 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>; 2427 let DispSize = "20" in 2428 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>; 2429 } 2430} 2431 2432class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls> 2433 : InstSSe<opcode, (outs cls:$R1, cls:$R3), 2434 (ins bdaddr12only:$BD2, bdaddr12only:$BD4), 2435 mnemonic#"\t$R1, $R3, $BD2, $BD4", []> { 2436 let mayLoad = 1; 2437} 2438 2439multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> { 2440 let mayLoad = 1 in { 2441 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), 2442 (ins bdaddr12only:$BD2, imm32zx4:$M4), 2443 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 2444 let M4 = 0 in 2445 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), 2446 (ins bdaddr12only:$BD2), 2447 mnemonic#"\t$V1, $V3, $BD2", []>; 2448 } 2449} 2450 2451class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 2452 RegisterOperand cls> 2453 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 2454 mnemonic#"\t$R1, $RI2", 2455 [(operator cls:$R1, pcrel32:$RI2)]> { 2456 let mayStore = 1; 2457 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 2458 // However, BDXs have two extra operands and are therefore 6 units more 2459 // complex. 2460 let AddedComplexity = 7; 2461} 2462 2463class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2464 RegisterOperand cls, bits<5> bytes, 2465 AddressingMode mode = bdxaddr12only> 2466 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2), 2467 mnemonic#"\t$R1, $XBD2", 2468 [(operator cls:$R1, mode:$XBD2)]> { 2469 let OpKey = mnemonic#"r"#cls; 2470 let OpType = "mem"; 2471 let mayStore = 1; 2472 let AccessBytes = bytes; 2473} 2474 2475class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2476 RegisterOperand cls, bits<5> bytes, 2477 AddressingMode mode = bdxaddr20only> 2478 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2), 2479 mnemonic#"\t$R1, $XBD2", 2480 [(operator cls:$R1, mode:$XBD2)]> { 2481 let OpKey = mnemonic#"r"#cls; 2482 let OpType = "mem"; 2483 let mayStore = 1; 2484 let AccessBytes = bytes; 2485} 2486 2487multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 2488 SDPatternOperator operator, RegisterOperand cls, 2489 bits<5> bytes> { 2490 let DispKey = mnemonic ## #cls in { 2491 let DispSize = "12" in 2492 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 2493 let DispSize = "20" in 2494 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 2495 bdxaddr20pair>; 2496 } 2497} 2498 2499class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2500 TypedReg tr, bits<5> bytes, bits<4> type = 0> 2501 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2), 2502 mnemonic#"\t$V1, $XBD2", 2503 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2)]> { 2504 let M3 = type; 2505 let mayStore = 1; 2506 let AccessBytes = bytes; 2507} 2508 2509class StoreVRXGeneric<string mnemonic, bits<16> opcode> 2510 : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3), 2511 mnemonic#"\t$V1, $XBD2, $M3", []> { 2512 let mayStore = 1; 2513} 2514 2515multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> { 2516 let mayStore = 1, AccessBytes = 16 in { 2517 def Align : InstVRX<opcode, (outs), 2518 (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3), 2519 mnemonic#"\t$V1, $XBD2, $M3", []>; 2520 let M3 = 0 in 2521 def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2), 2522 mnemonic#"\t$V1, $XBD2", []>; 2523 } 2524} 2525 2526class StoreLengthVRSb<string mnemonic, bits<16> opcode, 2527 SDPatternOperator operator, bits<5> bytes> 2528 : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2), 2529 mnemonic#"\t$V1, $R3, $BD2", 2530 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 2531 let M4 = 0; 2532 let mayStore = 1; 2533 let AccessBytes = bytes; 2534} 2535 2536class StoreLengthVRSd<string mnemonic, bits<16> opcode, 2537 SDPatternOperator operator, bits<5> bytes> 2538 : InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2), 2539 mnemonic#"\t$V1, $R3, $BD2", 2540 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 2541 let mayStore = 1; 2542 let AccessBytes = bytes; 2543} 2544 2545class StoreLengthVSI<string mnemonic, bits<16> opcode, 2546 SDPatternOperator operator, bits<5> bytes> 2547 : InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3), 2548 mnemonic#"\t$V1, $BD2, $I3", 2549 [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> { 2550 let mayStore = 1; 2551 let AccessBytes = bytes; 2552} 2553 2554class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 2555 AddressingMode mode = bdaddr12only> 2556 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2), 2557 mnemonic#"\t$R1, $R3, $BD2", []> { 2558 let mayStore = 1; 2559} 2560 2561class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 2562 AddressingMode mode = bdaddr20only> 2563 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2), 2564 mnemonic#"\t$R1, $R3, $BD2", []> { 2565 let mayStore = 1; 2566} 2567 2568multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode, 2569 bits<16> rsyOpcode, RegisterOperand cls> { 2570 let DispKey = mnemonic ## #cls in { 2571 let DispSize = "12" in 2572 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>; 2573 let DispSize = "20" in 2574 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>; 2575 } 2576} 2577 2578multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> { 2579 let mayStore = 1 in { 2580 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, 2581 bdaddr12only:$BD2, imm32zx4:$M4), 2582 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 2583 let M4 = 0 in 2584 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, 2585 bdaddr12only:$BD2), 2586 mnemonic#"\t$V1, $V3, $BD2", []>; 2587 } 2588} 2589 2590// StoreSI* instructions are used to store an integer to memory, but the 2591// addresses are more restricted than for normal stores. If we are in the 2592// situation of having to force either the address into a register or the 2593// constant into a register, it's usually better to do the latter. 2594// We therefore match the address in the same way as a normal store and 2595// only use the StoreSI* instruction if the matched address is suitable. 2596class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2597 ImmOpWithPattern imm> 2598 : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2), 2599 mnemonic#"\t$BD1, $I2", 2600 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 2601 let mayStore = 1; 2602} 2603 2604class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2605 ImmOpWithPattern imm> 2606 : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2), 2607 mnemonic#"\t$BD1, $I2", 2608 [(operator imm:$I2, mviaddr20pair:$BD1)]> { 2609 let mayStore = 1; 2610} 2611 2612class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2613 ImmOpWithPattern imm> 2614 : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2), 2615 mnemonic#"\t$BD1, $I2", 2616 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 2617 let mayStore = 1; 2618} 2619 2620multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 2621 SDPatternOperator operator, ImmOpWithPattern imm> { 2622 let DispKey = mnemonic in { 2623 let DispSize = "12" in 2624 def "" : StoreSI<mnemonic, siOpcode, operator, imm>; 2625 let DispSize = "20" in 2626 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>; 2627 } 2628} 2629 2630class StoreSSE<string mnemonic, bits<16> opcode> 2631 : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2), 2632 mnemonic#"\t$BD1, $BD2", []> { 2633 let mayStore = 1; 2634} 2635 2636class CondStoreRSY<string mnemonic, bits<16> opcode, 2637 RegisterOperand cls, bits<5> bytes, 2638 AddressingMode mode = bdaddr20only> 2639 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3), 2640 mnemonic#"$M3\t$R1, $BD2", []> { 2641 let mayStore = 1; 2642 let AccessBytes = bytes; 2643 let CCMaskLast = 1; 2644} 2645 2646// Like CondStoreRSY, but used for the raw assembly form. The condition-code 2647// mask is the third operand rather than being part of the mnemonic. 2648class AsmCondStoreRSY<string mnemonic, bits<16> opcode, 2649 RegisterOperand cls, bits<5> bytes, 2650 AddressingMode mode = bdaddr20only> 2651 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3), 2652 mnemonic#"\t$R1, $BD2, $M3", []> { 2653 let mayStore = 1; 2654 let AccessBytes = bytes; 2655} 2656 2657// Like CondStoreRSY, but with a fixed CC mask. 2658class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode, 2659 RegisterOperand cls, bits<5> bytes, 2660 AddressingMode mode = bdaddr20only> 2661 : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2), 2662 mnemonic#V.suffix#"\t$R1, $BD2", []> { 2663 let mayStore = 1; 2664 let AccessBytes = bytes; 2665 let isAsmParserOnly = V.alternate; 2666 let M3 = V.ccmask; 2667} 2668 2669multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode, 2670 RegisterOperand cls, bits<5> bytes, 2671 AddressingMode mode = bdaddr20only> { 2672 let isCodeGenOnly = 1 in 2673 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>; 2674 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>; 2675} 2676 2677class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm> 2678 : InstI<opcode, (outs), (ins imm:$I1), 2679 mnemonic#"\t$I1", []>; 2680 2681class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls> 2682 : InstRR<opcode, (outs), (ins cls:$R1), 2683 mnemonic#"\t$R1", []> { 2684 let R2 = 0; 2685} 2686 2687class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 2688 SDPatternOperator operator> 2689 : InstRRE<opcode, (outs), (ins cls:$R1), 2690 mnemonic#"\t$R1", [(operator cls:$R1)]> { 2691 let R2 = 0; 2692} 2693 2694class SideEffectUnaryS<string mnemonic, bits<16> opcode, 2695 SDPatternOperator operator, bits<5> bytes, 2696 AddressingMode mode = bdaddr12only> 2697 : InstS<opcode, (outs), (ins mode:$BD2), 2698 mnemonic#"\t$BD2", [(operator mode:$BD2)]> { 2699 let mayLoad = 1; 2700 let AccessBytes = bytes; 2701} 2702 2703class SideEffectAddressS<string mnemonic, bits<16> opcode, 2704 SDPatternOperator operator, 2705 AddressingMode mode = bdaddr12only> 2706 : InstS<opcode, (outs), (ins mode:$BD2), 2707 mnemonic#"\t$BD2", [(operator mode:$BD2)]>; 2708 2709class LoadAddressRX<string mnemonic, bits<8> opcode, 2710 SDPatternOperator operator, AddressingMode mode> 2711 : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2), 2712 mnemonic#"\t$R1, $XBD2", 2713 [(set GR64:$R1, (operator mode:$XBD2))]>; 2714 2715class LoadAddressRXY<string mnemonic, bits<16> opcode, 2716 SDPatternOperator operator, AddressingMode mode> 2717 : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2), 2718 mnemonic#"\t$R1, $XBD2", 2719 [(set GR64:$R1, (operator mode:$XBD2))]>; 2720 2721multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode, 2722 bits<16> rxyOpcode, SDPatternOperator operator> { 2723 let DispKey = mnemonic in { 2724 let DispSize = "12" in 2725 def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>; 2726 let DispSize = "20" in 2727 def Y : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>; 2728 } 2729} 2730 2731class LoadAddressRIL<string mnemonic, bits<12> opcode, 2732 SDPatternOperator operator> 2733 : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2), 2734 mnemonic#"\t$R1, $RI2", 2735 [(set GR64:$R1, (operator pcrel32:$RI2))]>; 2736 2737class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2738 RegisterOperand cls1, RegisterOperand cls2> 2739 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2), 2740 mnemonic#"\t$R1, $R2", 2741 [(set cls1:$R1, (operator cls2:$R2))]> { 2742 let OpKey = mnemonic#cls1; 2743 let OpType = "reg"; 2744} 2745 2746class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2747 RegisterOperand cls1, RegisterOperand cls2> 2748 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2), 2749 mnemonic#"\t$R1, $R2", 2750 [(set cls1:$R1, (operator cls2:$R2))]> { 2751 let OpKey = mnemonic#cls1; 2752 let OpType = "reg"; 2753} 2754 2755class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 2756 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src), 2757 mnemonic#"\t$R1", []> { 2758 let Constraints = "$R1 = $R1src"; 2759 let DisableEncoding = "$R1src"; 2760 let R2 = 0; 2761} 2762 2763class UnaryMemRRFc<string mnemonic, bits<16> opcode, 2764 RegisterOperand cls1, RegisterOperand cls2> 2765 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src), 2766 mnemonic#"\t$R1, $R2", []> { 2767 let Constraints = "$R1 = $R1src"; 2768 let DisableEncoding = "$R1src"; 2769 let M3 = 0; 2770} 2771 2772class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 2773 RegisterOperand cls, ImmOpWithPattern imm> 2774 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2), 2775 mnemonic#"\t$R1, $I2", 2776 [(set cls:$R1, (operator imm:$I2))]>; 2777 2778class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 2779 RegisterOperand cls, ImmOpWithPattern imm> 2780 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2), 2781 mnemonic#"\t$R1, $I2", 2782 [(set cls:$R1, (operator imm:$I2))]>; 2783 2784class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 2785 RegisterOperand cls> 2786 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2), 2787 mnemonic#"\t$R1, $RI2", 2788 [(set cls:$R1, (operator pcrel32:$RI2))]> { 2789 let mayLoad = 1; 2790 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 2791 // However, BDXs have two extra operands and are therefore 6 units more 2792 // complex. 2793 let AddedComplexity = 7; 2794} 2795 2796class CondUnaryRSY<string mnemonic, bits<16> opcode, 2797 SDPatternOperator operator, RegisterOperand cls, 2798 bits<5> bytes, AddressingMode mode = bdaddr20only> 2799 : InstRSYb<opcode, (outs cls:$R1), 2800 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3), 2801 mnemonic#"$M3\t$R1, $BD2", 2802 [(set cls:$R1, 2803 (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src, 2804 cond4:$valid, cond4:$M3))]> { 2805 let Constraints = "$R1 = $R1src"; 2806 let DisableEncoding = "$R1src"; 2807 let mayLoad = 1; 2808 let AccessBytes = bytes; 2809 let CCMaskLast = 1; 2810} 2811 2812// Like CondUnaryRSY, but used for the raw assembly form. The condition-code 2813// mask is the third operand rather than being part of the mnemonic. 2814class AsmCondUnaryRSY<string mnemonic, bits<16> opcode, 2815 RegisterOperand cls, bits<5> bytes, 2816 AddressingMode mode = bdaddr20only> 2817 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3), 2818 mnemonic#"\t$R1, $BD2, $M3", []> { 2819 let mayLoad = 1; 2820 let AccessBytes = bytes; 2821 let Constraints = "$R1 = $R1src"; 2822 let DisableEncoding = "$R1src"; 2823} 2824 2825// Like CondUnaryRSY, but with a fixed CC mask. 2826class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode, 2827 RegisterOperand cls, bits<5> bytes, 2828 AddressingMode mode = bdaddr20only> 2829 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2), 2830 mnemonic#V.suffix#"\t$R1, $BD2", []> { 2831 let Constraints = "$R1 = $R1src"; 2832 let DisableEncoding = "$R1src"; 2833 let mayLoad = 1; 2834 let AccessBytes = bytes; 2835 let isAsmParserOnly = V.alternate; 2836 let M3 = V.ccmask; 2837} 2838 2839multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode, 2840 SDPatternOperator operator, 2841 RegisterOperand cls, bits<5> bytes, 2842 AddressingMode mode = bdaddr20only> { 2843 let isCodeGenOnly = 1 in 2844 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>; 2845 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>; 2846} 2847 2848class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2849 RegisterOperand cls, bits<5> bytes, 2850 AddressingMode mode = bdxaddr12only> 2851 : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2), 2852 mnemonic#"\t$R1, $XBD2", 2853 [(set cls:$R1, (operator mode:$XBD2))]> { 2854 let OpKey = mnemonic#"r"#cls; 2855 let OpType = "mem"; 2856 let mayLoad = 1; 2857 let AccessBytes = bytes; 2858} 2859 2860class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2861 RegisterOperand cls, bits<5> bytes> 2862 : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2), 2863 mnemonic#"\t$R1, $XBD2", 2864 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> { 2865 let OpKey = mnemonic#"r"#cls; 2866 let OpType = "mem"; 2867 let mayLoad = 1; 2868 let AccessBytes = bytes; 2869 let M3 = 0; 2870} 2871 2872class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2873 RegisterOperand cls, bits<5> bytes, 2874 AddressingMode mode = bdxaddr20only> 2875 : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2), 2876 mnemonic#"\t$R1, $XBD2", 2877 [(set cls:$R1, (operator mode:$XBD2))]> { 2878 let OpKey = mnemonic#"r"#cls; 2879 let OpType = "mem"; 2880 let mayLoad = 1; 2881 let AccessBytes = bytes; 2882} 2883 2884multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 2885 SDPatternOperator operator, RegisterOperand cls, 2886 bits<5> bytes> { 2887 let DispKey = mnemonic ## #cls in { 2888 let DispSize = "12" in 2889 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 2890 let DispSize = "20" in 2891 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 2892 bdxaddr20pair>; 2893 } 2894} 2895 2896class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2897 TypedReg tr, ImmOpWithPattern imm, bits<4> type = 0> 2898 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2), 2899 mnemonic#"\t$V1, $I2", 2900 [(set (tr.vt tr.op:$V1), (operator (i32 timm:$I2)))]> { 2901 let M3 = type; 2902} 2903 2904class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm> 2905 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3), 2906 mnemonic#"\t$V1, $I2, $M3", []>; 2907 2908class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2909 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0, 2910 bits<4> m5 = 0> 2911 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2), 2912 mnemonic#"\t$V1, $V2", 2913 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> { 2914 let M3 = type; 2915 let M4 = m4; 2916 let M5 = m5; 2917} 2918 2919class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0, 2920 bits<4> m5 = 0> 2921 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), 2922 mnemonic#"\t$V1, $V2, $M3", []> { 2923 let M4 = m4; 2924 let M5 = m5; 2925} 2926 2927class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0> 2928 : InstVRRa<opcode, (outs VR128:$V1), 2929 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4), 2930 mnemonic#"\t$V1, $V2, $M3, $M4", []> { 2931 let M5 = m5; 2932} 2933 2934// Declare a pair of instructions, one which sets CC and one which doesn't. 2935// The CC-setting form ends with "S" and sets the low bit of M5. 2936// The form that does not set CC has an extra operand to optionally allow 2937// specifying arbitrary M5 values in assembler. 2938multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode, 2939 SDPatternOperator operator, 2940 SDPatternOperator operator_cc, 2941 TypedReg tr1, TypedReg tr2, bits<4> type> { 2942 let M3 = type, M4 = 0 in 2943 def "" : InstVRRa<opcode, (outs tr1.op:$V1), 2944 (ins tr2.op:$V2, imm32zx4:$M5), 2945 mnemonic#"\t$V1, $V2, $M5", []>; 2946 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))), 2947 (!cast<Instruction>(NAME) tr2.op:$V2, 0)>; 2948 def : InstAlias<mnemonic#"\t$V1, $V2", 2949 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>; 2950 let Defs = [CC] in 2951 def S : UnaryVRRa<mnemonic##"s", opcode, operator_cc, tr1, tr2, 2952 type, 0, 1>; 2953} 2954 2955multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> { 2956 let M4 = 0, Defs = [CC] in 2957 def "" : InstVRRa<opcode, (outs VR128:$V1), 2958 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5), 2959 mnemonic#"\t$V1, $V2, $M3, $M5", []>; 2960 def : InstAlias<mnemonic#"\t$V1, $V2, $M3", 2961 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, 2962 imm32zx4:$M3, 0)>; 2963} 2964 2965class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2966 TypedReg tr, bits<5> bytes, bits<4> type = 0> 2967 : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2), 2968 mnemonic#"\t$V1, $XBD2", 2969 [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> { 2970 let M3 = type; 2971 let mayLoad = 1; 2972 let AccessBytes = bytes; 2973} 2974 2975class UnaryVRXGeneric<string mnemonic, bits<16> opcode> 2976 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 2977 mnemonic#"\t$V1, $XBD2, $M3", []> { 2978 let mayLoad = 1; 2979} 2980 2981multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> { 2982 let mayLoad = 1, AccessBytes = 16 in { 2983 def Align : InstVRX<opcode, (outs VR128:$V1), 2984 (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 2985 mnemonic#"\t$V1, $XBD2, $M3", []>; 2986 let M3 = 0 in 2987 def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2), 2988 mnemonic#"\t$V1, $XBD2", []>; 2989 } 2990} 2991 2992class SideEffectBinaryRX<string mnemonic, bits<8> opcode, 2993 RegisterOperand cls> 2994 : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2), 2995 mnemonic##"\t$R1, $XBD2", []>; 2996 2997class SideEffectBinaryRXY<string mnemonic, bits<16> opcode, 2998 RegisterOperand cls> 2999 : InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2), 3000 mnemonic##"\t$R1, $XBD2", []>; 3001 3002class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode, 3003 RegisterOperand cls> 3004 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 3005 mnemonic##"\t$R1, $RI2", []> { 3006 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 3007 // However, BDXs have two extra operands and are therefore 6 units more 3008 // complex. 3009 let AddedComplexity = 7; 3010} 3011 3012class SideEffectBinaryRRE<string mnemonic, bits<16> opcode, 3013 RegisterOperand cls1, RegisterOperand cls2> 3014 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3015 mnemonic#"\t$R1, $R2", []>; 3016 3017class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode, 3018 RegisterOperand cls1, RegisterOperand cls2> 3019 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3020 mnemonic#"\t$R1, $R2", []> { 3021 let R3 = 0; 3022 let M4 = 0; 3023} 3024 3025class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode, 3026 RegisterOperand cls1, RegisterOperand cls2> 3027 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3028 mnemonic#"\t$R1, $R2", []> { 3029 let M3 = 0; 3030} 3031 3032class SideEffectBinaryIE<string mnemonic, bits<16> opcode, 3033 ImmOpWithPattern imm1, ImmOpWithPattern imm2> 3034 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2), 3035 mnemonic#"\t$I1, $I2", []>; 3036 3037class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm> 3038 : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 3039 mnemonic#"\t$BD1, $I2", []>; 3040 3041class SideEffectBinarySIL<string mnemonic, bits<16> opcode, 3042 SDPatternOperator operator, ImmOpWithPattern imm> 3043 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 3044 mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>; 3045 3046class SideEffectBinarySSa<string mnemonic, bits<8> opcode> 3047 : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2), 3048 mnemonic##"\t$BDL1, $BD2", []>; 3049 3050class SideEffectBinarySSb<string mnemonic, bits<8> opcode> 3051 : InstSSb<opcode, 3052 (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2), 3053 mnemonic##"\t$BDL1, $BDL2", []>; 3054 3055class SideEffectBinarySSf<string mnemonic, bits<8> opcode> 3056 : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2), 3057 mnemonic##"\t$BD1, $BDL2", []>; 3058 3059class SideEffectBinarySSE<string mnemonic, bits<16> opcode> 3060 : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2), 3061 mnemonic#"\t$BD1, $BD2", []>; 3062 3063class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode, 3064 RegisterOperand cls1, RegisterOperand cls2> 3065 : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3066 mnemonic#"\t$R1, $R2", []> { 3067 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3068 let DisableEncoding = "$R1src, $R2src"; 3069} 3070 3071class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode, 3072 RegisterOperand cls1, RegisterOperand cls2> 3073 : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src), 3074 mnemonic#"\t$R1, $R2", []> { 3075 let Constraints = "$R2 = $R2src"; 3076 let DisableEncoding = "$R2src"; 3077} 3078 3079class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode, 3080 RegisterOperand cls1, RegisterOperand cls2> 3081 : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3082 mnemonic#"\t$R1, $R2", []> { 3083 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3084 let DisableEncoding = "$R1src, $R2src"; 3085} 3086 3087class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode, 3088 RegisterOperand cls1, RegisterOperand cls2> 3089 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3090 mnemonic#"\t$R1, $R2", []> { 3091 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3092 let DisableEncoding = "$R1src, $R2src"; 3093 let M3 = 0; 3094} 3095 3096class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3097 RegisterOperand cls1, RegisterOperand cls2> 3098 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3099 mnemonic#"\t$R1, $R2", 3100 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 3101 let OpKey = mnemonic#cls1; 3102 let OpType = "reg"; 3103 let Constraints = "$R1 = $R1src"; 3104 let DisableEncoding = "$R1src"; 3105} 3106 3107class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3108 RegisterOperand cls1, RegisterOperand cls2> 3109 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3110 mnemonic#"\t$R1, $R2", 3111 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 3112 let OpKey = mnemonic#cls1; 3113 let OpType = "reg"; 3114 let Constraints = "$R1 = $R1src"; 3115 let DisableEncoding = "$R1src"; 3116} 3117 3118class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3119 RegisterOperand cls1, RegisterOperand cls2> 3120 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2), 3121 mnemonic#"\t$R1, $R3, $R2", 3122 [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> { 3123 let OpKey = mnemonic#cls; 3124 let OpType = "reg"; 3125} 3126 3127class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3128 RegisterOperand cls1, RegisterOperand cls2, 3129 RegisterOperand cls3> 3130 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3), 3131 mnemonic#"\t$R1, $R2, $R3", 3132 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> { 3133 let M4 = 0; 3134 let OpKey = mnemonic#cls1; 3135 let OpType = "reg"; 3136} 3137 3138multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 3139 SDPatternOperator operator, RegisterOperand cls1, 3140 RegisterOperand cls2> { 3141 let NumOpsKey = mnemonic in { 3142 let NumOpsValue = "3" in 3143 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>, 3144 Requires<[FeatureDistinctOps]>; 3145 let NumOpsValue = "2" in 3146 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>; 3147 } 3148} 3149 3150multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2, 3151 SDPatternOperator operator, RegisterOperand cls1, 3152 RegisterOperand cls2> { 3153 let NumOpsKey = mnemonic in { 3154 let NumOpsValue = "3" in 3155 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>, 3156 Requires<[FeatureDistinctOps]>; 3157 let NumOpsValue = "2" in 3158 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>; 3159 } 3160} 3161 3162class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3163 RegisterOperand cls1, RegisterOperand cls2, 3164 RegisterOperand cls3> 3165 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3), 3166 mnemonic#"\t$R1, $R3, $R2", 3167 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> { 3168 let M4 = 0; 3169} 3170 3171class BinaryRRFc<string mnemonic, bits<16> opcode, 3172 RegisterOperand cls1, RegisterOperand cls2> 3173 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3), 3174 mnemonic#"\t$R1, $R2, $M3", []>; 3175 3176class BinaryMemRRFc<string mnemonic, bits<16> opcode, 3177 RegisterOperand cls1, RegisterOperand cls2, ImmOpWithPattern imm> 3178 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3), 3179 mnemonic#"\t$R1, $R2, $M3", []> { 3180 let Constraints = "$R1 = $R1src"; 3181 let DisableEncoding = "$R1src"; 3182} 3183 3184multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode, 3185 RegisterOperand cls1, RegisterOperand cls2> { 3186 def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 3187 def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>; 3188} 3189 3190class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3191 RegisterOperand cls2> 3192 : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4), 3193 mnemonic#"\t$R1, $R2, $M4", []>; 3194 3195class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3196 RegisterOperand cls2> 3197 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2), 3198 mnemonic#"\t$R1, $M3, $R2", []> { 3199 let M4 = 0; 3200} 3201 3202class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3203 RegisterOperand cls2> 3204 : InstRRFc<opcode, (outs cls1:$R1), 3205 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), 3206 mnemonic#"$M3\t$R1, $R2", 3207 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src, 3208 cond4:$valid, cond4:$M3))]> { 3209 let Constraints = "$R1 = $R1src"; 3210 let DisableEncoding = "$R1src"; 3211 let CCMaskLast = 1; 3212 let NumOpsKey = !subst("loc", "sel", mnemonic); 3213 let NumOpsValue = "2"; 3214} 3215 3216// Like CondBinaryRRF, but used for the raw assembly form. The condition-code 3217// mask is the third operand rather than being part of the mnemonic. 3218class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3219 RegisterOperand cls2> 3220 : InstRRFc<opcode, (outs cls1:$R1), 3221 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3), 3222 mnemonic#"\t$R1, $R2, $M3", []> { 3223 let Constraints = "$R1 = $R1src"; 3224 let DisableEncoding = "$R1src"; 3225} 3226 3227// Like CondBinaryRRF, but with a fixed CC mask. 3228class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode, 3229 RegisterOperand cls1, RegisterOperand cls2> 3230 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3231 mnemonic#V.suffix#"\t$R1, $R2", []> { 3232 let Constraints = "$R1 = $R1src"; 3233 let DisableEncoding = "$R1src"; 3234 let isAsmParserOnly = V.alternate; 3235 let M3 = V.ccmask; 3236} 3237 3238multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode, 3239 RegisterOperand cls1, RegisterOperand cls2> { 3240 let isCodeGenOnly = 1 in 3241 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>; 3242 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>; 3243} 3244 3245class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3246 RegisterOperand cls2, RegisterOperand cls3> 3247 : InstRRFa<opcode, (outs cls1:$R1), 3248 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4), 3249 mnemonic#"$M4\t$R1, $R2, $R3", 3250 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3, 3251 cond4:$valid, cond4:$M4))]> { 3252 let CCMaskLast = 1; 3253 let NumOpsKey = mnemonic; 3254 let NumOpsValue = "3"; 3255} 3256 3257// Like CondBinaryRRFa, but used for the raw assembly form. The condition-code 3258// mask is the third operand rather than being part of the mnemonic. 3259class AsmCondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3260 RegisterOperand cls2, RegisterOperand cls3> 3261 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4), 3262 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 3263 3264// Like CondBinaryRRFa, but with a fixed CC mask. 3265class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode, 3266 RegisterOperand cls1, RegisterOperand cls2, 3267 RegisterOperand cls3> 3268 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2), 3269 mnemonic#V.suffix#"\t$R1, $R2, $R3", []> { 3270 let isAsmParserOnly = V.alternate; 3271 let M4 = V.ccmask; 3272} 3273 3274multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode, 3275 RegisterOperand cls1, RegisterOperand cls2, 3276 RegisterOperand cls3> { 3277 let isCodeGenOnly = 1 in 3278 def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 3279 def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 3280} 3281 3282class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3283 RegisterOperand cls, ImmOpWithPattern imm> 3284 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3285 mnemonic#"\t$R1, $I2", 3286 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 3287 let Constraints = "$R1 = $R1src"; 3288 let DisableEncoding = "$R1src"; 3289} 3290 3291class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3292 RegisterOperand cls, ImmOpWithPattern imm> 3293 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2), 3294 mnemonic#"\t$R1, $R3, $I2", 3295 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 3296 3297multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2, 3298 SDPatternOperator operator, RegisterOperand cls, 3299 ImmOpWithPattern imm> { 3300 let NumOpsKey = mnemonic in { 3301 let NumOpsValue = "3" in 3302 def K : BinaryRIE<mnemonic##"k", opcode2, operator, cls, imm>, 3303 Requires<[FeatureDistinctOps]>; 3304 let NumOpsValue = "2" in 3305 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>; 3306 } 3307} 3308 3309class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls, 3310 ImmOpWithPattern imm> 3311 : InstRIEg<opcode, (outs cls:$R1), 3312 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3), 3313 mnemonic#"$M3\t$R1, $I2", 3314 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src, 3315 cond4:$valid, cond4:$M3))]> { 3316 let Constraints = "$R1 = $R1src"; 3317 let DisableEncoding = "$R1src"; 3318 let CCMaskLast = 1; 3319} 3320 3321// Like CondBinaryRIE, but used for the raw assembly form. The condition-code 3322// mask is the third operand rather than being part of the mnemonic. 3323class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls, 3324 ImmOpWithPattern imm> 3325 : InstRIEg<opcode, (outs cls:$R1), 3326 (ins cls:$R1src, imm:$I2, imm32zx4:$M3), 3327 mnemonic#"\t$R1, $I2, $M3", []> { 3328 let Constraints = "$R1 = $R1src"; 3329 let DisableEncoding = "$R1src"; 3330} 3331 3332// Like CondBinaryRIE, but with a fixed CC mask. 3333class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode, 3334 RegisterOperand cls, ImmOpWithPattern imm> 3335 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3336 mnemonic#V.suffix#"\t$R1, $I2", []> { 3337 let Constraints = "$R1 = $R1src"; 3338 let DisableEncoding = "$R1src"; 3339 let isAsmParserOnly = V.alternate; 3340 let M3 = V.ccmask; 3341} 3342 3343multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode, 3344 RegisterOperand cls, ImmOpWithPattern imm> { 3345 let isCodeGenOnly = 1 in 3346 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>; 3347 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>; 3348} 3349 3350class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3351 RegisterOperand cls, ImmOpWithPattern imm> 3352 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3353 mnemonic#"\t$R1, $I2", 3354 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 3355 let Constraints = "$R1 = $R1src"; 3356 let DisableEncoding = "$R1src"; 3357} 3358 3359class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3360 RegisterOperand cls> 3361 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2), 3362 mnemonic#"\t$R1, $BD2", 3363 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> { 3364 let R3 = 0; 3365 let Constraints = "$R1 = $R1src"; 3366 let DisableEncoding = "$R1src"; 3367} 3368 3369class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3370 RegisterOperand cls> 3371 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2), 3372 mnemonic#"\t$R1, $R3, $BD2", 3373 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>; 3374 3375multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 3376 SDPatternOperator operator, RegisterOperand cls> { 3377 let NumOpsKey = mnemonic in { 3378 let NumOpsValue = "3" in 3379 def K : BinaryRSY<mnemonic##"k", opcode2, operator, cls>, 3380 Requires<[FeatureDistinctOps]>; 3381 let NumOpsValue = "2" in 3382 def "" : BinaryRS<mnemonic, opcode1, operator, cls>; 3383 } 3384} 3385 3386class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls> 3387 : InstRSLb<opcode, (outs cls:$R1), 3388 (ins bdladdr12onlylen8:$BDL2, imm32zx4:$M3), 3389 mnemonic#"\t$R1, $BDL2, $M3", []> { 3390 let mayLoad = 1; 3391} 3392 3393class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3394 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3395 AddressingMode mode = bdxaddr12only> 3396 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 3397 mnemonic#"\t$R1, $XBD2", 3398 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 3399 let OpKey = mnemonic#"r"#cls; 3400 let OpType = "mem"; 3401 let Constraints = "$R1 = $R1src"; 3402 let DisableEncoding = "$R1src"; 3403 let mayLoad = 1; 3404 let AccessBytes = bytes; 3405} 3406 3407class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3408 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 3409 : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2), 3410 mnemonic#"\t$R1, $XBD2", 3411 [(set cls:$R1, (operator cls:$R1src, 3412 (load bdxaddr12only:$XBD2)))]> { 3413 let OpKey = mnemonic#"r"#cls; 3414 let OpType = "mem"; 3415 let Constraints = "$R1 = $R1src"; 3416 let DisableEncoding = "$R1src"; 3417 let mayLoad = 1; 3418 let AccessBytes = bytes; 3419 let M3 = 0; 3420} 3421 3422class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3423 RegisterOperand cls1, RegisterOperand cls2, 3424 SDPatternOperator load, bits<5> bytes> 3425 : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2), 3426 mnemonic#"\t$R1, $R3, $XBD2", 3427 [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> { 3428 let OpKey = mnemonic#"r"#cls; 3429 let OpType = "mem"; 3430 let mayLoad = 1; 3431 let AccessBytes = bytes; 3432} 3433 3434class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3435 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3436 AddressingMode mode = bdxaddr20only> 3437 : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2), 3438 mnemonic#"\t$R1, $XBD2", 3439 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 3440 let OpKey = mnemonic#"r"#cls; 3441 let OpType = "mem"; 3442 let Constraints = "$R1 = $R1src"; 3443 let DisableEncoding = "$R1src"; 3444 let mayLoad = 1; 3445 let AccessBytes = bytes; 3446} 3447 3448multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 3449 SDPatternOperator operator, RegisterOperand cls, 3450 SDPatternOperator load, bits<5> bytes> { 3451 let DispKey = mnemonic ## #cls in { 3452 let DispSize = "12" in 3453 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 3454 bdxaddr12pair>; 3455 let DispSize = "20" in 3456 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes, 3457 bdxaddr20pair>; 3458 } 3459} 3460 3461class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3462 Operand imm, AddressingMode mode = bdaddr12only> 3463 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 3464 mnemonic#"\t$BD1, $I2", 3465 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 3466 let mayLoad = 1; 3467 let mayStore = 1; 3468} 3469 3470class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3471 Operand imm, AddressingMode mode = bdaddr20only> 3472 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 3473 mnemonic#"\t$BD1, $I2", 3474 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> { 3475 let mayLoad = 1; 3476 let mayStore = 1; 3477} 3478 3479multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, 3480 bits<16> siyOpcode, SDPatternOperator operator, 3481 Operand imm> { 3482 let DispKey = mnemonic ## #cls in { 3483 let DispSize = "12" in 3484 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 3485 let DispSize = "20" in 3486 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 3487 } 3488} 3489 3490class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls> 3491 : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2), 3492 mnemonic#"\t$R3, $BD1, $BD2", []> { 3493 let mayLoad = 1; 3494} 3495 3496class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3497 TypedReg tr, bits<4> type> 3498 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3), 3499 mnemonic#"\t$V1, $I2, $I3", 3500 [(set (tr.vt tr.op:$V1), (operator imm32zx8_timm:$I2, imm32zx8_timm:$I3))]> { 3501 let M4 = type; 3502} 3503 3504class BinaryVRIbGeneric<string mnemonic, bits<16> opcode> 3505 : InstVRIb<opcode, (outs VR128:$V1), 3506 (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4), 3507 mnemonic#"\t$V1, $I2, $I3, $M4", []>; 3508 3509class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3510 TypedReg tr1, TypedReg tr2, bits<4> type> 3511 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2), 3512 mnemonic#"\t$V1, $V3, $I2", 3513 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3), 3514 imm32zx16_timm:$I2))]> { 3515 let M4 = type; 3516} 3517 3518class BinaryVRIcGeneric<string mnemonic, bits<16> opcode> 3519 : InstVRIc<opcode, (outs VR128:$V1), 3520 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4), 3521 mnemonic#"\t$V1, $V3, $I2, $M4", []>; 3522 3523class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3524 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5> 3525 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3), 3526 mnemonic#"\t$V1, $V2, $I3", 3527 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3528 imm32zx12_timm:$I3))]> { 3529 let M4 = type; 3530 let M5 = m5; 3531} 3532 3533class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode> 3534 : InstVRIe<opcode, (outs VR128:$V1), 3535 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 3536 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>; 3537 3538class BinaryVRIh<string mnemonic, bits<16> opcode> 3539 : InstVRIh<opcode, (outs VR128:$V1), 3540 (ins imm32zx16:$I2, imm32zx4:$I3), 3541 mnemonic#"\t$V1, $I2, $I3", []>; 3542 3543class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3544 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0> 3545 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5), 3546 mnemonic#"\t$V1, $V2, $M5", 3547 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3548 imm32zx12:$M5))]> { 3549 let M3 = type; 3550 let M4 = m4; 3551} 3552 3553class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode> 3554 : InstVRRa<opcode, (outs VR128:$V1), 3555 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5), 3556 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>; 3557 3558class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3559 TypedReg tr1, TypedReg tr2, bits<4> type = 0, 3560 bits<4> modifier = 0> 3561 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 3562 mnemonic#"\t$V1, $V2, $V3", 3563 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3564 (tr2.vt tr2.op:$V3)))]> { 3565 let M4 = type; 3566 let M5 = modifier; 3567} 3568 3569// Declare a pair of instructions, one which sets CC and one which doesn't. 3570// The CC-setting form ends with "S" and sets the low bit of M5. 3571multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode, 3572 SDPatternOperator operator, 3573 SDPatternOperator operator_cc, TypedReg tr1, 3574 TypedReg tr2, bits<4> type, bits<4> modifier = 0> { 3575 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 3576 !and (modifier, 14)>; 3577 let Defs = [CC] in 3578 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 3579 !add (!and (modifier, 14), 1)>; 3580} 3581 3582class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode> 3583 : InstVRRb<opcode, (outs VR128:$V1), 3584 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 3585 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> { 3586 let Defs = [CC]; 3587} 3588 3589// Declare a pair of instructions, one which sets CC and one which doesn't. 3590// The CC-setting form ends with "S" and sets the low bit of M5. 3591// The form that does not set CC has an extra operand to optionally allow 3592// specifying arbitrary M5 values in assembler. 3593multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode, 3594 SDPatternOperator operator, 3595 SDPatternOperator operator_cc, 3596 TypedReg tr1, TypedReg tr2, bits<4> type> { 3597 let M4 = type in 3598 def "" : InstVRRb<opcode, (outs tr1.op:$V1), 3599 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5), 3600 mnemonic#"\t$V1, $V2, $V3, $M5", []>; 3601 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))), 3602 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>; 3603 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 3604 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 3605 tr2.op:$V3, 0)>; 3606 let Defs = [CC] in 3607 def S : BinaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 1>; 3608} 3609 3610multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> { 3611 let Defs = [CC] in 3612 def "" : InstVRRb<opcode, (outs VR128:$V1), 3613 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 3614 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 3615 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4", 3616 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 3617 imm32zx4:$M4, 0)>; 3618} 3619 3620class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3621 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0, 3622 bits<4> m6 = 0> 3623 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 3624 mnemonic#"\t$V1, $V2, $V3", 3625 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3626 (tr2.vt tr2.op:$V3)))]> { 3627 let M4 = type; 3628 let M5 = m5; 3629 let M6 = m6; 3630} 3631 3632class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0, 3633 bits<4> m6 = 0> 3634 : InstVRRc<opcode, (outs VR128:$V1), 3635 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4), 3636 mnemonic#"\t$V1, $V2, $V3, $M4", []> { 3637 let M5 = m5; 3638 let M6 = m6; 3639} 3640 3641class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0> 3642 : InstVRRc<opcode, (outs VR128:$V1), 3643 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 3644 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> { 3645 let M6 = m6; 3646} 3647 3648// Declare a pair of instructions, one which sets CC and one which doesn't. 3649// The CC-setting form ends with "S" and sets the low bit of M5. 3650multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode, 3651 SDPatternOperator operator, 3652 SDPatternOperator operator_cc, TypedReg tr1, 3653 TypedReg tr2, bits<4> type, bits<4> m5, 3654 bits<4> modifier = 0> { 3655 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, 3656 m5, !and (modifier, 14)>; 3657 let Defs = [CC] in 3658 def S : BinaryVRRc<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 3659 m5, !add (!and (modifier, 14), 1)>; 3660} 3661 3662class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode> 3663 : InstVRRc<opcode, (outs VR128:$V1), 3664 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 3665 imm32zx4:$M6), 3666 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>; 3667 3668class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3669 TypedReg tr> 3670 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3), 3671 mnemonic#"\t$V1, $R2, $R3", 3672 [(set (tr.vt tr.op:$V1), (operator GR64:$R2, GR64:$R3))]>; 3673 3674class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls> 3675 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3), 3676 mnemonic#"\t$R1, $V2, $M3", []> { 3677 let M4 = 0; 3678} 3679 3680class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3681 TypedReg tr1, TypedReg tr2, bits<4> type> 3682 : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2), 3683 mnemonic#"\t$V1, $V3, $BD2", 3684 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3), 3685 shift12only:$BD2))]> { 3686 let M4 = type; 3687} 3688 3689class BinaryVRSaGeneric<string mnemonic, bits<16> opcode> 3690 : InstVRSa<opcode, (outs VR128:$V1), 3691 (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4), 3692 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 3693 3694class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3695 bits<5> bytes> 3696 : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2), 3697 mnemonic#"\t$V1, $R3, $BD2", 3698 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 3699 let M4 = 0; 3700 let mayLoad = 1; 3701 let AccessBytes = bytes; 3702} 3703 3704class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3705 TypedReg tr, bits<4> type> 3706 : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2), 3707 mnemonic#"\t$R1, $V3, $BD2", 3708 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> { 3709 let M4 = type; 3710} 3711 3712class BinaryVRScGeneric<string mnemonic, bits<16> opcode> 3713 : InstVRSc<opcode, (outs GR64:$R1), 3714 (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4), 3715 mnemonic#"\t$R1, $V3, $BD2, $M4", []>; 3716 3717class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3718 bits<5> bytes> 3719 : InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2), 3720 mnemonic#"\t$V1, $R3, $BD2", 3721 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 3722 let mayLoad = 1; 3723 let AccessBytes = bytes; 3724} 3725 3726class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3727 TypedReg tr, bits<5> bytes> 3728 : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3), 3729 mnemonic#"\t$V1, $XBD2, $M3", 3730 [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2, 3731 imm32zx4_timm:$M3))]> { 3732 let mayLoad = 1; 3733 let AccessBytes = bytes; 3734} 3735 3736class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 3737 bits<5> bytes, AddressingMode mode = bdaddr12only> 3738 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2), 3739 mnemonic#"\t$R1, $M3, $BD2", []> { 3740 let mayStore = 1; 3741 let AccessBytes = bytes; 3742} 3743 3744class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 3745 bits<5> bytes, AddressingMode mode = bdaddr20only> 3746 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2), 3747 mnemonic#"\t$R1, $M3, $BD2", []> { 3748 let mayStore = 1; 3749 let AccessBytes = bytes; 3750} 3751 3752multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode, 3753 bits<16> rsyOpcode, RegisterOperand cls, 3754 bits<5> bytes> { 3755 let DispKey = mnemonic ## #cls in { 3756 let DispSize = "12" in 3757 def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 3758 let DispSize = "20" in 3759 def Y : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, 3760 bdaddr20pair>; 3761 } 3762} 3763 3764class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls> 3765 : InstRSLb<opcode, (outs), 3766 (ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3), 3767 mnemonic#"\t$R1, $BDL2, $M3", []> { 3768 let mayStore = 1; 3769} 3770 3771class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3772 bits<5> bytes> 3773 : InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3), 3774 mnemonic#"\t$V1, $BD2, $I3", 3775 [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> { 3776 let mayLoad = 1; 3777 let AccessBytes = bytes; 3778} 3779 3780class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 3781 ImmOpWithPattern index> 3782 : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3), 3783 mnemonic#"\t$V1, $VBD2, $M3", []> { 3784 let mayStore = 1; 3785 let AccessBytes = bytes; 3786} 3787 3788class StoreBinaryVRX<string mnemonic, bits<16> opcode, 3789 SDPatternOperator operator, TypedReg tr, bits<5> bytes, 3790 ImmOpWithPattern index> 3791 : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3), 3792 mnemonic#"\t$V1, $XBD2, $M3", 3793 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> { 3794 let mayStore = 1; 3795 let AccessBytes = bytes; 3796} 3797 3798class MemoryBinarySSd<string mnemonic, bits<8> opcode, 3799 RegisterOperand cls> 3800 : InstSSd<opcode, (outs), 3801 (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3), 3802 mnemonic#"\t$RBD1, $BD2, $R3", []>; 3803 3804class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3805 RegisterOperand cls1, RegisterOperand cls2> 3806 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3807 mnemonic#"\t$R1, $R2", 3808 [(set CC, (operator cls1:$R1, cls2:$R2))]> { 3809 let OpKey = mnemonic#cls1; 3810 let OpType = "reg"; 3811 let isCompare = 1; 3812} 3813 3814class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3815 RegisterOperand cls1, RegisterOperand cls2> 3816 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3817 mnemonic#"\t$R1, $R2", 3818 [(set CC, (operator cls1:$R1, cls2:$R2))]> { 3819 let OpKey = mnemonic#cls1; 3820 let OpType = "reg"; 3821 let isCompare = 1; 3822} 3823 3824class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3825 RegisterOperand cls, ImmOpWithPattern imm> 3826 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2), 3827 mnemonic#"\t$R1, $I2", 3828 [(set CC, (operator cls:$R1, imm:$I2))]> { 3829 let isCompare = 1; 3830} 3831 3832class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3833 RegisterOperand cls, ImmOpWithPattern imm> 3834 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2), 3835 mnemonic#"\t$R1, $I2", 3836 [(set CC, (operator cls:$R1, imm:$I2))]> { 3837 let isCompare = 1; 3838} 3839 3840class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3841 RegisterOperand cls, SDPatternOperator load> 3842 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 3843 mnemonic#"\t$R1, $RI2", 3844 [(set CC, (operator cls:$R1, (load pcrel32:$RI2)))]> { 3845 let isCompare = 1; 3846 let mayLoad = 1; 3847 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 3848 // However, BDXs have two extra operands and are therefore 6 units more 3849 // complex. 3850 let AddedComplexity = 7; 3851} 3852 3853class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3854 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3855 AddressingMode mode = bdxaddr12only> 3856 : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2), 3857 mnemonic#"\t$R1, $XBD2", 3858 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 3859 let OpKey = mnemonic#"r"#cls; 3860 let OpType = "mem"; 3861 let isCompare = 1; 3862 let mayLoad = 1; 3863 let AccessBytes = bytes; 3864} 3865 3866class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3867 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 3868 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2), 3869 mnemonic#"\t$R1, $XBD2", 3870 [(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> { 3871 let OpKey = mnemonic#"r"#cls; 3872 let OpType = "mem"; 3873 let isCompare = 1; 3874 let mayLoad = 1; 3875 let AccessBytes = bytes; 3876 let M3 = 0; 3877} 3878 3879class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3880 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3881 AddressingMode mode = bdxaddr20only> 3882 : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2), 3883 mnemonic#"\t$R1, $XBD2", 3884 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 3885 let OpKey = mnemonic#"r"#cls; 3886 let OpType = "mem"; 3887 let isCompare = 1; 3888 let mayLoad = 1; 3889 let AccessBytes = bytes; 3890} 3891 3892multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 3893 SDPatternOperator operator, RegisterOperand cls, 3894 SDPatternOperator load, bits<5> bytes> { 3895 let DispKey = mnemonic ## #cls in { 3896 let DispSize = "12" in 3897 def "" : CompareRX<mnemonic, rxOpcode, operator, cls, 3898 load, bytes, bdxaddr12pair>; 3899 let DispSize = "20" in 3900 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls, 3901 load, bytes, bdxaddr20pair>; 3902 } 3903} 3904 3905class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 3906 bits<5> bytes, AddressingMode mode = bdaddr12only> 3907 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2), 3908 mnemonic#"\t$R1, $M3, $BD2", []> { 3909 let mayLoad = 1; 3910 let AccessBytes = bytes; 3911} 3912 3913class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 3914 bits<5> bytes, AddressingMode mode = bdaddr20only> 3915 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2), 3916 mnemonic#"\t$R1, $M3, $BD2", []> { 3917 let mayLoad = 1; 3918 let AccessBytes = bytes; 3919} 3920 3921multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 3922 RegisterOperand cls, bits<5> bytes> { 3923 let DispKey = mnemonic ## #cls in { 3924 let DispSize = "12" in 3925 def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 3926 let DispSize = "20" in 3927 def Y : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>; 3928 } 3929} 3930 3931class CompareSSb<string mnemonic, bits<8> opcode> 3932 : InstSSb<opcode, 3933 (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2), 3934 mnemonic##"\t$BDL1, $BDL2", []> { 3935 let isCompare = 1; 3936 let mayLoad = 1; 3937} 3938 3939class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3940 SDPatternOperator load, ImmOpWithPattern imm, 3941 AddressingMode mode = bdaddr12only> 3942 : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2), 3943 mnemonic#"\t$BD1, $I2", 3944 [(set CC, (operator (load mode:$BD1), imm:$I2))]> { 3945 let isCompare = 1; 3946 let mayLoad = 1; 3947} 3948 3949class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3950 SDPatternOperator load, ImmOpWithPattern imm> 3951 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 3952 mnemonic#"\t$BD1, $I2", 3953 [(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> { 3954 let isCompare = 1; 3955 let mayLoad = 1; 3956} 3957 3958class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3959 SDPatternOperator load, ImmOpWithPattern imm, 3960 AddressingMode mode = bdaddr20only> 3961 : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2), 3962 mnemonic#"\t$BD1, $I2", 3963 [(set CC, (operator (load mode:$BD1), imm:$I2))]> { 3964 let isCompare = 1; 3965 let mayLoad = 1; 3966} 3967 3968multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 3969 SDPatternOperator operator, SDPatternOperator load, 3970 ImmOpWithPattern imm> { 3971 let DispKey = mnemonic in { 3972 let DispSize = "12" in 3973 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>; 3974 let DispSize = "20" in 3975 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm, 3976 bdaddr20pair>; 3977 } 3978} 3979 3980class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3981 TypedReg tr, bits<4> type> 3982 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2), 3983 mnemonic#"\t$V1, $V2", 3984 [(set CC, (operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2)))]> { 3985 let isCompare = 1; 3986 let M3 = type; 3987 let M4 = 0; 3988 let M5 = 0; 3989} 3990 3991class CompareVRRaGeneric<string mnemonic, bits<16> opcode> 3992 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3), 3993 mnemonic#"\t$V1, $V2, $M3", []> { 3994 let isCompare = 1; 3995 let M4 = 0; 3996 let M5 = 0; 3997} 3998 3999class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode> 4000 : InstVRRa<opcode, (outs), 4001 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4), 4002 mnemonic#"\t$V1, $V2, $M3, $M4", []> { 4003 let isCompare = 1; 4004 let M5 = 0; 4005} 4006 4007class CompareVRRh<string mnemonic, bits<16> opcode> 4008 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3), 4009 mnemonic#"\t$V1, $V2, $M3", []> { 4010 let isCompare = 1; 4011} 4012 4013class TestInherentS<string mnemonic, bits<16> opcode, 4014 SDPatternOperator operator> 4015 : InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> { 4016 let BD2 = 0; 4017} 4018 4019class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4020 RegisterOperand cls> 4021 : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2), 4022 mnemonic#"\t$R1, $XBD2", 4023 [(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> { 4024 let M3 = 0; 4025} 4026 4027class TestBinarySIL<string mnemonic, bits<16> opcode, 4028 SDPatternOperator operator, ImmOpWithPattern imm> 4029 : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2), 4030 mnemonic#"\t$BD1, $I2", 4031 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>; 4032 4033class TestRSL<string mnemonic, bits<16> opcode> 4034 : InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1), 4035 mnemonic#"\t$BDL1", []> { 4036 let mayLoad = 1; 4037} 4038 4039class TestVRRg<string mnemonic, bits<16> opcode> 4040 : InstVRRg<opcode, (outs), (ins VR128:$V1), 4041 mnemonic#"\t$V1", []>; 4042 4043class SideEffectTernarySSc<string mnemonic, bits<8> opcode> 4044 : InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1, 4045 shift12only:$BD2, imm32zx4:$I3), 4046 mnemonic##"\t$BDL1, $BD2, $I3", []>; 4047 4048class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode, 4049 RegisterOperand cls1, RegisterOperand cls2, 4050 RegisterOperand cls3> 4051 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), 4052 mnemonic#"\t$R1, $R2, $R3", []> { 4053 let M4 = 0; 4054} 4055 4056class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode, 4057 RegisterOperand cls1, RegisterOperand cls2, 4058 RegisterOperand cls3> 4059 : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2), 4060 (ins cls1:$R1src, cls2:$R2src, cls3:$R3), 4061 mnemonic#"\t$R1, $R2, $R3", []> { 4062 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 4063 let DisableEncoding = "$R1src, $R2src"; 4064 let M4 = 0; 4065} 4066 4067class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode, 4068 RegisterOperand cls1, RegisterOperand cls2, 4069 RegisterOperand cls3> 4070 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), 4071 mnemonic#"\t$R1, $R3, $R2", []> { 4072 let M4 = 0; 4073} 4074 4075class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode, 4076 RegisterOperand cls1, 4077 RegisterOperand cls2, 4078 RegisterOperand cls3> 4079 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3), 4080 (ins cls1:$R1src, cls2:$R2src, cls3:$R3src), 4081 mnemonic#"\t$R1, $R3, $R2", []> { 4082 let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src"; 4083 let DisableEncoding = "$R1src, $R2src, $R3src"; 4084 let M4 = 0; 4085} 4086 4087class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode, 4088 RegisterOperand cls1, RegisterOperand cls2, 4089 ImmOpWithPattern imm> 4090 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3), 4091 mnemonic#"\t$R1, $R2, $M3", []>; 4092 4093multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode, 4094 RegisterOperand cls1, 4095 RegisterOperand cls2> { 4096 def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 4097 def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>; 4098} 4099 4100class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode, 4101 RegisterOperand cls1, RegisterOperand cls2, 4102 ImmOpWithPattern imm> 4103 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), 4104 (ins cls1:$R1src, cls2:$R2src, imm:$M3), 4105 mnemonic#"\t$R1, $R2, $M3", []> { 4106 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 4107 let DisableEncoding = "$R1src, $R2src"; 4108} 4109 4110multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode, 4111 RegisterOperand cls1, 4112 RegisterOperand cls2> { 4113 def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 4114 def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>; 4115} 4116 4117class SideEffectTernarySSF<string mnemonic, bits<12> opcode, 4118 RegisterOperand cls> 4119 : InstSSF<opcode, (outs), 4120 (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3), 4121 mnemonic#"\t$BD1, $BD2, $R3", []>; 4122 4123class TernaryRRFa<string mnemonic, bits<16> opcode, 4124 RegisterOperand cls1, RegisterOperand cls2, 4125 RegisterOperand cls3> 4126 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4), 4127 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 4128 4129class TernaryRRFb<string mnemonic, bits<16> opcode, 4130 RegisterOperand cls1, RegisterOperand cls2, 4131 RegisterOperand cls3> 4132 : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3), 4133 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4), 4134 mnemonic#"\t$R1, $R3, $R2, $M4", []> { 4135 let Constraints = "$R1 = $R1src"; 4136 let DisableEncoding = "$R1src"; 4137} 4138 4139class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1, 4140 RegisterOperand cls2> 4141 : InstRRFe<opcode, (outs cls1:$R1), 4142 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4), 4143 mnemonic#"\t$R1, $M3, $R2, $M4", []>; 4144 4145class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4146 RegisterOperand cls1, RegisterOperand cls2> 4147 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2), 4148 mnemonic#"\t$R1, $R3, $R2", 4149 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> { 4150 let OpKey = mnemonic#cls; 4151 let OpType = "reg"; 4152 let Constraints = "$R1 = $R1src"; 4153 let DisableEncoding = "$R1src"; 4154} 4155 4156class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 4157 bits<5> bytes, AddressingMode mode = bdaddr12only> 4158 : InstRSb<opcode, (outs cls:$R1), 4159 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2), 4160 mnemonic#"\t$R1, $M3, $BD2", []> { 4161 4162 let Constraints = "$R1 = $R1src"; 4163 let DisableEncoding = "$R1src"; 4164 let mayLoad = 1; 4165 let AccessBytes = bytes; 4166} 4167 4168class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 4169 bits<5> bytes, AddressingMode mode = bdaddr20only> 4170 : InstRSYb<opcode, (outs cls:$R1), 4171 (ins cls:$R1src, imm32zx4:$M3, mode:$BD2), 4172 mnemonic#"\t$R1, $M3, $BD2", []> { 4173 4174 let Constraints = "$R1 = $R1src"; 4175 let DisableEncoding = "$R1src"; 4176 let mayLoad = 1; 4177 let AccessBytes = bytes; 4178} 4179 4180multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 4181 RegisterOperand cls, bits<5> bytes> { 4182 let DispKey = mnemonic ## #cls in { 4183 let DispSize = "12" in 4184 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 4185 let DispSize = "20" in 4186 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>; 4187 } 4188} 4189 4190class SideEffectTernaryRS<string mnemonic, bits<8> opcode, 4191 RegisterOperand cls1, RegisterOperand cls2> 4192 : InstRSa<opcode, (outs), 4193 (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2), 4194 mnemonic#"\t$R1, $R3, $BD2", []>; 4195 4196class SideEffectTernaryRSY<string mnemonic, bits<16> opcode, 4197 RegisterOperand cls1, RegisterOperand cls2> 4198 : InstRSYa<opcode, (outs), 4199 (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2), 4200 mnemonic#"\t$R1, $R3, $BD2", []>; 4201 4202class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode, 4203 RegisterOperand cls1, RegisterOperand cls2> 4204 : InstRSa<opcode, (outs cls1:$R1, cls2:$R3), 4205 (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2), 4206 mnemonic#"\t$R1, $R3, $BD2", []> { 4207 let Constraints = "$R1 = $R1src, $R3 = $R3src"; 4208 let DisableEncoding = "$R1src, $R3src"; 4209} 4210 4211class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode, 4212 RegisterOperand cls1, RegisterOperand cls2> 4213 : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3), 4214 (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2), 4215 mnemonic#"\t$R1, $R3, $BD2", []> { 4216 let Constraints = "$R1 = $R1src, $R3 = $R3src"; 4217 let DisableEncoding = "$R1src, $R3src"; 4218} 4219 4220class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4221 RegisterOperand cls1, RegisterOperand cls2, 4222 SDPatternOperator load, bits<5> bytes> 4223 : InstRXF<opcode, (outs cls1:$R1), 4224 (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2), 4225 mnemonic#"\t$R1, $R3, $XBD2", 4226 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, 4227 (load bdxaddr12only:$XBD2)))]> { 4228 let OpKey = mnemonic#"r"#cls; 4229 let OpType = "mem"; 4230 let Constraints = "$R1 = $R1src"; 4231 let DisableEncoding = "$R1src"; 4232 let mayLoad = 1; 4233 let AccessBytes = bytes; 4234} 4235 4236class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4237 TypedReg tr1, TypedReg tr2, ImmOpWithPattern imm, ImmOpWithPattern index> 4238 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3), 4239 mnemonic#"\t$V1, $I2, $M3", 4240 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4241 imm:$I2, index:$M3))]> { 4242 let Constraints = "$V1 = $V1src"; 4243 let DisableEncoding = "$V1src"; 4244} 4245 4246class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4247 TypedReg tr1, TypedReg tr2, bits<4> type> 4248 : InstVRId<opcode, (outs tr1.op:$V1), 4249 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 4250 mnemonic#"\t$V1, $V2, $V3, $I4", 4251 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4252 (tr2.vt tr2.op:$V3), 4253 imm32zx8_timm:$I4))]> { 4254 let M5 = type; 4255} 4256 4257class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4258 : InstVRIi<opcode, (outs VR128:$V1), 4259 (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4), 4260 mnemonic#"\t$V1, $R2, $I3, $M4", []>; 4261 4262class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4263 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or> 4264 : InstVRRa<opcode, (outs tr1.op:$V1), 4265 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5), 4266 mnemonic#"\t$V1, $V2, $M4, $M5", 4267 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4268 imm32zx4_timm:$M4, 4269 imm32zx4_timm:$M5))], 4270 m4or> { 4271 let M3 = type; 4272} 4273 4274class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode> 4275 : InstVRRa<opcode, (outs VR128:$V1), 4276 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5), 4277 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>; 4278 4279class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4280 TypedReg tr1, TypedReg tr2, bits<4> type, 4281 SDPatternOperator m5mask, bits<4> m5or> 4282 : InstVRRb<opcode, (outs tr1.op:$V1), 4283 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5), 4284 mnemonic#"\t$V1, $V2, $V3, $M5", 4285 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4286 (tr2.vt tr2.op:$V3), 4287 m5mask:$M5))], 4288 m5or> { 4289 let M4 = type; 4290} 4291 4292// Declare a pair of instructions, one which sets CC and one which doesn't. 4293// The CC-setting form ends with "S" and sets the low bit of M5. 4294// Also create aliases to make use of M5 operand optional in assembler. 4295multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode, 4296 SDPatternOperator operator, 4297 SDPatternOperator operator_cc, 4298 TypedReg tr1, TypedReg tr2, bits<4> type, 4299 bits<4> modifier = 0> { 4300 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 4301 imm32zx4even_timm, !and (modifier, 14)>; 4302 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 4303 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4304 tr2.op:$V3, 0)>; 4305 let Defs = [CC] in 4306 def S : TernaryVRRb<mnemonic##"s", opcode, operator_cc, tr1, tr2, type, 4307 imm32zx4even_timm, !add(!and (modifier, 14), 1)>; 4308 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3", 4309 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 4310 tr2.op:$V3, 0)>; 4311} 4312 4313multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> { 4314 let Defs = [CC] in 4315 def "" : InstVRRb<opcode, (outs VR128:$V1), 4316 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4317 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 4318 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4", 4319 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4320 imm32zx4:$M4, 0)>; 4321} 4322 4323class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4324 TypedReg tr1, TypedReg tr2> 4325 : InstVRRc<opcode, (outs tr1.op:$V1), 4326 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4), 4327 mnemonic#"\t$V1, $V2, $V3, $M4", 4328 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4329 (tr2.vt tr2.op:$V3), 4330 imm32zx4_timm:$M4))]> { 4331 let M5 = 0; 4332 let M6 = 0; 4333} 4334 4335class TernaryVRRcFloat<string mnemonic, bits<16> opcode, 4336 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 4337 bits<4> type = 0, bits<4> m5 = 0> 4338 : InstVRRc<opcode, (outs tr1.op:$V1), 4339 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6), 4340 mnemonic#"\t$V1, $V2, $V3, $M6", 4341 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4342 (tr2.vt tr2.op:$V3), 4343 imm32zx4_timm:$M6))]> { 4344 let M4 = type; 4345 let M5 = m5; 4346} 4347 4348class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode> 4349 : InstVRRc<opcode, (outs VR128:$V1), 4350 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 4351 imm32zx4:$M6), 4352 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>; 4353 4354class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4355 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m6 = 0> 4356 : InstVRRd<opcode, (outs tr1.op:$V1), 4357 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 4358 mnemonic#"\t$V1, $V2, $V3, $V4", 4359 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4360 (tr2.vt tr2.op:$V3), 4361 (tr1.vt tr1.op:$V4)))]> { 4362 let M5 = type; 4363 let M6 = m6; 4364} 4365 4366class TernaryVRRdGeneric<string mnemonic, bits<16> opcode> 4367 : InstVRRd<opcode, (outs VR128:$V1), 4368 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5), 4369 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> { 4370 let M6 = 0; 4371} 4372 4373// Ternary operation where the assembler mnemonic has an extra operand to 4374// optionally allow specifiying arbitrary M6 values. 4375multiclass TernaryExtraVRRd<string mnemonic, bits<16> opcode, 4376 SDPatternOperator operator, 4377 TypedReg tr1, TypedReg tr2, bits<4> type> { 4378 let M5 = type, Defs = [CC] in 4379 def "" : InstVRRd<opcode, (outs tr1.op:$V1), 4380 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6), 4381 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>; 4382 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3), 4383 (tr1.vt tr1.op:$V4)), 4384 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>; 4385 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 4386 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4387 tr2.op:$V3, tr1.op:$V4, 0)>; 4388} 4389 4390multiclass TernaryExtraVRRdGeneric<string mnemonic, bits<16> opcode> { 4391 let Defs = [CC] in 4392 def "" : InstVRRd<opcode, (outs VR128:$V1), 4393 (ins VR128:$V2, VR128:$V3, VR128:$V4, 4394 imm32zx4:$M5, imm32zx4:$M6), 4395 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4396 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5", 4397 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4398 VR128:$V4, imm32zx4:$M5, 0)>; 4399} 4400 4401class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4402 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0> 4403 : InstVRRe<opcode, (outs tr1.op:$V1), 4404 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 4405 mnemonic#"\t$V1, $V2, $V3, $V4", 4406 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4407 (tr2.vt tr2.op:$V3), 4408 (tr1.vt tr1.op:$V4)))]> { 4409 let M5 = m5; 4410 let M6 = type; 4411} 4412 4413class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode> 4414 : InstVRRe<opcode, (outs VR128:$V1), 4415 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6), 4416 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4417 4418class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4419 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type> 4420 : InstVRSb<opcode, (outs tr1.op:$V1), 4421 (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2), 4422 mnemonic#"\t$V1, $R3, $BD2", 4423 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4424 cls:$R3, 4425 shift12only:$BD2))]> { 4426 let Constraints = "$V1 = $V1src"; 4427 let DisableEncoding = "$V1src"; 4428 let M4 = type; 4429} 4430 4431class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4432 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, 4433 imm32zx4:$M3, imm32zx4:$M4), 4434 mnemonic#"\t$R1, $V2, $M3, $M4", []>; 4435 4436class TernaryVRSbGeneric<string mnemonic, bits<16> opcode> 4437 : InstVRSb<opcode, (outs VR128:$V1), 4438 (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4), 4439 mnemonic#"\t$V1, $R3, $BD2, $M4", []> { 4440 let Constraints = "$V1 = $V1src"; 4441 let DisableEncoding = "$V1src"; 4442} 4443 4444class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 4445 ImmOpWithPattern index> 4446 : InstVRV<opcode, (outs VR128:$V1), 4447 (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3), 4448 mnemonic#"\t$V1, $VBD2, $M3", []> { 4449 let Constraints = "$V1 = $V1src"; 4450 let DisableEncoding = "$V1src"; 4451 let mayLoad = 1; 4452 let AccessBytes = bytes; 4453} 4454 4455class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4456 TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index> 4457 : InstVRX<opcode, (outs tr1.op:$V1), 4458 (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3), 4459 mnemonic#"\t$V1, $XBD2, $M3", 4460 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4461 bdxaddr12only:$XBD2, 4462 index:$M3))]> { 4463 let Constraints = "$V1 = $V1src"; 4464 let DisableEncoding = "$V1src"; 4465 let mayLoad = 1; 4466 let AccessBytes = bytes; 4467} 4468 4469class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4470 TypedReg tr1, TypedReg tr2, bits<4> type> 4471 : InstVRId<opcode, (outs tr1.op:$V1), 4472 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 4473 mnemonic#"\t$V1, $V2, $V3, $I4", 4474 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4475 (tr2.vt tr2.op:$V2), 4476 (tr2.vt tr2.op:$V3), 4477 imm32zx8_timm:$I4))]> { 4478 let Constraints = "$V1 = $V1src"; 4479 let DisableEncoding = "$V1src"; 4480 let M5 = type; 4481} 4482 4483class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode> 4484 : InstVRId<opcode, (outs VR128:$V1), 4485 (ins VR128:$V1src, VR128:$V2, VR128:$V3, 4486 imm32zx8:$I4, imm32zx4:$M5), 4487 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> { 4488 let Constraints = "$V1 = $V1src"; 4489 let DisableEncoding = "$V1src"; 4490} 4491 4492class QuaternaryVRIf<string mnemonic, bits<16> opcode> 4493 : InstVRIf<opcode, (outs VR128:$V1), 4494 (ins VR128:$V2, VR128:$V3, 4495 imm32zx8:$I4, imm32zx4:$M5), 4496 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>; 4497 4498class QuaternaryVRIg<string mnemonic, bits<16> opcode> 4499 : InstVRIg<opcode, (outs VR128:$V1), 4500 (ins VR128:$V2, imm32zx8:$I3, 4501 imm32zx8:$I4, imm32zx4:$M5), 4502 mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>; 4503 4504class QuaternaryVRRd<string mnemonic, bits<16> opcode, 4505 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 4506 TypedReg tr3, TypedReg tr4, bits<4> type, 4507 SDPatternOperator m6mask = imm32zx4_timm, bits<4> m6or = 0> 4508 : InstVRRd<opcode, (outs tr1.op:$V1), 4509 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6), 4510 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", 4511 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4512 (tr3.vt tr3.op:$V3), 4513 (tr4.vt tr4.op:$V4), 4514 m6mask:$M6))], 4515 m6or> { 4516 let M5 = type; 4517} 4518 4519class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode> 4520 : InstVRRd<opcode, (outs VR128:$V1), 4521 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6), 4522 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4523 4524// Declare a pair of instructions, one which sets CC and one which doesn't. 4525// The CC-setting form ends with "S" and sets the low bit of M6. 4526// Also create aliases to make use of M6 operand optional in assembler. 4527multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode, 4528 SDPatternOperator operator, 4529 SDPatternOperator operator_cc, 4530 TypedReg tr1, TypedReg tr2, bits<4> type, 4531 bits<4> modifier = 0> { 4532 def "" : QuaternaryVRRd<mnemonic, opcode, operator, 4533 tr1, tr2, tr2, tr2, type, 4534 imm32zx4even_timm, !and (modifier, 14)>; 4535 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 4536 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4537 tr2.op:$V3, tr2.op:$V4, 0)>; 4538 let Defs = [CC] in 4539 def S : QuaternaryVRRd<mnemonic##"s", opcode, operator_cc, 4540 tr1, tr2, tr2, tr2, type, 4541 imm32zx4even_timm, !add (!and (modifier, 14), 1)>; 4542 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4", 4543 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 4544 tr2.op:$V3, tr2.op:$V4, 0)>; 4545} 4546 4547multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> { 4548 let Defs = [CC] in 4549 def "" : QuaternaryVRRdGeneric<mnemonic, opcode>; 4550 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5", 4551 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4552 VR128:$V4, imm32zx4_timm:$M5, 0)>; 4553} 4554 4555class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode, 4556 RegisterOperand cls1, RegisterOperand cls2, 4557 RegisterOperand cls3> 4558 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), 4559 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 4560 4561multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode, 4562 RegisterOperand cls1, 4563 RegisterOperand cls2, 4564 RegisterOperand cls3> { 4565 def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 4566 def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 4567 def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>; 4568} 4569 4570class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode, 4571 RegisterOperand cls1, RegisterOperand cls2, 4572 RegisterOperand cls3> 4573 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), 4574 mnemonic#"\t$R1, $R3, $R2, $M4", []>; 4575 4576multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode, 4577 RegisterOperand cls1, 4578 RegisterOperand cls2, 4579 RegisterOperand cls3> { 4580 def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; 4581 def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; 4582} 4583 4584class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode, 4585 RegisterOperand cls> 4586 : InstSSe<opcode, (outs), 4587 (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4), 4588 mnemonic#"\t$R1, $BD2, $R3, $BD4", []>; 4589 4590class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4591 RegisterOperand cls, AddressingMode mode = bdaddr20only> 4592 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2), 4593 mnemonic#"\t$R1, $R3, $BD2", 4594 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> { 4595 let mayLoad = 1; 4596 let mayStore = 1; 4597} 4598 4599class CmpSwapRRE<string mnemonic, bits<16> opcode, 4600 RegisterOperand cls1, RegisterOperand cls2> 4601 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 4602 mnemonic#"\t$R1, $R2", []> { 4603 let Constraints = "$R1 = $R1src"; 4604 let DisableEncoding = "$R1src"; 4605 let mayLoad = 1; 4606 let mayStore = 1; 4607} 4608 4609class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 4610 RegisterOperand cls, AddressingMode mode = bdaddr12only> 4611 : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 4612 mnemonic#"\t$R1, $R3, $BD2", 4613 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 4614 let Constraints = "$R1 = $R1src"; 4615 let DisableEncoding = "$R1src"; 4616 let mayLoad = 1; 4617 let mayStore = 1; 4618} 4619 4620class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4621 RegisterOperand cls, AddressingMode mode = bdaddr20only> 4622 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2), 4623 mnemonic#"\t$R1, $R3, $BD2", 4624 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 4625 let Constraints = "$R1 = $R1src"; 4626 let DisableEncoding = "$R1src"; 4627 let mayLoad = 1; 4628 let mayStore = 1; 4629} 4630 4631multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 4632 SDPatternOperator operator, RegisterOperand cls> { 4633 let DispKey = mnemonic ## #cls in { 4634 let DispSize = "12" in 4635 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>; 4636 let DispSize = "20" in 4637 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>; 4638 } 4639} 4640 4641class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1, 4642 RegisterOperand cls2> 4643 : InstRIEf<opcode, (outs cls1:$R1), 4644 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 4645 imm32zx6:$I5), 4646 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> { 4647 let Constraints = "$R1 = $R1src"; 4648 let DisableEncoding = "$R1src"; 4649} 4650 4651class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator> 4652 : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2), 4653 mnemonic##"\t$M1, $XBD2", 4654 [(operator imm32zx4_timm:$M1, bdxaddr20only:$XBD2)]>; 4655 4656class PrefetchRILPC<string mnemonic, bits<12> opcode, 4657 SDPatternOperator operator> 4658 : InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2), 4659 mnemonic##"\t$M1, $RI2", 4660 [(operator imm32zx4_timm:$M1, pcrel32:$RI2)]> { 4661 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 4662 // However, BDXs have two extra operands and are therefore 6 units more 4663 // complex. 4664 let AddedComplexity = 7; 4665} 4666 4667class BranchPreloadSMI<string mnemonic, bits<8> opcode> 4668 : InstSMI<opcode, (outs), 4669 (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3), 4670 mnemonic#"\t$M1, $RI2, $BD3", []>; 4671 4672class BranchPreloadMII<string mnemonic, bits<8> opcode> 4673 : InstMII<opcode, (outs), 4674 (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3), 4675 mnemonic#"\t$M1, $RI2, $RI3", []>; 4676 4677// A floating-point load-and test operation. Create both a normal unary 4678// operation and one that acts as a comparison against zero. 4679// Note that the comparison against zero operation is not available if we 4680// have vector support, since load-and-test instructions will partially 4681// clobber the target (vector) register. 4682multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode, 4683 RegisterOperand cls> { 4684 def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>; 4685 let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in 4686 def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>; 4687} 4688 4689//===----------------------------------------------------------------------===// 4690// Pseudo instructions 4691//===----------------------------------------------------------------------===// 4692// 4693// Convenience instructions that get lowered to real instructions 4694// by either SystemZTargetLowering::EmitInstrWithCustomInserter() 4695// or SystemZInstrInfo::expandPostRAPseudo(). 4696// 4697//===----------------------------------------------------------------------===// 4698 4699class Pseudo<dag outs, dag ins, list<dag> pattern> 4700 : InstSystemZ<0, outs, ins, "", pattern> { 4701 let isPseudo = 1; 4702 let isCodeGenOnly = 1; 4703} 4704 4705// Like UnaryRI, but expanded after RA depending on the choice of register. 4706class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 4707 ImmOpWithPattern imm> 4708 : Pseudo<(outs cls:$R1), (ins imm:$I2), 4709 [(set cls:$R1, (operator imm:$I2))]>; 4710 4711// Like UnaryRXY, but expanded after RA depending on the choice of register. 4712class UnaryRXYPseudo<string key, SDPatternOperator operator, 4713 RegisterOperand cls, bits<5> bytes, 4714 AddressingMode mode = bdxaddr20only> 4715 : Pseudo<(outs cls:$R1), (ins mode:$XBD2), 4716 [(set cls:$R1, (operator mode:$XBD2))]> { 4717 let OpKey = key#"r"#cls; 4718 let OpType = "mem"; 4719 let mayLoad = 1; 4720 let Has20BitOffset = 1; 4721 let HasIndex = 1; 4722 let AccessBytes = bytes; 4723} 4724 4725// Like UnaryRR, but expanded after RA depending on the choice of registers. 4726class UnaryRRPseudo<string key, SDPatternOperator operator, 4727 RegisterOperand cls1, RegisterOperand cls2> 4728 : Pseudo<(outs cls1:$R1), (ins cls2:$R2), 4729 [(set cls1:$R1, (operator cls2:$R2))]> { 4730 let OpKey = key#cls1; 4731 let OpType = "reg"; 4732} 4733 4734// Like BinaryRI, but expanded after RA depending on the choice of register. 4735class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 4736 ImmOpWithPattern imm> 4737 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2), 4738 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 4739 let Constraints = "$R1 = $R1src"; 4740} 4741 4742// Like BinaryRIE, but expanded after RA depending on the choice of register. 4743class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls, 4744 ImmOpWithPattern imm> 4745 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2), 4746 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 4747 4748// Like BinaryRIAndK, but expanded after RA depending on the choice of register. 4749multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator, 4750 RegisterOperand cls, ImmOpWithPattern imm> { 4751 let NumOpsKey = key in { 4752 let NumOpsValue = "3" in 4753 def K : BinaryRIEPseudo<operator, cls, imm>, 4754 Requires<[FeatureHighWord, FeatureDistinctOps]>; 4755 let NumOpsValue = "2" in 4756 def "" : BinaryRIPseudo<operator, cls, imm>, 4757 Requires<[FeatureHighWord]>; 4758 } 4759} 4760 4761// A pseudo that is used during register allocation when folding a memory 4762// operand. The 3-address register instruction with a spilled source cannot 4763// be converted directly to a target 2-address reg/mem instruction. 4764// Mapping: <INSN>R -> MemFoldPseudo -> <INSN> 4765class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes, 4766 AddressingMode mode> 4767 : Pseudo<(outs cls:$R1), (ins cls:$R2, mode:$XBD2), []> { 4768 let OpKey = mnemonic#"rk"#cls; 4769 let OpType = "mem"; 4770 let MemKey = mnemonic#cls; 4771 let MemType = "pseudo"; 4772 let mayLoad = 1; 4773 let AccessBytes = bytes; 4774 let HasIndex = 1; 4775 let hasNoSchedulingInfo = 1; 4776} 4777 4778// Like CompareRI, but expanded after RA depending on the choice of register. 4779class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls, 4780 ImmOpWithPattern imm> 4781 : Pseudo<(outs), (ins cls:$R1, imm:$I2), 4782 [(set CC, (operator cls:$R1, imm:$I2))]> { 4783 let isCompare = 1; 4784} 4785 4786// Like CompareRXY, but expanded after RA depending on the choice of register. 4787class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 4788 SDPatternOperator load, bits<5> bytes, 4789 AddressingMode mode = bdxaddr20only> 4790 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2), 4791 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 4792 let mayLoad = 1; 4793 let Has20BitOffset = 1; 4794 let HasIndex = 1; 4795 let AccessBytes = bytes; 4796} 4797 4798// Like TestBinarySIL, but expanded later. 4799class TestBinarySILPseudo<SDPatternOperator operator, ImmOpWithPattern imm> 4800 : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2), 4801 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>; 4802 4803// Like CondBinaryRRF, but expanded after RA depending on the choice of 4804// register. 4805class CondBinaryRRFPseudo<string mnemonic, RegisterOperand cls1, 4806 RegisterOperand cls2> 4807 : Pseudo<(outs cls1:$R1), 4808 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), 4809 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src, 4810 cond4:$valid, cond4:$M3))]> { 4811 let Constraints = "$R1 = $R1src"; 4812 let DisableEncoding = "$R1src"; 4813 let CCMaskLast = 1; 4814 let NumOpsKey = !subst("loc", "sel", mnemonic); 4815 let NumOpsValue = "2"; 4816} 4817 4818// Like CondBinaryRRFa, but expanded after RA depending on the choice of 4819// register. 4820class CondBinaryRRFaPseudo<string mnemonic, RegisterOperand cls1, 4821 RegisterOperand cls2, RegisterOperand cls3> 4822 : Pseudo<(outs cls1:$R1), 4823 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4), 4824 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3, 4825 cond4:$valid, cond4:$M4))]> { 4826 let CCMaskLast = 1; 4827 let NumOpsKey = mnemonic; 4828 let NumOpsValue = "3"; 4829} 4830 4831// Like CondBinaryRIE, but expanded after RA depending on the choice of 4832// register. 4833class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm> 4834 : Pseudo<(outs cls:$R1), 4835 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3), 4836 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src, 4837 cond4:$valid, cond4:$M3))]> { 4838 let Constraints = "$R1 = $R1src"; 4839 let DisableEncoding = "$R1src"; 4840 let CCMaskLast = 1; 4841} 4842 4843// Like CondUnaryRSY, but expanded after RA depending on the choice of 4844// register. 4845class CondUnaryRSYPseudo<SDPatternOperator operator, RegisterOperand cls, 4846 bits<5> bytes, AddressingMode mode = bdaddr20only> 4847 : Pseudo<(outs cls:$R1), 4848 (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3), 4849 [(set cls:$R1, 4850 (z_select_ccmask (operator mode:$BD2), cls:$R1src, 4851 cond4:$valid, cond4:$R3))]> { 4852 let Constraints = "$R1 = $R1src"; 4853 let DisableEncoding = "$R1src"; 4854 let mayLoad = 1; 4855 let AccessBytes = bytes; 4856 let CCMaskLast = 1; 4857} 4858 4859// Like CondStoreRSY, but expanded after RA depending on the choice of 4860// register. 4861class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes, 4862 AddressingMode mode = bdaddr20only> 4863 : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> { 4864 let mayStore = 1; 4865 let AccessBytes = bytes; 4866 let CCMaskLast = 1; 4867} 4868 4869// Like StoreRXY, but expanded after RA depending on the choice of register. 4870class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 4871 bits<5> bytes, AddressingMode mode = bdxaddr20only> 4872 : Pseudo<(outs), (ins cls:$R1, mode:$XBD2), 4873 [(operator cls:$R1, mode:$XBD2)]> { 4874 let mayStore = 1; 4875 let Has20BitOffset = 1; 4876 let HasIndex = 1; 4877 let AccessBytes = bytes; 4878} 4879 4880// Like RotateSelectRIEf, but expanded after RA depending on the choice 4881// of registers. 4882class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2> 4883 : Pseudo<(outs cls1:$R1), 4884 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 4885 imm32zx6:$I5), 4886 []> { 4887 let Constraints = "$R1 = $R1src"; 4888 let DisableEncoding = "$R1src"; 4889} 4890 4891// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is 4892// the value of the PSW's 2-bit condition code field. 4893class SelectWrapper<ValueType vt, RegisterOperand cls> 4894 : Pseudo<(outs cls:$dst), 4895 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc), 4896 [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2, 4897 imm32zx4_timm:$valid, imm32zx4_timm:$cc))]> { 4898 let usesCustomInserter = 1; 4899 let hasNoSchedulingInfo = 1; 4900 let Uses = [CC]; 4901} 4902 4903// Stores $new to $addr if $cc is true ("" case) or false (Inv case). 4904multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 4905 SDPatternOperator load, AddressingMode mode> { 4906 let Uses = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1, 4907 mayLoad = 1, mayStore = 1 in { 4908 def "" : Pseudo<(outs), 4909 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 4910 [(store (z_select_ccmask cls:$new, (load mode:$addr), 4911 imm32zx4_timm:$valid, imm32zx4_timm:$cc), 4912 mode:$addr)]>; 4913 def Inv : Pseudo<(outs), 4914 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 4915 [(store (z_select_ccmask (load mode:$addr), cls:$new, 4916 imm32zx4_timm:$valid, imm32zx4_timm:$cc), 4917 mode:$addr)]>; 4918 } 4919} 4920 4921// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND 4922// describe the second (non-memory) operand. 4923class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls, 4924 dag pat, DAGOperand operand> 4925 : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2), 4926 [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> { 4927 let Defs = [CC]; 4928 let Has20BitOffset = 1; 4929 let mayLoad = 1; 4930 let mayStore = 1; 4931 let usesCustomInserter = 1; 4932 let hasNoSchedulingInfo = 1; 4933} 4934 4935// Specializations of AtomicLoadWBinary. 4936class AtomicLoadBinaryReg32<SDPatternOperator operator> 4937 : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>; 4938class AtomicLoadBinaryImm32<SDPatternOperator operator, ImmOpWithPattern imm> 4939 : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>; 4940class AtomicLoadBinaryReg64<SDPatternOperator operator> 4941 : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>; 4942class AtomicLoadBinaryImm64<SDPatternOperator operator, ImmOpWithPattern imm> 4943 : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>; 4944 4945// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND 4946// describe the second (non-memory) operand. 4947class AtomicLoadWBinary<SDPatternOperator operator, dag pat, 4948 DAGOperand operand> 4949 : Pseudo<(outs GR32:$dst), 4950 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift, 4951 ADDR32:$negbitshift, uimm32:$bitsize), 4952 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift, 4953 ADDR32:$negbitshift, uimm32:$bitsize))]> { 4954 let Defs = [CC]; 4955 let Has20BitOffset = 1; 4956 let mayLoad = 1; 4957 let mayStore = 1; 4958 let usesCustomInserter = 1; 4959 let hasNoSchedulingInfo = 1; 4960} 4961 4962// Specializations of AtomicLoadWBinary. 4963class AtomicLoadWBinaryReg<SDPatternOperator operator> 4964 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>; 4965class AtomicLoadWBinaryImm<SDPatternOperator operator, ImmOpWithPattern imm> 4966 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>; 4967 4968// A pseudo instruction that is a direct alias of a real instruction. 4969// These aliases are used in cases where a particular register operand is 4970// fixed or where the same instruction is used with different register sizes. 4971// The size parameter is the size in bytes of the associated real instruction. 4972class Alias<int size, dag outs, dag ins, list<dag> pattern> 4973 : InstSystemZ<size, outs, ins, "", pattern> { 4974 let isPseudo = 1; 4975 let isCodeGenOnly = 1; 4976} 4977 4978class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2> 4979 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>; 4980 4981// An alias of a UnaryVRR*, but with different register sizes. 4982class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2> 4983 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2), 4984 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>; 4985 4986// An alias of a UnaryVRX, but with different register sizes. 4987class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr, 4988 AddressingMode mode = bdxaddr12only> 4989 : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2), 4990 [(set (tr.vt tr.op:$V1), (operator mode:$XBD2))]>; 4991 4992// An alias of a StoreVRX, but with different register sizes. 4993class StoreAliasVRX<SDPatternOperator operator, TypedReg tr, 4994 AddressingMode mode = bdxaddr12only> 4995 : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2), 4996 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>; 4997 4998// An alias of a BinaryRI, but with different register sizes. 4999class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls, 5000 ImmOpWithPattern imm> 5001 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 5002 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5003 let Constraints = "$R1 = $R1src"; 5004} 5005 5006// An alias of a BinaryRIL, but with different register sizes. 5007class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls, 5008 ImmOpWithPattern imm> 5009 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 5010 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5011 let Constraints = "$R1 = $R1src"; 5012} 5013 5014// An alias of a BinaryVRRf, but with different register sizes. 5015class BinaryAliasVRRf<RegisterOperand cls> 5016 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>; 5017 5018// An alias of a CompareRI, but with different register sizes. 5019class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls, 5020 ImmOpWithPattern imm> 5021 : Alias<4, (outs), (ins cls:$R1, imm:$I2), 5022 [(set CC, (operator cls:$R1, imm:$I2))]> { 5023 let isCompare = 1; 5024} 5025 5026// An alias of a RotateSelectRIEf, but with different register sizes. 5027class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2> 5028 : Alias<6, (outs cls1:$R1), 5029 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 5030 imm32zx6:$I5), []> { 5031 let Constraints = "$R1 = $R1src"; 5032} 5033 5034//===----------------------------------------------------------------------===// 5035// Multiclasses that emit both real and pseudo instructions 5036//===----------------------------------------------------------------------===// 5037 5038multiclass BinaryRXYAndPseudo<string mnemonic, bits<16> opcode, 5039 SDPatternOperator operator, RegisterOperand cls, 5040 SDPatternOperator load, bits<5> bytes, 5041 AddressingMode mode = bdxaddr20only> { 5042 5043 def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> { 5044 let MemKey = mnemonic#cls; 5045 let MemType = "target"; 5046 } 5047 let Has20BitOffset = 1 in 5048 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, mode>; 5049} 5050 5051multiclass BinaryRXPairAndPseudo<string mnemonic, bits<8> rxOpcode, 5052 bits<16> rxyOpcode, SDPatternOperator operator, 5053 RegisterOperand cls, 5054 SDPatternOperator load, bits<5> bytes> { 5055 let DispKey = mnemonic ## #cls in { 5056 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 5057 bdxaddr12pair> { 5058 let DispSize = "12"; 5059 let MemKey = mnemonic#cls; 5060 let MemType = "target"; 5061 } 5062 let DispSize = "20" in 5063 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, 5064 bytes, bdxaddr20pair>; 5065 } 5066 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>; 5067} 5068 5069// Define an instruction that operates on two fixed-length blocks of memory, 5070// and associated pseudo instructions for operating on blocks of any size. 5071// The Sequence form uses a straight-line sequence of instructions and 5072// the Loop form uses a loop of length-256 instructions followed by 5073// another instruction to handle the excess. 5074multiclass MemorySS<string mnemonic, bits<8> opcode, 5075 SDPatternOperator sequence, SDPatternOperator loop> { 5076 def "" : SideEffectBinarySSa<mnemonic, opcode>; 5077 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [CC] in { 5078 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5079 imm64:$length), 5080 [(sequence bdaddr12only:$dest, bdaddr12only:$src, 5081 imm64:$length)]>; 5082 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5083 imm64:$length, GR64:$count256), 5084 [(loop bdaddr12only:$dest, bdaddr12only:$src, 5085 imm64:$length, GR64:$count256)]>; 5086 } 5087} 5088 5089// The same, but setting a CC result as comparion operator. 5090multiclass CompareMemorySS<string mnemonic, bits<8> opcode, 5091 SDPatternOperator sequence, SDPatternOperator loop> { 5092 def "" : SideEffectBinarySSa<mnemonic, opcode>; 5093 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 5094 def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5095 imm64:$length), 5096 [(set CC, (sequence bdaddr12only:$dest, bdaddr12only:$src, 5097 imm64:$length))]>; 5098 def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5099 imm64:$length, GR64:$count256), 5100 [(set CC, (loop bdaddr12only:$dest, bdaddr12only:$src, 5101 imm64:$length, GR64:$count256))]>; 5102 } 5103} 5104 5105// Define an instruction that operates on two strings, both terminated 5106// by the character in R0. The instruction processes a CPU-determinated 5107// number of bytes at a time and sets CC to 3 if the instruction needs 5108// to be repeated. Also define a pseudo instruction that represents 5109// the full loop (the main instruction plus the branch on CC==3). 5110multiclass StringRRE<string mnemonic, bits<16> opcode, 5111 SDPatternOperator operator> { 5112 let Uses = [R0L] in 5113 def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>; 5114 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 5115 def Loop : Pseudo<(outs GR64:$end), 5116 (ins GR64:$start1, GR64:$start2, GR32:$char), 5117 [(set GR64:$end, (operator GR64:$start1, GR64:$start2, 5118 GR32:$char))]>; 5119} 5120