1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Basic SystemZ instruction definition 11//===----------------------------------------------------------------------===// 12 13class InstSystemZ<int size, dag outs, dag ins, string asmstr, 14 list<dag> pattern> : Instruction { 15 let Namespace = "SystemZ"; 16 17 dag OutOperandList = outs; 18 dag InOperandList = ins; 19 let Size = size; 20 let Pattern = pattern; 21 let AsmString = asmstr; 22 23 let hasSideEffects = 0; 24 let mayLoad = 0; 25 let mayStore = 0; 26 27 // Some instructions come in pairs, one having a 12-bit displacement 28 // and the other having a 20-bit displacement. Both instructions in 29 // the pair have the same DispKey and their DispSizes are "12" and "20" 30 // respectively. 31 string DispKey = ""; 32 string DispSize = "none"; 33 34 // Many register-based <INSN>R instructions have a memory-based <INSN> 35 // counterpart. OpKey uniquely identifies <INSN>R, while OpType is 36 // "reg" for <INSN>R and "mem" for <INSN>. 37 string OpKey = ""; 38 string OpType = "none"; 39 40 // MemKey identifies a targe reg-mem opcode, while MemType can be either 41 // "pseudo" or "target". This is used to map a pseduo memory instruction to 42 // its corresponding target opcode. See comment at MemFoldPseudo. 43 string MemKey = ""; 44 string MemType = "none"; 45 46 // Many distinct-operands instructions have older 2-operand equivalents. 47 // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs, 48 // with NumOpsValue being "2" or "3" as appropriate. 49 string NumOpsKey = ""; 50 string NumOpsValue = "none"; 51 52 // True if this instruction is a simple D(X,B) load of a register 53 // (with no sign or zero extension). 54 bit SimpleBDXLoad = 0; 55 56 // True if this instruction is a simple D(X,B) store of a register 57 // (with no truncation). 58 bit SimpleBDXStore = 0; 59 60 // True if this instruction has a 20-bit displacement field. 61 bit Has20BitOffset = 0; 62 63 // True if addresses in this instruction have an index register. 64 bit HasIndex = 0; 65 66 // True if this is a 128-bit pseudo instruction that combines two 64-bit 67 // operations. 68 bit Is128Bit = 0; 69 70 // The access size of all memory operands in bytes, or 0 if not known. 71 bits<5> AccessBytes = 0; 72 73 // If the instruction sets CC to a useful value, this gives the mask 74 // of all possible CC results. The mask has the same form as 75 // SystemZ::CCMASK_*. 76 bits<4> CCValues = 0; 77 78 // The subset of CCValues that have the same meaning as they would after a 79 // comparison of the first operand against zero. "Logical" instructions 80 // leave this blank as they set CC in a different way. 81 bits<4> CompareZeroCCMask = 0; 82 83 // True if the instruction is conditional and if the CC mask operand 84 // comes first (as for BRC, etc.). 85 bit CCMaskFirst = 0; 86 87 // Similar, but true if the CC mask operand comes last (as for LOC, etc.). 88 bit CCMaskLast = 0; 89 90 // True if the instruction is the "logical" rather than "arithmetic" form, 91 // in cases where a distinction exists. Except for logical compares, if the 92 // instruction sets this flag along with a non-zero CCValues field, it is 93 // assumed to set CC to either CCMASK_LOGICAL_ZERO or 94 // CCMASK_LOGICAL_NONZERO. 95 bit IsLogical = 0; 96 97 // True if the (add or sub) instruction sets CC like a compare of the 98 // result against zero, but only if the 'nsw' flag is set. 99 bit CCIfNoSignedWrap = 0; 100 101 let TSFlags{0} = SimpleBDXLoad; 102 let TSFlags{1} = SimpleBDXStore; 103 let TSFlags{2} = Has20BitOffset; 104 let TSFlags{3} = HasIndex; 105 let TSFlags{4} = Is128Bit; 106 let TSFlags{9-5} = AccessBytes; 107 let TSFlags{13-10} = CCValues; 108 let TSFlags{17-14} = CompareZeroCCMask; 109 let TSFlags{18} = CCMaskFirst; 110 let TSFlags{19} = CCMaskLast; 111 let TSFlags{20} = IsLogical; 112 let TSFlags{21} = CCIfNoSignedWrap; 113} 114 115//===----------------------------------------------------------------------===// 116// Mappings between instructions 117//===----------------------------------------------------------------------===// 118 119// Return the version of an instruction that has an unsigned 12-bit 120// displacement. 121def getDisp12Opcode : InstrMapping { 122 let FilterClass = "InstSystemZ"; 123 let RowFields = ["DispKey"]; 124 let ColFields = ["DispSize"]; 125 let KeyCol = ["20"]; 126 let ValueCols = [["12"]]; 127} 128 129// Return the version of an instruction that has a signed 20-bit displacement. 130def getDisp20Opcode : InstrMapping { 131 let FilterClass = "InstSystemZ"; 132 let RowFields = ["DispKey"]; 133 let ColFields = ["DispSize"]; 134 let KeyCol = ["12"]; 135 let ValueCols = [["20"]]; 136} 137 138// Return the memory form of a register instruction. Note that this may 139// return a MemFoldPseudo instruction (see below). 140def getMemOpcode : InstrMapping { 141 let FilterClass = "InstSystemZ"; 142 let RowFields = ["OpKey"]; 143 let ColFields = ["OpType"]; 144 let KeyCol = ["reg"]; 145 let ValueCols = [["mem"]]; 146} 147 148// Return the target memory instruction for a MemFoldPseudo. 149def getTargetMemOpcode : InstrMapping { 150 let FilterClass = "InstSystemZ"; 151 let RowFields = ["MemKey"]; 152 let ColFields = ["MemType"]; 153 let KeyCol = ["pseudo"]; 154 let ValueCols = [["target"]]; 155} 156 157// Return the 2-operand form of a 3-operand instruction. 158def getTwoOperandOpcode : InstrMapping { 159 let FilterClass = "InstSystemZ"; 160 let RowFields = ["NumOpsKey"]; 161 let ColFields = ["NumOpsValue"]; 162 let KeyCol = ["3"]; 163 let ValueCols = [["2"]]; 164} 165 166//===----------------------------------------------------------------------===// 167// Instruction formats 168//===----------------------------------------------------------------------===// 169// 170// Formats are specified using operand field declarations of the form: 171// 172// bits<4> Rn : register input or output for operand n 173// bits<5> Vn : vector register input or output for operand n 174// bits<m> In : immediate value of width m for operand n 175// bits<4> Bn : base register for address operand n 176// bits<m> Dn : displacement for address operand n 177// bits<5> Vn : vector index for address operand n 178// bits<4> Xn : index register for address operand n 179// bits<4> Mn : mode value for operand n 180// 181// The operand numbers ("n" in the list above) follow the architecture manual. 182// Assembly operands sometimes have a different order; in particular, R3 often 183// is often written between operands 1 and 2. 184// 185//===----------------------------------------------------------------------===// 186 187class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 188 : InstSystemZ<2, outs, ins, asmstr, pattern> { 189 field bits<16> Inst; 190 field bits<16> SoftFail = 0; 191 192 let Inst = op; 193} 194 195class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 196 : InstSystemZ<2, outs, ins, asmstr, pattern> { 197 field bits<16> Inst; 198 field bits<16> SoftFail = 0; 199 200 bits<8> I1; 201 202 let Inst{15-8} = op; 203 let Inst{7-0} = I1; 204} 205 206class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 207 : InstSystemZ<4, outs, ins, asmstr, pattern> { 208 field bits<32> Inst; 209 field bits<32> SoftFail = 0; 210 211 bits<4> I1; 212 bits<4> I2; 213 214 let Inst{31-16} = op; 215 let Inst{15-8} = 0; 216 let Inst{7-4} = I1; 217 let Inst{3-0} = I2; 218} 219 220class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 221 : InstSystemZ<6, outs, ins, asmstr, pattern> { 222 field bits<48> Inst; 223 field bits<48> SoftFail = 0; 224 225 bits<4> M1; 226 bits<12> RI2; 227 bits<24> RI3; 228 229 let Inst{47-40} = op; 230 let Inst{39-36} = M1; 231 let Inst{35-24} = RI2; 232 let Inst{23-0} = RI3; 233} 234 235class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 236 : InstSystemZ<4, outs, ins, asmstr, pattern> { 237 field bits<32> Inst; 238 field bits<32> SoftFail = 0; 239 240 bits<4> R1; 241 bits<16> I2; 242 243 let Inst{31-24} = op{11-4}; 244 let Inst{23-20} = R1; 245 let Inst{19-16} = op{3-0}; 246 let Inst{15-0} = I2; 247} 248 249class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 250 : InstSystemZ<4, outs, ins, asmstr, pattern> { 251 field bits<32> Inst; 252 field bits<32> SoftFail = 0; 253 254 bits<4> R1; 255 bits<16> RI2; 256 257 let Inst{31-24} = op{11-4}; 258 let Inst{23-20} = R1; 259 let Inst{19-16} = op{3-0}; 260 let Inst{15-0} = RI2; 261} 262 263class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 264 : InstSystemZ<4, outs, ins, asmstr, pattern> { 265 field bits<32> Inst; 266 field bits<32> SoftFail = 0; 267 268 bits<4> M1; 269 bits<16> RI2; 270 271 let Inst{31-24} = op{11-4}; 272 let Inst{23-20} = M1; 273 let Inst{19-16} = op{3-0}; 274 let Inst{15-0} = RI2; 275} 276 277class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 278 : InstSystemZ<6, outs, ins, asmstr, pattern> { 279 field bits<48> Inst; 280 field bits<48> SoftFail = 0; 281 282 bits<4> R1; 283 bits<16> I2; 284 bits<4> M3; 285 286 let Inst{47-40} = op{15-8}; 287 let Inst{39-36} = R1; 288 let Inst{35-32} = 0; 289 let Inst{31-16} = I2; 290 let Inst{15-12} = M3; 291 let Inst{11-8} = 0; 292 let Inst{7-0} = op{7-0}; 293} 294 295class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 296 : InstSystemZ<6, outs, ins, asmstr, pattern> { 297 field bits<48> Inst; 298 field bits<48> SoftFail = 0; 299 300 bits<4> R1; 301 bits<4> R2; 302 bits<4> M3; 303 bits<16> RI4; 304 305 let Inst{47-40} = op{15-8}; 306 let Inst{39-36} = R1; 307 let Inst{35-32} = R2; 308 let Inst{31-16} = RI4; 309 let Inst{15-12} = M3; 310 let Inst{11-8} = 0; 311 let Inst{7-0} = op{7-0}; 312} 313 314class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 315 : InstSystemZ<6, outs, ins, asmstr, pattern> { 316 field bits<48> Inst; 317 field bits<48> SoftFail = 0; 318 319 bits<4> R1; 320 bits<8> I2; 321 bits<4> M3; 322 bits<16> RI4; 323 324 let Inst{47-40} = op{15-8}; 325 let Inst{39-36} = R1; 326 let Inst{35-32} = M3; 327 let Inst{31-16} = RI4; 328 let Inst{15-8} = I2; 329 let Inst{7-0} = op{7-0}; 330} 331 332class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 333 : InstSystemZ<6, outs, ins, asmstr, pattern> { 334 field bits<48> Inst; 335 field bits<48> SoftFail = 0; 336 337 bits<4> R1; 338 bits<4> R3; 339 bits<16> I2; 340 341 let Inst{47-40} = op{15-8}; 342 let Inst{39-36} = R1; 343 let Inst{35-32} = R3; 344 let Inst{31-16} = I2; 345 let Inst{15-8} = 0; 346 let Inst{7-0} = op{7-0}; 347} 348 349class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 350 : InstSystemZ<6, outs, ins, asmstr, pattern> { 351 field bits<48> Inst; 352 field bits<48> SoftFail = 0; 353 354 bits<4> R1; 355 bits<4> R3; 356 bits<16> RI2; 357 358 let Inst{47-40} = op{15-8}; 359 let Inst{39-36} = R1; 360 let Inst{35-32} = R3; 361 let Inst{31-16} = RI2; 362 let Inst{15-8} = 0; 363 let Inst{7-0} = op{7-0}; 364} 365 366class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 367 bits<8> I3Or = 0, bits<8> I4Or = 0> 368 : InstSystemZ<6, outs, ins, asmstr, pattern> { 369 field bits<48> Inst; 370 field bits<48> SoftFail = 0; 371 372 bits<4> R1; 373 bits<4> R2; 374 bits<8> I3; 375 bits<8> I4; 376 bits<8> I5; 377 378 let Inst{47-40} = op{15-8}; 379 let Inst{39-36} = R1; 380 let Inst{35-32} = R2; 381 let Inst{31} = !if(I3Or{7}, 1, I3{7}); 382 let Inst{30} = !if(I3Or{6}, 1, I3{6}); 383 let Inst{29} = !if(I3Or{5}, 1, I3{5}); 384 let Inst{28} = !if(I3Or{4}, 1, I3{4}); 385 let Inst{27} = !if(I3Or{3}, 1, I3{3}); 386 let Inst{26} = !if(I3Or{2}, 1, I3{2}); 387 let Inst{25} = !if(I3Or{1}, 1, I3{1}); 388 let Inst{24} = !if(I3Or{0}, 1, I3{0}); 389 let Inst{23} = !if(I4Or{7}, 1, I4{7}); 390 let Inst{22} = !if(I4Or{6}, 1, I4{6}); 391 let Inst{21} = !if(I4Or{5}, 1, I4{5}); 392 let Inst{20} = !if(I4Or{4}, 1, I4{4}); 393 let Inst{19} = !if(I4Or{3}, 1, I4{3}); 394 let Inst{18} = !if(I4Or{2}, 1, I4{2}); 395 let Inst{17} = !if(I4Or{1}, 1, I4{1}); 396 let Inst{16} = !if(I4Or{0}, 1, I4{0}); 397 let Inst{15-8} = I5; 398 let Inst{7-0} = op{7-0}; 399} 400 401class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 402 : InstSystemZ<6, outs, ins, asmstr, pattern> { 403 field bits<48> Inst; 404 field bits<48> SoftFail = 0; 405 406 bits<4> R1; 407 bits<4> M3; 408 bits<16> I2; 409 410 let Inst{47-40} = op{15-8}; 411 let Inst{39-36} = R1; 412 let Inst{35-32} = M3; 413 let Inst{31-16} = I2; 414 let Inst{15-8} = 0; 415 let Inst{7-0} = op{7-0}; 416} 417 418class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 419 : InstSystemZ<6, outs, ins, asmstr, pattern> { 420 field bits<48> Inst; 421 field bits<48> SoftFail = 0; 422 423 bits<4> R1; 424 bits<32> I2; 425 426 let Inst{47-40} = op{11-4}; 427 let Inst{39-36} = R1; 428 let Inst{35-32} = op{3-0}; 429 let Inst{31-0} = I2; 430} 431 432class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 433 : InstSystemZ<6, outs, ins, asmstr, pattern> { 434 field bits<48> Inst; 435 field bits<48> SoftFail = 0; 436 437 bits<4> R1; 438 bits<32> RI2; 439 440 let Inst{47-40} = op{11-4}; 441 let Inst{39-36} = R1; 442 let Inst{35-32} = op{3-0}; 443 let Inst{31-0} = RI2; 444} 445 446class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 447 : InstSystemZ<6, outs, ins, asmstr, pattern> { 448 field bits<48> Inst; 449 field bits<48> SoftFail = 0; 450 451 bits<4> M1; 452 bits<32> RI2; 453 454 let Inst{47-40} = op{11-4}; 455 let Inst{39-36} = M1; 456 let Inst{35-32} = op{3-0}; 457 let Inst{31-0} = RI2; 458} 459 460class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 461 : InstSystemZ<6, outs, ins, asmstr, pattern> { 462 field bits<48> Inst; 463 field bits<48> SoftFail = 0; 464 465 bits<4> R1; 466 bits<8> I2; 467 bits<4> M3; 468 bits<4> B4; 469 bits<12> D4; 470 471 let Inst{47-40} = op{15-8}; 472 let Inst{39-36} = R1; 473 let Inst{35-32} = M3; 474 let Inst{31-28} = B4; 475 let Inst{27-16} = D4; 476 let Inst{15-8} = I2; 477 let Inst{7-0} = op{7-0}; 478} 479 480class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 481 : InstSystemZ<2, outs, ins, asmstr, pattern> { 482 field bits<16> Inst; 483 field bits<16> SoftFail = 0; 484 485 bits<4> R1; 486 bits<4> R2; 487 488 let Inst{15-8} = op; 489 let Inst{7-4} = R1; 490 let Inst{3-0} = R2; 491} 492 493class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 494 : InstSystemZ<4, outs, ins, asmstr, pattern> { 495 field bits<32> Inst; 496 field bits<32> SoftFail = 0; 497 498 bits<4> R1; 499 bits<4> R3; 500 bits<4> R2; 501 502 let Inst{31-16} = op; 503 let Inst{15-12} = R1; 504 let Inst{11-8} = 0; 505 let Inst{7-4} = R3; 506 let Inst{3-0} = R2; 507} 508 509class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 510 : InstSystemZ<4, outs, ins, asmstr, pattern> { 511 field bits<32> Inst; 512 field bits<32> SoftFail = 0; 513 514 bits<4> R1; 515 bits<4> R2; 516 517 let Inst{31-16} = op; 518 let Inst{15-8} = 0; 519 let Inst{7-4} = R1; 520 let Inst{3-0} = R2; 521} 522 523class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 524 : InstSystemZ<4, outs, ins, asmstr, pattern> { 525 field bits<32> Inst; 526 field bits<32> SoftFail = 0; 527 528 bits<4> R1; 529 bits<4> R2; 530 bits<4> R3; 531 bits<4> M4; 532 533 let Inst{31-16} = op; 534 let Inst{15-12} = R3; 535 let Inst{11-8} = M4; 536 let Inst{7-4} = R1; 537 let Inst{3-0} = R2; 538} 539 540class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 541 : InstSystemZ<4, outs, ins, asmstr, pattern> { 542 field bits<32> Inst; 543 field bits<32> SoftFail = 0; 544 545 bits<4> R1; 546 bits<4> R2; 547 bits<4> R3; 548 bits<4> M4; 549 550 let Inst{31-16} = op; 551 let Inst{15-12} = R3; 552 let Inst{11-8} = M4; 553 let Inst{7-4} = R1; 554 let Inst{3-0} = R2; 555} 556 557class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 558 : InstSystemZ<4, outs, ins, asmstr, pattern> { 559 field bits<32> Inst; 560 field bits<32> SoftFail = 0; 561 562 bits<4> R1; 563 bits<4> R2; 564 bits<4> M3; 565 566 let Inst{31-16} = op; 567 let Inst{15-12} = M3; 568 let Inst{11-8} = 0; 569 let Inst{7-4} = R1; 570 let Inst{3-0} = R2; 571} 572 573class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 574 : InstSystemZ<4, outs, ins, asmstr, pattern> { 575 field bits<32> Inst; 576 field bits<32> SoftFail = 0; 577 578 bits<4> R1; 579 bits<4> R2; 580 bits<4> M4; 581 582 let Inst{31-16} = op; 583 let Inst{15-12} = 0; 584 let Inst{11-8} = M4; 585 let Inst{7-4} = R1; 586 let Inst{3-0} = R2; 587} 588 589class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 590 : InstSystemZ<4, outs, ins, asmstr, pattern> { 591 field bits<32> Inst; 592 field bits<32> SoftFail = 0; 593 594 bits<4> R1; 595 bits<4> R2; 596 bits<4> M3; 597 bits<4> M4; 598 599 let Inst{31-16} = op; 600 let Inst{15-12} = M3; 601 let Inst{11-8} = M4; 602 let Inst{7-4} = R1; 603 let Inst{3-0} = R2; 604} 605 606class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 607 : InstSystemZ<6, outs, ins, asmstr, pattern> { 608 field bits<48> Inst; 609 field bits<48> SoftFail = 0; 610 611 bits<4> R1; 612 bits<4> R2; 613 bits<4> M3; 614 bits<4> B4; 615 bits<12> D4; 616 617 let Inst{47-40} = op{15-8}; 618 let Inst{39-36} = R1; 619 let Inst{35-32} = R2; 620 let Inst{31-28} = B4; 621 let Inst{27-16} = D4; 622 let Inst{15-12} = M3; 623 let Inst{11-8} = 0; 624 let Inst{7-0} = op{7-0}; 625} 626 627class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 628 : InstSystemZ<4, outs, ins, asmstr, pattern> { 629 field bits<32> Inst; 630 field bits<32> SoftFail = 0; 631 632 bits<4> R1; 633 bits<4> X2; 634 bits<4> B2; 635 bits<12> D2; 636 637 let Inst{31-24} = op; 638 let Inst{23-20} = R1; 639 let Inst{19-16} = X2; 640 let Inst{15-12} = B2; 641 let Inst{11-0} = D2; 642 643 let HasIndex = 1; 644} 645 646class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 647 : InstSystemZ<4, outs, ins, asmstr, pattern> { 648 field bits<32> Inst; 649 field bits<32> SoftFail = 0; 650 651 bits<4> M1; 652 bits<4> X2; 653 bits<4> B2; 654 bits<12> D2; 655 656 let Inst{31-24} = op; 657 let Inst{23-20} = M1; 658 let Inst{19-16} = X2; 659 let Inst{15-12} = B2; 660 let Inst{11-0} = D2; 661 662 let HasIndex = 1; 663} 664 665class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 666 : InstSystemZ<6, outs, ins, asmstr, pattern> { 667 field bits<48> Inst; 668 field bits<48> SoftFail = 0; 669 670 bits<4> R1; 671 bits<4> X2; 672 bits<4> B2; 673 bits<12> D2; 674 bits<4> M3; 675 676 let Inst{47-40} = op{15-8}; 677 let Inst{39-36} = R1; 678 let Inst{35-32} = X2; 679 let Inst{31-28} = B2; 680 let Inst{27-16} = D2; 681 let Inst{15-12} = M3; 682 let Inst{11-8} = 0; 683 let Inst{7-0} = op{7-0}; 684 685 let HasIndex = 1; 686} 687 688class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 689 : InstSystemZ<6, outs, ins, asmstr, pattern> { 690 field bits<48> Inst; 691 field bits<48> SoftFail = 0; 692 693 bits<4> R1; 694 bits<4> R3; 695 bits<4> X2; 696 bits<4> B2; 697 bits<12> D2; 698 699 let Inst{47-40} = op{15-8}; 700 let Inst{39-36} = R3; 701 let Inst{35-32} = X2; 702 let Inst{31-28} = B2; 703 let Inst{27-16} = D2; 704 let Inst{15-12} = R1; 705 let Inst{11-8} = 0; 706 let Inst{7-0} = op{7-0}; 707 708 let HasIndex = 1; 709} 710 711class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 712 : InstSystemZ<6, outs, ins, asmstr, pattern> { 713 field bits<48> Inst; 714 field bits<48> SoftFail = 0; 715 716 bits<4> R1; 717 bits<4> X2; 718 bits<4> B2; 719 bits<20> D2; 720 721 let Inst{47-40} = op{15-8}; 722 let Inst{39-36} = R1; 723 let Inst{35-32} = X2; 724 let Inst{31-28} = B2; 725 let Inst{27-16} = D2{11-0}; 726 let Inst{15-8} = D2{19-12}; 727 let Inst{7-0} = op{7-0}; 728 729 let Has20BitOffset = 1; 730 let HasIndex = 1; 731} 732 733class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 734 : InstSystemZ<6, outs, ins, asmstr, pattern> { 735 field bits<48> Inst; 736 field bits<48> SoftFail = 0; 737 738 bits<4> M1; 739 bits<4> X2; 740 bits<4> B2; 741 bits<20> D2; 742 743 let Inst{47-40} = op{15-8}; 744 let Inst{39-36} = M1; 745 let Inst{35-32} = X2; 746 let Inst{31-28} = B2; 747 let Inst{27-16} = D2{11-0}; 748 let Inst{15-8} = D2{19-12}; 749 let Inst{7-0} = op{7-0}; 750 751 let Has20BitOffset = 1; 752 let HasIndex = 1; 753} 754 755class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 756 : InstSystemZ<4, outs, ins, asmstr, pattern> { 757 field bits<32> Inst; 758 field bits<32> SoftFail = 0; 759 760 bits<4> R1; 761 bits<4> R3; 762 bits<4> B2; 763 bits<12> D2; 764 765 let Inst{31-24} = op; 766 let Inst{23-20} = R1; 767 let Inst{19-16} = R3; 768 let Inst{15-12} = B2; 769 let Inst{11-0} = D2; 770} 771 772class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 773 : InstSystemZ<4, outs, ins, asmstr, pattern> { 774 field bits<32> Inst; 775 field bits<32> SoftFail = 0; 776 777 bits<4> R1; 778 bits<4> M3; 779 bits<4> B2; 780 bits<12> D2; 781 782 let Inst{31-24} = op; 783 let Inst{23-20} = R1; 784 let Inst{19-16} = M3; 785 let Inst{15-12} = B2; 786 let Inst{11-0} = D2; 787} 788 789class InstRSEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 790 : InstSystemZ<6, outs, ins, asmstr, pattern> { 791 field bits<48> Inst; 792 field bits<48> SoftFail = 0; 793 794 bits<4> R1; 795 bits<4> R3; 796 bits<4> B2; 797 bits<12> D2; 798 799 let Inst{47-40} = op{15-8}; 800 let Inst{39-36} = R1; 801 let Inst{35-32} = R3; 802 let Inst{31-28} = B2; 803 let Inst{27-16} = D2; 804 let Inst{15-8} = 0; 805 let Inst{7-0} = op{7-0}; 806} 807 808class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 809 : InstSystemZ<4, outs, ins, asmstr, pattern> { 810 field bits<32> Inst; 811 field bits<32> SoftFail = 0; 812 813 bits<4> R1; 814 bits<4> R3; 815 bits<16> RI2; 816 817 let Inst{31-24} = op; 818 let Inst{23-20} = R1; 819 let Inst{19-16} = R3; 820 let Inst{15-0} = RI2; 821} 822 823class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 824 : InstSystemZ<6, outs, ins, asmstr, pattern> { 825 field bits<48> Inst; 826 field bits<48> SoftFail = 0; 827 828 bits<4> B1; 829 bits<12> D1; 830 bits<4> L1; 831 832 let Inst{47-40} = op{15-8}; 833 let Inst{39-36} = L1; 834 let Inst{35-32} = 0; 835 let Inst{31-28} = B1; 836 let Inst{27-16} = D1; 837 let Inst{15-8} = 0; 838 let Inst{7-0} = op{7-0}; 839} 840 841class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 842 : InstSystemZ<6, outs, ins, asmstr, pattern> { 843 field bits<48> Inst; 844 field bits<48> SoftFail = 0; 845 846 bits<4> R1; 847 bits<4> B2; 848 bits<12> D2; 849 bits<8> L2; 850 bits<4> M3; 851 852 let Inst{47-40} = op{15-8}; 853 let Inst{39-32} = L2; 854 let Inst{31-28} = B2; 855 let Inst{27-16} = D2; 856 let Inst{15-12} = R1; 857 let Inst{11-8} = M3; 858 let Inst{7-0} = op{7-0}; 859} 860 861class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 862 : InstSystemZ<6, outs, ins, asmstr, pattern> { 863 field bits<48> Inst; 864 field bits<48> SoftFail = 0; 865 866 bits<4> R1; 867 bits<4> R3; 868 bits<4> B2; 869 bits<20> D2; 870 871 let Inst{47-40} = op{15-8}; 872 let Inst{39-36} = R1; 873 let Inst{35-32} = R3; 874 let Inst{31-28} = B2; 875 let Inst{27-16} = D2{11-0}; 876 let Inst{15-8} = D2{19-12}; 877 let Inst{7-0} = op{7-0}; 878 879 let Has20BitOffset = 1; 880} 881 882class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 883 : InstSystemZ<6, outs, ins, asmstr, pattern> { 884 field bits<48> Inst; 885 field bits<48> SoftFail = 0; 886 887 bits<4> R1; 888 bits<4> M3; 889 bits<4> B2; 890 bits<20> D2; 891 892 let Inst{47-40} = op{15-8}; 893 let Inst{39-36} = R1; 894 let Inst{35-32} = M3; 895 let Inst{31-28} = B2; 896 let Inst{27-16} = D2{11-0}; 897 let Inst{15-8} = D2{19-12}; 898 let Inst{7-0} = op{7-0}; 899 900 let Has20BitOffset = 1; 901} 902 903class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 904 : InstSystemZ<4, outs, ins, asmstr, pattern> { 905 field bits<32> Inst; 906 field bits<32> SoftFail = 0; 907 908 bits<4> B1; 909 bits<12> D1; 910 bits<8> I2; 911 912 let Inst{31-24} = op; 913 let Inst{23-16} = I2; 914 let Inst{15-12} = B1; 915 let Inst{11-0} = D1; 916} 917 918class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 919 : InstSystemZ<6, outs, ins, asmstr, pattern> { 920 field bits<48> Inst; 921 field bits<48> SoftFail = 0; 922 923 bits<4> B1; 924 bits<12> D1; 925 bits<16> I2; 926 927 let Inst{47-32} = op; 928 let Inst{31-28} = B1; 929 let Inst{27-16} = D1; 930 let Inst{15-0} = I2; 931} 932 933class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 934 : InstSystemZ<6, outs, ins, asmstr, pattern> { 935 field bits<48> Inst; 936 field bits<48> SoftFail = 0; 937 938 bits<4> B1; 939 bits<20> D1; 940 bits<8> I2; 941 942 let Inst{47-40} = op{15-8}; 943 let Inst{39-32} = I2; 944 let Inst{31-28} = B1; 945 let Inst{27-16} = D1{11-0}; 946 let Inst{15-8} = D1{19-12}; 947 let Inst{7-0} = op{7-0}; 948 949 let Has20BitOffset = 1; 950} 951 952class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 953 : InstSystemZ<6, outs, ins, asmstr, pattern> { 954 field bits<48> Inst; 955 field bits<48> SoftFail = 0; 956 957 bits<4> M1; 958 bits<16> RI2; 959 bits<4> B3; 960 bits<12> D3; 961 962 let Inst{47-40} = op; 963 let Inst{39-36} = M1; 964 let Inst{35-32} = 0; 965 let Inst{31-28} = B3; 966 let Inst{27-16} = D3; 967 let Inst{15-0} = RI2; 968} 969 970class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 971 : InstSystemZ<6, outs, ins, asmstr, pattern> { 972 field bits<48> Inst; 973 field bits<48> SoftFail = 0; 974 975 bits<4> B1; 976 bits<12> D1; 977 bits<8> L1; 978 bits<4> B2; 979 bits<12> D2; 980 981 let Inst{47-40} = op; 982 let Inst{39-32} = L1; 983 let Inst{31-28} = B1; 984 let Inst{27-16} = D1; 985 let Inst{15-12} = B2; 986 let Inst{11-0} = D2; 987} 988 989class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 990 : InstSystemZ<6, outs, ins, asmstr, pattern> { 991 field bits<48> Inst; 992 field bits<48> SoftFail = 0; 993 994 bits<4> B1; 995 bits<12> D1; 996 bits<4> L1; 997 bits<4> B2; 998 bits<12> D2; 999 bits<4> L2; 1000 1001 let Inst{47-40} = op; 1002 let Inst{39-36} = L1; 1003 let Inst{35-32} = L2; 1004 let Inst{31-28} = B1; 1005 let Inst{27-16} = D1; 1006 let Inst{15-12} = B2; 1007 let Inst{11-0} = D2; 1008} 1009 1010class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1011 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1012 field bits<48> Inst; 1013 field bits<48> SoftFail = 0; 1014 1015 bits<4> B1; 1016 bits<12> D1; 1017 bits<4> L1; 1018 bits<4> B2; 1019 bits<12> D2; 1020 bits<4> I3; 1021 1022 let Inst{47-40} = op; 1023 let Inst{39-36} = L1; 1024 let Inst{35-32} = I3; 1025 let Inst{31-28} = B1; 1026 let Inst{27-16} = D1; 1027 let Inst{15-12} = B2; 1028 let Inst{11-0} = D2; 1029} 1030 1031class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1032 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1033 field bits<48> Inst; 1034 field bits<48> SoftFail = 0; 1035 1036 bits<4> R1; 1037 bits<4> B1; 1038 bits<12> D1; 1039 bits<4> B2; 1040 bits<12> D2; 1041 bits<4> R3; 1042 1043 let Inst{47-40} = op; 1044 let Inst{39-36} = R1; 1045 let Inst{35-32} = R3; 1046 let Inst{31-28} = B1; 1047 let Inst{27-16} = D1; 1048 let Inst{15-12} = B2; 1049 let Inst{11-0} = D2; 1050} 1051 1052class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1053 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1054 field bits<48> Inst; 1055 field bits<48> SoftFail = 0; 1056 1057 bits<4> R1; 1058 bits<4> B2; 1059 bits<12> D2; 1060 bits<4> R3; 1061 bits<4> B4; 1062 bits<12> D4; 1063 1064 let Inst{47-40} = op; 1065 let Inst{39-36} = R1; 1066 let Inst{35-32} = R3; 1067 let Inst{31-28} = B2; 1068 let Inst{27-16} = D2; 1069 let Inst{15-12} = B4; 1070 let Inst{11-0} = D4; 1071} 1072 1073class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1074 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1075 field bits<48> Inst; 1076 field bits<48> SoftFail = 0; 1077 1078 bits<4> B1; 1079 bits<12> D1; 1080 bits<4> B2; 1081 bits<12> D2; 1082 bits<8> L2; 1083 1084 let Inst{47-40} = op; 1085 let Inst{39-32} = L2; 1086 let Inst{31-28} = B1; 1087 let Inst{27-16} = D1; 1088 let Inst{15-12} = B2; 1089 let Inst{11-0} = D2; 1090} 1091 1092class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1093 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1094 field bits<48> Inst; 1095 field bits<48> SoftFail = 0; 1096 1097 bits<4> B1; 1098 bits<12> D1; 1099 bits<4> B2; 1100 bits<12> D2; 1101 1102 let Inst{47-32} = op; 1103 let Inst{31-28} = B1; 1104 let Inst{27-16} = D1; 1105 let Inst{15-12} = B2; 1106 let Inst{11-0} = D2; 1107} 1108 1109class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1110 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1111 field bits<48> Inst; 1112 field bits<48> SoftFail = 0; 1113 1114 bits<4> B1; 1115 bits<12> D1; 1116 bits<4> B2; 1117 bits<12> D2; 1118 bits<4> R3; 1119 1120 let Inst{47-40} = op{11-4}; 1121 let Inst{39-36} = R3; 1122 let Inst{35-32} = op{3-0}; 1123 let Inst{31-28} = B1; 1124 let Inst{27-16} = D1; 1125 let Inst{15-12} = B2; 1126 let Inst{11-0} = D2; 1127} 1128 1129class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1130 : InstSystemZ<4, outs, ins, asmstr, pattern> { 1131 field bits<32> Inst; 1132 field bits<32> SoftFail = 0; 1133 1134 bits<4> B2; 1135 bits<12> D2; 1136 1137 let Inst{31-16} = op; 1138 let Inst{15-12} = B2; 1139 let Inst{11-0} = D2; 1140} 1141 1142class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1143 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1144 field bits<48> Inst; 1145 field bits<48> SoftFail = 0; 1146 1147 bits<5> V1; 1148 bits<16> I2; 1149 bits<4> M3; 1150 1151 let Inst{47-40} = op{15-8}; 1152 let Inst{39-36} = V1{3-0}; 1153 let Inst{35-32} = 0; 1154 let Inst{31-16} = I2; 1155 let Inst{15-12} = M3; 1156 let Inst{11} = V1{4}; 1157 let Inst{10-8} = 0; 1158 let Inst{7-0} = op{7-0}; 1159} 1160 1161class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1162 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1163 field bits<48> Inst; 1164 field bits<48> SoftFail = 0; 1165 1166 bits<5> V1; 1167 bits<8> I2; 1168 bits<8> I3; 1169 bits<4> M4; 1170 1171 let Inst{47-40} = op{15-8}; 1172 let Inst{39-36} = V1{3-0}; 1173 let Inst{35-32} = 0; 1174 let Inst{31-24} = I2; 1175 let Inst{23-16} = I3; 1176 let Inst{15-12} = M4; 1177 let Inst{11} = V1{4}; 1178 let Inst{10-8} = 0; 1179 let Inst{7-0} = op{7-0}; 1180} 1181 1182class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1183 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1184 field bits<48> Inst; 1185 field bits<48> SoftFail = 0; 1186 1187 bits<5> V1; 1188 bits<5> V3; 1189 bits<16> I2; 1190 bits<4> M4; 1191 1192 let Inst{47-40} = op{15-8}; 1193 let Inst{39-36} = V1{3-0}; 1194 let Inst{35-32} = V3{3-0}; 1195 let Inst{31-16} = I2; 1196 let Inst{15-12} = M4; 1197 let Inst{11} = V1{4}; 1198 let Inst{10} = V3{4}; 1199 let Inst{9-8} = 0; 1200 let Inst{7-0} = op{7-0}; 1201} 1202 1203class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1204 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1205 field bits<48> Inst; 1206 field bits<48> SoftFail = 0; 1207 1208 bits<5> V1; 1209 bits<5> V2; 1210 bits<5> V3; 1211 bits<8> I4; 1212 bits<4> M5; 1213 1214 let Inst{47-40} = op{15-8}; 1215 let Inst{39-36} = V1{3-0}; 1216 let Inst{35-32} = V2{3-0}; 1217 let Inst{31-28} = V3{3-0}; 1218 let Inst{27-24} = 0; 1219 let Inst{23-16} = I4; 1220 let Inst{15-12} = M5; 1221 let Inst{11} = V1{4}; 1222 let Inst{10} = V2{4}; 1223 let Inst{9} = V3{4}; 1224 let Inst{8} = 0; 1225 let Inst{7-0} = op{7-0}; 1226} 1227 1228class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1229 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1230 field bits<48> Inst; 1231 field bits<48> SoftFail = 0; 1232 1233 bits<5> V1; 1234 bits<5> V2; 1235 bits<12> I3; 1236 bits<4> M4; 1237 bits<4> M5; 1238 1239 let Inst{47-40} = op{15-8}; 1240 let Inst{39-36} = V1{3-0}; 1241 let Inst{35-32} = V2{3-0}; 1242 let Inst{31-20} = I3; 1243 let Inst{19-16} = M5; 1244 let Inst{15-12} = M4; 1245 let Inst{11} = V1{4}; 1246 let Inst{10} = V2{4}; 1247 let Inst{9-8} = 0; 1248 let Inst{7-0} = op{7-0}; 1249} 1250 1251class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1252 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1253 field bits<48> Inst; 1254 field bits<48> SoftFail = 0; 1255 1256 bits<5> V1; 1257 bits<5> V2; 1258 bits<5> V3; 1259 bits<8> I4; 1260 bits<4> M5; 1261 1262 let Inst{47-40} = op{15-8}; 1263 let Inst{39-36} = V1{3-0}; 1264 let Inst{35-32} = V2{3-0}; 1265 let Inst{31-28} = V3{3-0}; 1266 let Inst{27-24} = 0; 1267 let Inst{23-20} = M5; 1268 let Inst{19-12} = I4; 1269 let Inst{11} = V1{4}; 1270 let Inst{10} = V2{4}; 1271 let Inst{9} = V3{4}; 1272 let Inst{8} = 0; 1273 let Inst{7-0} = op{7-0}; 1274} 1275 1276class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1277 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1278 field bits<48> Inst; 1279 field bits<48> SoftFail = 0; 1280 1281 bits<5> V1; 1282 bits<5> V2; 1283 bits<8> I3; 1284 bits<8> I4; 1285 bits<4> M5; 1286 1287 let Inst{47-40} = op{15-8}; 1288 let Inst{39-36} = V1{3-0}; 1289 let Inst{35-32} = V2{3-0}; 1290 let Inst{31-24} = I4; 1291 let Inst{23-20} = M5; 1292 let Inst{19-12} = I3; 1293 let Inst{11} = V1{4}; 1294 let Inst{10} = V2{4}; 1295 let Inst{9-8} = 0; 1296 let Inst{7-0} = op{7-0}; 1297} 1298 1299class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1300 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1301 field bits<48> Inst; 1302 field bits<48> SoftFail = 0; 1303 1304 bits<5> V1; 1305 bits<16> I2; 1306 bits<4> I3; 1307 1308 let Inst{47-40} = op{15-8}; 1309 let Inst{39-36} = V1{3-0}; 1310 let Inst{35-32} = 0; 1311 let Inst{31-16} = I2; 1312 let Inst{15-12} = I3; 1313 let Inst{11} = V1{4}; 1314 let Inst{10-8} = 0; 1315 let Inst{7-0} = op{7-0}; 1316} 1317 1318class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1319 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1320 field bits<48> Inst; 1321 field bits<48> SoftFail = 0; 1322 1323 bits<5> V1; 1324 bits<4> R2; 1325 bits<8> I3; 1326 bits<4> M4; 1327 1328 let Inst{47-40} = op{15-8}; 1329 let Inst{39-36} = V1{3-0}; 1330 let Inst{35-32} = R2; 1331 let Inst{31-24} = 0; 1332 let Inst{23-20} = M4; 1333 let Inst{19-12} = I3; 1334 let Inst{11} = V1{4}; 1335 let Inst{10-8} = 0; 1336 let Inst{7-0} = op{7-0}; 1337} 1338 1339// Depending on the instruction mnemonic, certain bits may be or-ed into 1340// the M4 value provided as explicit operand. These are passed as m4or. 1341class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1342 bits<4> m4or = 0> 1343 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1344 field bits<48> Inst; 1345 field bits<48> SoftFail = 0; 1346 1347 bits<5> V1; 1348 bits<5> V2; 1349 bits<4> M3; 1350 bits<4> M4; 1351 bits<4> M5; 1352 1353 let Inst{47-40} = op{15-8}; 1354 let Inst{39-36} = V1{3-0}; 1355 let Inst{35-32} = V2{3-0}; 1356 let Inst{31-24} = 0; 1357 let Inst{23-20} = M5; 1358 let Inst{19} = !if (!eq (m4or{3}, 1), 1, M4{3}); 1359 let Inst{18} = !if (!eq (m4or{2}, 1), 1, M4{2}); 1360 let Inst{17} = !if (!eq (m4or{1}, 1), 1, M4{1}); 1361 let Inst{16} = !if (!eq (m4or{0}, 1), 1, M4{0}); 1362 let Inst{15-12} = M3; 1363 let Inst{11} = V1{4}; 1364 let Inst{10} = V2{4}; 1365 let Inst{9-8} = 0; 1366 let Inst{7-0} = op{7-0}; 1367} 1368 1369// Depending on the instruction mnemonic, certain bits may be or-ed into 1370// the M5 value provided as explicit operand. These are passed as m5or. 1371class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1372 bits<4> m5or = 0> 1373 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1374 field bits<48> Inst; 1375 field bits<48> SoftFail = 0; 1376 1377 bits<5> V1; 1378 bits<5> V2; 1379 bits<5> V3; 1380 bits<4> M4; 1381 bits<4> M5; 1382 1383 let Inst{47-40} = op{15-8}; 1384 let Inst{39-36} = V1{3-0}; 1385 let Inst{35-32} = V2{3-0}; 1386 let Inst{31-28} = V3{3-0}; 1387 let Inst{27-24} = 0; 1388 let Inst{23} = !if (!eq (m5or{3}, 1), 1, M5{3}); 1389 let Inst{22} = !if (!eq (m5or{2}, 1), 1, M5{2}); 1390 let Inst{21} = !if (!eq (m5or{1}, 1), 1, M5{1}); 1391 let Inst{20} = !if (!eq (m5or{0}, 1), 1, M5{0}); 1392 let Inst{19-16} = 0; 1393 let Inst{15-12} = M4; 1394 let Inst{11} = V1{4}; 1395 let Inst{10} = V2{4}; 1396 let Inst{9} = V3{4}; 1397 let Inst{8} = 0; 1398 let Inst{7-0} = op{7-0}; 1399} 1400 1401class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1402 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1403 field bits<48> Inst; 1404 field bits<48> SoftFail = 0; 1405 1406 bits<5> V1; 1407 bits<5> V2; 1408 bits<5> V3; 1409 bits<4> M4; 1410 bits<4> M5; 1411 bits<4> M6; 1412 1413 let Inst{47-40} = op{15-8}; 1414 let Inst{39-36} = V1{3-0}; 1415 let Inst{35-32} = V2{3-0}; 1416 let Inst{31-28} = V3{3-0}; 1417 let Inst{27-24} = 0; 1418 let Inst{23-20} = M6; 1419 let Inst{19-16} = M5; 1420 let Inst{15-12} = M4; 1421 let Inst{11} = V1{4}; 1422 let Inst{10} = V2{4}; 1423 let Inst{9} = V3{4}; 1424 let Inst{8} = 0; 1425 let Inst{7-0} = op{7-0}; 1426} 1427 1428// Depending on the instruction mnemonic, certain bits may be or-ed into 1429// the M6 value provided as explicit operand. These are passed as m6or. 1430class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern, 1431 bits<4> m6or = 0> 1432 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1433 field bits<48> Inst; 1434 field bits<48> SoftFail = 0; 1435 1436 bits<5> V1; 1437 bits<5> V2; 1438 bits<5> V3; 1439 bits<5> V4; 1440 bits<4> M5; 1441 bits<4> M6; 1442 1443 let Inst{47-40} = op{15-8}; 1444 let Inst{39-36} = V1{3-0}; 1445 let Inst{35-32} = V2{3-0}; 1446 let Inst{31-28} = V3{3-0}; 1447 let Inst{27-24} = M5; 1448 let Inst{23} = !if (!eq (m6or{3}, 1), 1, M6{3}); 1449 let Inst{22} = !if (!eq (m6or{2}, 1), 1, M6{2}); 1450 let Inst{21} = !if (!eq (m6or{1}, 1), 1, M6{1}); 1451 let Inst{20} = !if (!eq (m6or{0}, 1), 1, M6{0}); 1452 let Inst{19-16} = 0; 1453 let Inst{15-12} = V4{3-0}; 1454 let Inst{11} = V1{4}; 1455 let Inst{10} = V2{4}; 1456 let Inst{9} = V3{4}; 1457 let Inst{8} = V4{4}; 1458 let Inst{7-0} = op{7-0}; 1459} 1460 1461class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1462 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1463 field bits<48> Inst; 1464 field bits<48> SoftFail = 0; 1465 1466 bits<5> V1; 1467 bits<5> V2; 1468 bits<5> V3; 1469 bits<5> V4; 1470 bits<4> M5; 1471 bits<4> M6; 1472 1473 let Inst{47-40} = op{15-8}; 1474 let Inst{39-36} = V1{3-0}; 1475 let Inst{35-32} = V2{3-0}; 1476 let Inst{31-28} = V3{3-0}; 1477 let Inst{27-24} = M6; 1478 let Inst{23-20} = 0; 1479 let Inst{19-16} = M5; 1480 let Inst{15-12} = V4{3-0}; 1481 let Inst{11} = V1{4}; 1482 let Inst{10} = V2{4}; 1483 let Inst{9} = V3{4}; 1484 let Inst{8} = V4{4}; 1485 let Inst{7-0} = op{7-0}; 1486} 1487 1488class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1489 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1490 field bits<48> Inst; 1491 field bits<48> SoftFail = 0; 1492 1493 bits<5> V1; 1494 bits<4> R2; 1495 bits<4> R3; 1496 1497 let Inst{47-40} = op{15-8}; 1498 let Inst{39-36} = V1{3-0}; 1499 let Inst{35-32} = R2; 1500 let Inst{31-28} = R3; 1501 let Inst{27-12} = 0; 1502 let Inst{11} = V1{4}; 1503 let Inst{10-8} = 0; 1504 let Inst{7-0} = op{7-0}; 1505} 1506 1507class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1508 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1509 field bits<48> Inst; 1510 field bits<48> SoftFail = 0; 1511 1512 bits<5> V1; 1513 1514 let Inst{47-40} = op{15-8}; 1515 let Inst{39-36} = 0; 1516 let Inst{35-32} = V1{3-0}; 1517 let Inst{31-12} = 0; 1518 let Inst{11} = 0; 1519 let Inst{10} = V1{4}; 1520 let Inst{9-8} = 0; 1521 let Inst{7-0} = op{7-0}; 1522} 1523 1524class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1525 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1526 field bits<48> Inst; 1527 field bits<48> SoftFail = 0; 1528 1529 bits<5> V1; 1530 bits<5> V2; 1531 bits<4> M3; 1532 1533 let Inst{47-40} = op{15-8}; 1534 let Inst{39-36} = 0; 1535 let Inst{35-32} = V1{3-0}; 1536 let Inst{31-28} = V2{3-0}; 1537 let Inst{27-24} = 0; 1538 let Inst{23-20} = M3; 1539 let Inst{19-12} = 0; 1540 let Inst{11} = 0; 1541 let Inst{10} = V1{4}; 1542 let Inst{9} = V2{4}; 1543 let Inst{8} = 0; 1544 let Inst{7-0} = op{7-0}; 1545} 1546 1547class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1548 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1549 field bits<48> Inst; 1550 field bits<48> SoftFail = 0; 1551 1552 bits<4> R1; 1553 bits<5> V2; 1554 bits<4> M3; 1555 bits<4> M4; 1556 1557 let Inst{47-40} = op{15-8}; 1558 let Inst{39-36} = R1; 1559 let Inst{35-32} = V2{3-0}; 1560 let Inst{31-24} = 0; 1561 let Inst{23-20} = M3; 1562 let Inst{19-16} = M4; 1563 let Inst{15-12} = 0; 1564 let Inst{11} = 0; 1565 let Inst{10} = V2{4}; 1566 let Inst{9-8} = 0; 1567 let Inst{7-0} = op{7-0}; 1568} 1569 1570class InstVRRj<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1571 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1572 field bits<48> Inst; 1573 field bits<48> SoftFail = 0; 1574 1575 bits<5> V1; 1576 bits<5> V2; 1577 bits<5> V3; 1578 bits<4> M4; 1579 1580 let Inst{47-40} = op{15-8}; 1581 let Inst{39-36} = V1{3-0}; 1582 let Inst{35-32} = V2{3-0}; 1583 let Inst{31-28} = V3{3-0}; 1584 let Inst{27-24} = 0; 1585 let Inst{23-20} = M4; 1586 let Inst{19-16} = 0; 1587 let Inst{15-12} = 0; 1588 let Inst{11} = V1{4}; 1589 let Inst{10} = V2{4}; 1590 let Inst{9} = V3{4}; 1591 let Inst{8} = 0; 1592 let Inst{7-0} = op{7-0}; 1593} 1594 1595class InstVRRk<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1596 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1597 field bits<48> Inst; 1598 field bits<48> SoftFail = 0; 1599 1600 bits<5> V1; 1601 bits<5> V2; 1602 bits<4> M3; 1603 1604 let Inst{47-40} = op{15-8}; 1605 let Inst{39-36} = V1{3-0}; 1606 let Inst{35-32} = V2{3-0}; 1607 let Inst{31-28} = 0; 1608 let Inst{27-24} = 0; 1609 let Inst{23-20} = M3; 1610 let Inst{19-16} = 0; 1611 let Inst{15-12} = 0; 1612 let Inst{11} = V1{4}; 1613 let Inst{10} = V2{4}; 1614 let Inst{9} = 0; 1615 let Inst{8} = 0; 1616 let Inst{7-0} = op{7-0}; 1617} 1618 1619class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1620 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1621 field bits<48> Inst; 1622 field bits<48> SoftFail = 0; 1623 1624 bits<5> V1; 1625 bits<4> B2; 1626 bits<12> D2; 1627 bits<5> V3; 1628 bits<4> M4; 1629 1630 let Inst{47-40} = op{15-8}; 1631 let Inst{39-36} = V1{3-0}; 1632 let Inst{35-32} = V3{3-0}; 1633 let Inst{31-28} = B2; 1634 let Inst{27-16} = D2; 1635 let Inst{15-12} = M4; 1636 let Inst{11} = V1{4}; 1637 let Inst{10} = V3{4}; 1638 let Inst{9-8} = 0; 1639 let Inst{7-0} = op{7-0}; 1640} 1641 1642class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1643 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1644 field bits<48> Inst; 1645 field bits<48> SoftFail = 0; 1646 1647 bits<5> V1; 1648 bits<4> B2; 1649 bits<12> D2; 1650 bits<4> R3; 1651 bits<4> M4; 1652 1653 let Inst{47-40} = op{15-8}; 1654 let Inst{39-36} = V1{3-0}; 1655 let Inst{35-32} = R3; 1656 let Inst{31-28} = B2; 1657 let Inst{27-16} = D2; 1658 let Inst{15-12} = M4; 1659 let Inst{11} = V1{4}; 1660 let Inst{10-8} = 0; 1661 let Inst{7-0} = op{7-0}; 1662} 1663 1664class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1665 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1666 field bits<48> Inst; 1667 field bits<48> SoftFail = 0; 1668 1669 bits<4> R1; 1670 bits<4> B2; 1671 bits<12> D2; 1672 bits<5> V3; 1673 bits<4> M4; 1674 1675 let Inst{47-40} = op{15-8}; 1676 let Inst{39-36} = R1; 1677 let Inst{35-32} = V3{3-0}; 1678 let Inst{31-28} = B2; 1679 let Inst{27-16} = D2; 1680 let Inst{15-12} = M4; 1681 let Inst{11} = 0; 1682 let Inst{10} = V3{4}; 1683 let Inst{9-8} = 0; 1684 let Inst{7-0} = op{7-0}; 1685} 1686 1687class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1688 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1689 field bits<48> Inst; 1690 field bits<48> SoftFail = 0; 1691 1692 bits<5> V1; 1693 bits<4> B2; 1694 bits<12> D2; 1695 bits<4> R3; 1696 1697 let Inst{47-40} = op{15-8}; 1698 let Inst{39-36} = 0; 1699 let Inst{35-32} = R3; 1700 let Inst{31-28} = B2; 1701 let Inst{27-16} = D2; 1702 let Inst{15-12} = V1{3-0}; 1703 let Inst{11-9} = 0; 1704 let Inst{8} = V1{4}; 1705 let Inst{7-0} = op{7-0}; 1706} 1707 1708class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1709 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1710 field bits<48> Inst; 1711 field bits<48> SoftFail = 0; 1712 1713 bits<5> V1; 1714 bits<5> V2; 1715 bits<4> B2; 1716 bits<12> D2; 1717 bits<4> M3; 1718 1719 let Inst{47-40} = op{15-8}; 1720 let Inst{39-36} = V1{3-0}; 1721 let Inst{35-32} = V2{3-0}; 1722 let Inst{31-28} = B2; 1723 let Inst{27-16} = D2; 1724 let Inst{15-12} = M3; 1725 let Inst{11} = V1{4}; 1726 let Inst{10} = V2{4}; 1727 let Inst{9-8} = 0; 1728 let Inst{7-0} = op{7-0}; 1729} 1730 1731class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1732 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1733 field bits<48> Inst; 1734 field bits<48> SoftFail = 0; 1735 1736 bits<5> V1; 1737 bits<4> X2; 1738 bits<4> B2; 1739 bits<12> D2; 1740 bits<4> M3; 1741 1742 let Inst{47-40} = op{15-8}; 1743 let Inst{39-36} = V1{3-0}; 1744 let Inst{35-32} = X2; 1745 let Inst{31-28} = B2; 1746 let Inst{27-16} = D2; 1747 let Inst{15-12} = M3; 1748 let Inst{11} = V1{4}; 1749 let Inst{10-8} = 0; 1750 let Inst{7-0} = op{7-0}; 1751} 1752 1753class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern> 1754 : InstSystemZ<6, outs, ins, asmstr, pattern> { 1755 field bits<48> Inst; 1756 field bits<48> SoftFail = 0; 1757 1758 bits<5> V1; 1759 bits<4> B2; 1760 bits<12> D2; 1761 bits<8> I3; 1762 1763 let Inst{47-40} = op{15-8}; 1764 let Inst{39-32} = I3; 1765 let Inst{31-28} = B2; 1766 let Inst{27-16} = D2; 1767 let Inst{15-12} = V1{3-0}; 1768 let Inst{11-9} = 0; 1769 let Inst{8} = V1{4}; 1770 let Inst{7-0} = op{7-0}; 1771} 1772 1773//===----------------------------------------------------------------------===// 1774// Instruction classes for .insn directives 1775//===----------------------------------------------------------------------===// 1776 1777class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern> 1778 : InstE<0, outs, ins, asmstr, pattern> { 1779 bits<16> enc; 1780 1781 let Inst = enc; 1782} 1783 1784class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern> 1785 : InstRIa<0, outs, ins, asmstr, pattern> { 1786 bits<32> enc; 1787 1788 let Inst{31-24} = enc{31-24}; 1789 let Inst{19-16} = enc{19-16}; 1790} 1791 1792class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern> 1793 : InstRIEd<0, outs, ins, asmstr, pattern> { 1794 bits<48> enc; 1795 1796 let Inst{47-40} = enc{47-40}; 1797 let Inst{7-0} = enc{7-0}; 1798} 1799 1800class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern> 1801 : InstRILa<0, outs, ins, asmstr, pattern> { 1802 bits<48> enc; 1803 string type; 1804 1805 let Inst{47-40} = enc{47-40}; 1806 let Inst{35-32} = enc{35-32}; 1807} 1808 1809class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern> 1810 : InstRIS<0, outs, ins, asmstr, pattern> { 1811 bits<48> enc; 1812 1813 let Inst{47-40} = enc{47-40}; 1814 let Inst{7-0} = enc{7-0}; 1815} 1816 1817class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern> 1818 : InstRR<0, outs, ins, asmstr, pattern> { 1819 bits<16> enc; 1820 1821 let Inst{15-8} = enc{15-8}; 1822} 1823 1824class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern> 1825 : InstRRE<0, outs, ins, asmstr, pattern> { 1826 bits<32> enc; 1827 1828 let Inst{31-16} = enc{31-16}; 1829} 1830 1831class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern> 1832 : InstRRFa<0, outs, ins, asmstr, pattern> { 1833 bits<32> enc; 1834 1835 let Inst{31-16} = enc{31-16}; 1836} 1837 1838class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern> 1839 : InstRRS<0, outs, ins, asmstr, pattern> { 1840 bits<48> enc; 1841 1842 let Inst{47-40} = enc{47-40}; 1843 let Inst{7-0} = enc{7-0}; 1844} 1845 1846class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern> 1847 : InstRSa<0, outs, ins, asmstr, pattern> { 1848 bits<32> enc; 1849 1850 let Inst{31-24} = enc{31-24}; 1851} 1852 1853class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern> 1854 : InstRSEa<6, outs, ins, asmstr, pattern> { 1855 bits <48> enc; 1856 1857 let Inst{47-40} = enc{47-40}; 1858 let Inst{7-0} = enc{7-0}; 1859} 1860 1861class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern> 1862 : InstRSI<0, outs, ins, asmstr, pattern> { 1863 bits<32> enc; 1864 1865 let Inst{31-24} = enc{31-24}; 1866} 1867 1868class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern> 1869 : InstRSYa<0, outs, ins, asmstr, pattern> { 1870 bits<48> enc; 1871 1872 let Inst{47-40} = enc{47-40}; 1873 let Inst{7-0} = enc{7-0}; 1874} 1875 1876class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern> 1877 : InstRXa<0, outs, ins, asmstr, pattern> { 1878 bits<32> enc; 1879 1880 let Inst{31-24} = enc{31-24}; 1881} 1882 1883class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern> 1884 : InstRXE<0, outs, ins, asmstr, pattern> { 1885 bits<48> enc; 1886 1887 let M3 = 0; 1888 1889 let Inst{47-40} = enc{47-40}; 1890 let Inst{7-0} = enc{7-0}; 1891} 1892 1893class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern> 1894 : InstRXF<0, outs, ins, asmstr, pattern> { 1895 bits<48> enc; 1896 1897 let Inst{47-40} = enc{47-40}; 1898 let Inst{7-0} = enc{7-0}; 1899} 1900 1901class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern> 1902 : InstRXYa<0, outs, ins, asmstr, pattern> { 1903 bits<48> enc; 1904 1905 let Inst{47-40} = enc{47-40}; 1906 let Inst{7-0} = enc{7-0}; 1907} 1908 1909class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern> 1910 : InstS<0, outs, ins, asmstr, pattern> { 1911 bits<32> enc; 1912 1913 let Inst{31-16} = enc{31-16}; 1914} 1915 1916class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern> 1917 : InstSI<0, outs, ins, asmstr, pattern> { 1918 bits<32> enc; 1919 1920 let Inst{31-24} = enc{31-24}; 1921} 1922 1923class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern> 1924 : InstSIY<0, outs, ins, asmstr, pattern> { 1925 bits<48> enc; 1926 1927 let Inst{47-40} = enc{47-40}; 1928 let Inst{7-0} = enc{7-0}; 1929} 1930 1931class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern> 1932 : InstSIL<0, outs, ins, asmstr, pattern> { 1933 bits<48> enc; 1934 1935 let Inst{47-32} = enc{47-32}; 1936} 1937 1938class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern> 1939 : InstSSd<0, outs, ins, asmstr, pattern> { 1940 bits<48> enc; 1941 1942 let Inst{47-40} = enc{47-40}; 1943} 1944 1945class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern> 1946 : InstSSE<0, outs, ins, asmstr, pattern> { 1947 bits<48> enc; 1948 1949 let Inst{47-32} = enc{47-32}; 1950} 1951 1952class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern> 1953 : InstSSF<0, outs, ins, asmstr, pattern> { 1954 bits<48> enc; 1955 1956 let Inst{47-40} = enc{47-40}; 1957 let Inst{35-32} = enc{35-32}; 1958} 1959 1960class DirectiveInsnVRI<dag outs, dag ins, string asmstr, list<dag> pattern> 1961 : InstVRIe<0, outs, ins, asmstr, pattern> { 1962 bits<48> enc; 1963 1964 let Inst{47-40} = enc{47-40}; 1965 let Inst{7-0} = enc{7-0}; 1966} 1967 1968class DirectiveInsnVRR<dag outs, dag ins, string asmstr, list<dag> pattern> 1969 : InstVRRc<0, outs, ins, asmstr, pattern> { 1970 bits<48> enc; 1971 1972 let Inst{47-40} = enc{47-40}; 1973 let Inst{7-0} = enc{7-0}; 1974} 1975 1976class DirectiveInsnVRS<dag outs, dag ins, string asmstr, list<dag> pattern> 1977 : InstVRSc<0, outs, ins, asmstr, pattern> { 1978 bits<48> enc; 1979 1980 let Inst{47-40} = enc{47-40}; 1981 let Inst{7-0} = enc{7-0}; 1982} 1983 1984class DirectiveInsnVRV<dag outs, dag ins, string asmstr, list<dag> pattern> 1985 : InstVRV<0, outs, ins, asmstr, pattern> { 1986 bits<48> enc; 1987 1988 let Inst{47-40} = enc{47-40}; 1989 let Inst{7-0} = enc{7-0}; 1990} 1991 1992class DirectiveInsnVRX<dag outs, dag ins, string asmstr, list<dag> pattern> 1993 : InstVRX<0, outs, ins, asmstr, pattern> { 1994 bits<48> enc; 1995 1996 let Inst{47-40} = enc{47-40}; 1997 let Inst{7-0} = enc{7-0}; 1998} 1999 2000class DirectiveInsnVSI<dag outs, dag ins, string asmstr, list<dag> pattern> 2001 : InstVSI<0, outs, ins, asmstr, pattern> { 2002 bits<48> enc; 2003 2004 let Inst{47-40} = enc{47-40}; 2005 let Inst{7-0} = enc{7-0}; 2006} 2007 2008 2009//===----------------------------------------------------------------------===// 2010// Variants of instructions with condition mask 2011//===----------------------------------------------------------------------===// 2012// 2013// For instructions using a condition mask (e.g. conditional branches, 2014// compare-and-branch instructions, or conditional move instructions), 2015// we generally need to create multiple instruction patterns: 2016// 2017// - One used for code generation, which encodes the condition mask as an 2018// MI operand, but writes out an extended mnemonic for better readability. 2019// - One pattern for the base form of the instruction with an explicit 2020// condition mask (encoded as a plain integer MI operand). 2021// - Specific patterns for each extended mnemonic, where the condition mask 2022// is implied by the pattern name and not otherwise encoded at all. 2023// 2024// We need the latter primarily for the assembler and disassembler, since the 2025// assembler parser is not able to decode part of an instruction mnemonic 2026// into an operand. Thus we provide separate patterns for each mnemonic. 2027// 2028// Note that in some cases there are two different mnemonics for the same 2029// condition mask. In this case we cannot have both instructions available 2030// to the disassembler at the same time since the encodings are not distinct. 2031// Therefore the alternate forms are marked isAsmParserOnly. 2032// 2033// We don't make one of the two names an alias of the other because 2034// we need the custom parsing routines to select the correct register class. 2035// 2036// This section provides helpers for generating the specific forms. 2037// 2038//===----------------------------------------------------------------------===// 2039 2040// A class to describe a variant of an instruction with condition mask. 2041class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein, 2042 string asmvariantin = ""> { 2043 // The fixed condition mask to use. 2044 bits<4> ccmask = ccmaskin; 2045 2046 // The suffix to use for the extended assembler mnemonic. 2047 string suffix = suffixin; 2048 2049 // Whether this is an alternate that needs to be marked isAsmParserOnly. 2050 bit alternate = alternatein; 2051 2052 // Whether this needs be to restricted to a specific dialect. 2053 // Valid values are "att" and "hlasm", which when passed in 2054 // will set AsmVariantName. 2055 string asmvariant = asmvariantin; 2056} 2057 2058// Condition mask 15 means "always true", which is used to define 2059// unconditional branches as a variant of conditional branches. 2060def CondAlways : CondVariant<15, "", 0>; 2061 2062// Condition masks for general instructions that can set all 4 bits. 2063def CondVariantO : CondVariant<1, "o", 0>; 2064def CondVariantH : CondVariant<2, "h", 0>; 2065def CondVariantP : CondVariant<2, "p", 1>; 2066def CondVariantNLE : CondVariant<3, "nle", 0, "att">; 2067def CondVariantL : CondVariant<4, "l", 0>; 2068def CondVariantM : CondVariant<4, "m", 1>; 2069def CondVariantNHE : CondVariant<5, "nhe", 0, "att">; 2070def CondVariantLH : CondVariant<6, "lh", 0, "att">; 2071def CondVariantNE : CondVariant<7, "ne", 0>; 2072def CondVariantNZ : CondVariant<7, "nz", 1>; 2073def CondVariantE : CondVariant<8, "e", 0>; 2074def CondVariantZ : CondVariant<8, "z", 1>; 2075def CondVariantNLH : CondVariant<9, "nlh", 0, "att">; 2076def CondVariantHE : CondVariant<10, "he", 0, "att">; 2077def CondVariantNL : CondVariant<11, "nl", 0>; 2078def CondVariantNM : CondVariant<11, "nm", 1>; 2079def CondVariantLE : CondVariant<12, "le", 0, "att">; 2080def CondVariantNH : CondVariant<13, "nh", 0>; 2081def CondVariantNP : CondVariant<13, "np", 1>; 2082def CondVariantNO : CondVariant<14, "no", 0>; 2083 2084// A helper class to look up one of the above by name. 2085class CV<string name> 2086 : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask, 2087 !cast<CondVariant>("CondVariant"#name).suffix, 2088 !cast<CondVariant>("CondVariant"#name).alternate, 2089 !cast<CondVariant>("CondVariant"#name).asmvariant>; 2090 2091// Condition masks for integer instructions (e.g. compare-and-branch). 2092// This is like the list above, except that condition 3 is not possible 2093// and that the low bit of the mask is therefore always 0. This means 2094// that each condition has two names. Conditions "o" and "no" are not used. 2095def IntCondVariantH : CondVariant<2, "h", 0>; 2096def IntCondVariantNLE : CondVariant<2, "nle", 1, "att">; 2097def IntCondVariantL : CondVariant<4, "l", 0>; 2098def IntCondVariantNHE : CondVariant<4, "nhe", 1, "att">; 2099def IntCondVariantLH : CondVariant<6, "lh", 0, "att">; 2100def IntCondVariantNE : CondVariant<6, "ne", 1>; 2101def IntCondVariantE : CondVariant<8, "e", 0>; 2102def IntCondVariantNLH : CondVariant<8, "nlh", 1, "att">; 2103def IntCondVariantHE : CondVariant<10, "he", 0, "att">; 2104def IntCondVariantNL : CondVariant<10, "nl", 1>; 2105def IntCondVariantLE : CondVariant<12, "le", 0, "att">; 2106def IntCondVariantNH : CondVariant<12, "nh", 1>; 2107 2108// A helper class to look up one of the above by name. 2109class ICV<string name> 2110 : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask, 2111 !cast<CondVariant>("IntCondVariant"#name).suffix, 2112 !cast<CondVariant>("IntCondVariant"#name).alternate, 2113 !cast<CondVariant>("IntCondVariant"#name).asmvariant>; 2114 2115// Defines a class that makes it easier to define 2116// a MnemonicAlias when CondVariant's are involved. 2117multiclass MnemonicCondBranchAlias<CondVariant V, string from, string to, 2118 string asmvariant = V.asmvariant> { 2119 if !or(!eq(V.asmvariant, ""), !eq(V.asmvariant, asmvariant)) then 2120 def "" : MnemonicAlias<!subst("#", V.suffix, from), 2121 !subst("#", V.suffix, to), 2122 asmvariant>; 2123} 2124 2125//===----------------------------------------------------------------------===// 2126// Instruction definitions with semantics 2127//===----------------------------------------------------------------------===// 2128// 2129// These classes have the form [Cond]<Category><Format>, where <Format> is one 2130// of the formats defined above and where <Category> describes the inputs 2131// and outputs. "Cond" is used if the instruction is conditional, 2132// in which case the 4-bit condition-code mask is added as a final operand. 2133// <Category> can be one of: 2134// 2135// Inherent: 2136// One register output operand and no input operands. 2137// 2138// InherentDual: 2139// Two register output operands and no input operands. 2140// 2141// StoreInherent: 2142// One address operand. The instruction stores to the address. 2143// 2144// SideEffectInherent: 2145// No input or output operands, but causes some side effect. 2146// 2147// Branch: 2148// One branch target. The instruction branches to the target. 2149// 2150// Call: 2151// One output operand and one branch target. The instruction stores 2152// the return address to the output operand and branches to the target. 2153// 2154// CmpBranch: 2155// Two input operands and one optional branch target. The instruction 2156// compares the two input operands and branches or traps on the result. 2157// 2158// BranchUnary: 2159// One register output operand, one register input operand and one branch 2160// target. The instructions stores a modified form of the source register 2161// in the destination register and branches on the result. 2162// 2163// BranchBinary: 2164// One register output operand, two register input operands and one branch 2165// target. The instructions stores a modified form of one of the source 2166// registers in the destination register and branches on the result. 2167// 2168// LoadMultiple: 2169// One address input operand and two explicit output operands. 2170// The instruction loads a range of registers from the address, 2171// with the explicit operands giving the first and last register 2172// to load. Other loaded registers are added as implicit definitions. 2173// 2174// StoreMultiple: 2175// Two explicit input register operands and an address operand. 2176// The instruction stores a range of registers to the address, 2177// with the explicit operands giving the first and last register 2178// to store. Other stored registers are added as implicit uses. 2179// 2180// StoreLength: 2181// One value operand, one length operand and one address operand. 2182// The instruction stores the value operand to the address but 2183// doesn't write more than the number of bytes specified by the 2184// length operand. 2185// 2186// LoadAddress: 2187// One register output operand and one address operand. 2188// 2189// SideEffectAddress: 2190// One address operand. No output operands, but causes some side effect. 2191// 2192// Unary: 2193// One register output operand and one input operand. 2194// 2195// Store: 2196// One address operand and one other input operand. The instruction 2197// stores to the address. 2198// 2199// SideEffectUnary: 2200// One input operand. No output operands, but causes some side effect. 2201// 2202// Binary: 2203// One register output operand and two input operands. 2204// 2205// StoreBinary: 2206// One address operand and two other input operands. The instruction 2207// stores to the address. 2208// 2209// SideEffectBinary: 2210// Two input operands. No output operands, but causes some side effect. 2211// 2212// Compare: 2213// Two input operands and an implicit CC output operand. 2214// 2215// Test: 2216// One or two input operands and an implicit CC output operand. If 2217// present, the second input operand is an "address" operand used as 2218// a test class mask. 2219// 2220// Ternary: 2221// One register output operand and three input operands. 2222// 2223// SideEffectTernary: 2224// Three input operands. No output operands, but causes some side effect. 2225// 2226// Quaternary: 2227// One register output operand and four input operands. 2228// 2229// LoadAndOp: 2230// One output operand and two input operands, one of which is an address. 2231// The instruction both reads from and writes to the address. 2232// 2233// CmpSwap: 2234// One output operand and three input operands, one of which is an address. 2235// The instruction both reads from and writes to the address. 2236// 2237// RotateSelect: 2238// One output operand and five input operands. The first two operands 2239// are registers and the other three are immediates. 2240// 2241// Prefetch: 2242// One 4-bit immediate operand and one address operand. The immediate 2243// operand is 1 for a load prefetch and 2 for a store prefetch. 2244// 2245// BranchPreload: 2246// One 4-bit immediate operand and two address operands. 2247// 2248// The format determines which input operands are tied to output operands, 2249// and also determines the shape of any address operand. 2250// 2251// Multiclasses of the form <Category><Format>Pair define two instructions, 2252// one with <Category><Format> and one with <Category><Format>Y. The name 2253// of the first instruction has no suffix, the name of the second has 2254// an extra "y". 2255// 2256//===----------------------------------------------------------------------===// 2257 2258class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 2259 SDPatternOperator operator> 2260 : InstRRE<opcode, (outs cls:$R1), (ins), 2261 mnemonic#"\t$R1", 2262 [(set cls:$R1, (operator))]> { 2263 let R2 = 0; 2264} 2265 2266class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 2267 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins), 2268 mnemonic#"\t$R1, $R2", []>; 2269 2270class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value> 2271 : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> { 2272 let I2 = value; 2273 let M3 = 0; 2274} 2275 2276class StoreInherentS<string mnemonic, bits<16> opcode, 2277 SDPatternOperator operator, bits<5> bytes> 2278 : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2), 2279 mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> { 2280 let mayStore = 1; 2281 let AccessBytes = bytes; 2282} 2283 2284class SideEffectInherentE<string mnemonic, bits<16>opcode> 2285 : InstE<opcode, (outs), (ins), mnemonic, []>; 2286 2287class SideEffectInherentS<string mnemonic, bits<16> opcode, 2288 SDPatternOperator operator> 2289 : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> { 2290 let B2 = 0; 2291 let D2 = 0; 2292} 2293 2294class SideEffectInherentRRE<string mnemonic, bits<16> opcode> 2295 : InstRRE<opcode, (outs), (ins), mnemonic, []> { 2296 let R1 = 0; 2297 let R2 = 0; 2298} 2299 2300// Allow an optional TLS marker symbol to generate TLS call relocations. 2301class CallRI<string mnemonic, bits<12> opcode> 2302 : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2), 2303 mnemonic#"\t$R1, $RI2", []>; 2304 2305// Allow an optional TLS marker symbol to generate TLS call relocations. 2306class CallRIL<string mnemonic, bits<12> opcode> 2307 : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2), 2308 mnemonic#"\t$R1, $RI2", []>; 2309 2310class CallRR<string mnemonic, bits<8> opcode> 2311 : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2), 2312 mnemonic#"\t$R1, $R2", []>; 2313 2314class CallRX<string mnemonic, bits<8> opcode> 2315 : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2316 mnemonic#"\t$R1, $XBD2", []>; 2317 2318class CondBranchRI<string mnemonic, bits<12> opcode, 2319 SDPatternOperator operator = null_frag> 2320 : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2), 2321 !subst("#", "${M1}", mnemonic)#"\t$RI2", 2322 [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> { 2323 let CCMaskFirst = 1; 2324} 2325 2326class AsmCondBranchRI<string mnemonic, bits<12> opcode> 2327 : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2), 2328 mnemonic#"\t$M1, $RI2", []>; 2329 2330class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode, 2331 SDPatternOperator operator = null_frag> 2332 : InstRIc<opcode, (outs), (ins brtarget16:$RI2), 2333 !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> { 2334 let isAsmParserOnly = V.alternate; 2335 let AsmVariantName = V.asmvariant; 2336 let M1 = V.ccmask; 2337} 2338 2339class CondBranchRIL<string mnemonic, bits<12> opcode> 2340 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2), 2341 !subst("#", "${M1}", mnemonic)#"\t$RI2", []> { 2342 let CCMaskFirst = 1; 2343} 2344 2345class AsmCondBranchRIL<string mnemonic, bits<12> opcode> 2346 : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2), 2347 mnemonic#"\t$M1, $RI2", []>; 2348 2349class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode> 2350 : InstRILc<opcode, (outs), (ins brtarget32:$RI2), 2351 !subst("#", V.suffix, mnemonic)#"\t$RI2", []> { 2352 let isAsmParserOnly = V.alternate; 2353 let AsmVariantName = V.asmvariant; 2354 let M1 = V.ccmask; 2355} 2356 2357class CondBranchRR<string mnemonic, bits<8> opcode> 2358 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2), 2359 !subst("#", "${R1}", mnemonic)#"\t$R2", []> { 2360 let CCMaskFirst = 1; 2361} 2362 2363class AsmCondBranchRR<string mnemonic, bits<8> opcode> 2364 : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2), 2365 mnemonic#"\t$R1, $R2", []>; 2366 2367class NeverCondBranchRR<string mnemonic, bits<8> opcode> 2368 : InstRR<opcode, (outs), (ins GR64:$R2), 2369 mnemonic#"\t$R2", []> { 2370 let R1 = 0; 2371} 2372 2373class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode, 2374 SDPatternOperator operator = null_frag> 2375 : InstRR<opcode, (outs), (ins ADDR64:$R2), 2376 !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> { 2377 let isAsmParserOnly = V.alternate; 2378 let AsmVariantName = V.asmvariant; 2379 let R1 = V.ccmask; 2380} 2381 2382class CondBranchRX<string mnemonic, bits<8> opcode> 2383 : InstRXb<opcode, (outs), 2384 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2385 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> { 2386 let CCMaskFirst = 1; 2387} 2388 2389class AsmCondBranchRX<string mnemonic, bits<8> opcode> 2390 : InstRXb<opcode, (outs), 2391 (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2392 mnemonic#"\t$M1, $XBD2", []>; 2393 2394class NeverCondBranchRX<string mnemonic, bits<8> opcode> 2395 : InstRXb<opcode, (outs), 2396 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 2397 mnemonic#"\t$XBD2", []> { 2398 let M1 = 0; 2399} 2400 2401class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode> 2402 : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 2403 !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> { 2404 let isAsmParserOnly = V.alternate; 2405 let AsmVariantName = V.asmvariant; 2406 let M1 = V.ccmask; 2407} 2408 2409class CondBranchRXY<string mnemonic, bits<16> opcode> 2410 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, 2411 (bdxaddr20only $B2, $D2, $X2):$XBD2), 2412 !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> { 2413 let CCMaskFirst = 1; 2414 let mayLoad = 1; 2415} 2416 2417class AsmCondBranchRXY<string mnemonic, bits<16> opcode> 2418 : InstRXYb<opcode, (outs), 2419 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2), 2420 mnemonic#"\t$M1, $XBD2", []> { 2421 let mayLoad = 1; 2422} 2423 2424class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode, 2425 SDPatternOperator operator = null_frag> 2426 : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2), 2427 !subst("#", V.suffix, mnemonic)#"\t$XBD2", 2428 [(operator (load bdxaddr20only:$XBD2))]> { 2429 let isAsmParserOnly = V.alternate; 2430 let AsmVariantName = V.asmvariant; 2431 let M1 = V.ccmask; 2432 let mayLoad = 1; 2433} 2434 2435class CmpBranchRIEa<string mnemonic, bits<16> opcode, 2436 RegisterOperand cls, ImmOpWithPattern imm> 2437 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3), 2438 mnemonic#"$M3\t$R1, $I2", []>; 2439 2440class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode, 2441 RegisterOperand cls, ImmOpWithPattern imm> 2442 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3), 2443 mnemonic#"\t$R1, $I2, $M3", []>; 2444 2445class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode, 2446 RegisterOperand cls, ImmOpWithPattern imm> 2447 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2), 2448 mnemonic#V.suffix#"\t$R1, $I2", []> { 2449 let isAsmParserOnly = V.alternate; 2450 let AsmVariantName = V.asmvariant; 2451 let M3 = V.ccmask; 2452} 2453 2454multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode, 2455 RegisterOperand cls, ImmOpWithPattern imm> { 2456 let isCodeGenOnly = 1 in 2457 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>; 2458 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>; 2459} 2460 2461class CmpBranchRIEb<string mnemonic, bits<16> opcode, 2462 RegisterOperand cls> 2463 : InstRIEb<opcode, (outs), 2464 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4), 2465 mnemonic#"$M3\t$R1, $R2, $RI4", []>; 2466 2467class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode, 2468 RegisterOperand cls> 2469 : InstRIEb<opcode, (outs), 2470 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4), 2471 mnemonic#"\t$R1, $R2, $M3, $RI4", []>; 2472 2473class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode, 2474 RegisterOperand cls> 2475 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4), 2476 mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> { 2477 let isAsmParserOnly = V.alternate; 2478 let AsmVariantName = V.asmvariant; 2479 let M3 = V.ccmask; 2480} 2481 2482multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode, 2483 RegisterOperand cls> { 2484 let isCodeGenOnly = 1 in 2485 def "" : CmpBranchRIEb<mnemonic, opcode, cls>; 2486 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>; 2487} 2488 2489class CmpBranchRIEc<string mnemonic, bits<16> opcode, 2490 RegisterOperand cls, ImmOpWithPattern imm> 2491 : InstRIEc<opcode, (outs), 2492 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4), 2493 mnemonic#"$M3\t$R1, $I2, $RI4", []>; 2494 2495class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode, 2496 RegisterOperand cls, ImmOpWithPattern imm> 2497 : InstRIEc<opcode, (outs), 2498 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4), 2499 mnemonic#"\t$R1, $I2, $M3, $RI4", []>; 2500 2501class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode, 2502 RegisterOperand cls, ImmOpWithPattern imm> 2503 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4), 2504 mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> { 2505 let isAsmParserOnly = V.alternate; 2506 let AsmVariantName = V.asmvariant; 2507 let M3 = V.ccmask; 2508} 2509 2510multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode, 2511 RegisterOperand cls, ImmOpWithPattern imm> { 2512 let isCodeGenOnly = 1 in 2513 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>; 2514 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>; 2515} 2516 2517class CmpBranchRRFc<string mnemonic, bits<16> opcode, 2518 RegisterOperand cls> 2519 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3), 2520 mnemonic#"$M3\t$R1, $R2", []>; 2521 2522class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode, 2523 RegisterOperand cls> 2524 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3), 2525 mnemonic#"\t$R1, $R2, $M3", []>; 2526 2527multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode, 2528 RegisterOperand cls> { 2529 let isCodeGenOnly = 1 in 2530 def "" : CmpBranchRRFc<mnemonic, opcode, cls>; 2531 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>; 2532} 2533 2534class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode, 2535 RegisterOperand cls> 2536 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2), 2537 mnemonic#V.suffix#"\t$R1, $R2", []> { 2538 let isAsmParserOnly = V.alternate; 2539 let AsmVariantName = V.asmvariant; 2540 let M3 = V.ccmask; 2541} 2542 2543class CmpBranchRRS<string mnemonic, bits<16> opcode, 2544 RegisterOperand cls> 2545 : InstRRS<opcode, (outs), 2546 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4), 2547 mnemonic#"$M3\t$R1, $R2, $BD4", []>; 2548 2549class AsmCmpBranchRRS<string mnemonic, bits<16> opcode, 2550 RegisterOperand cls> 2551 : InstRRS<opcode, (outs), 2552 (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4), 2553 mnemonic#"\t$R1, $R2, $M3, $BD4", []>; 2554 2555class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode, 2556 RegisterOperand cls> 2557 : InstRRS<opcode, (outs), 2558 (ins cls:$R1, cls:$R2, (bdaddr12only $B4, $D4):$BD4), 2559 mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> { 2560 let isAsmParserOnly = V.alternate; 2561 let AsmVariantName = V.asmvariant; 2562 let M3 = V.ccmask; 2563} 2564 2565multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode, 2566 RegisterOperand cls> { 2567 let isCodeGenOnly = 1 in 2568 def "" : CmpBranchRRS<mnemonic, opcode, cls>; 2569 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>; 2570} 2571 2572class CmpBranchRIS<string mnemonic, bits<16> opcode, 2573 RegisterOperand cls, ImmOpWithPattern imm> 2574 : InstRIS<opcode, (outs), 2575 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4), 2576 mnemonic#"$M3\t$R1, $I2, $BD4", []>; 2577 2578class AsmCmpBranchRIS<string mnemonic, bits<16> opcode, 2579 RegisterOperand cls, ImmOpWithPattern imm> 2580 : InstRIS<opcode, (outs), 2581 (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4), 2582 mnemonic#"\t$R1, $I2, $M3, $BD4", []>; 2583 2584class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode, 2585 RegisterOperand cls, ImmOpWithPattern imm> 2586 : InstRIS<opcode, (outs), 2587 (ins cls:$R1, imm:$I2, (bdaddr12only $B4, $D4):$BD4), 2588 mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> { 2589 let isAsmParserOnly = V.alternate; 2590 let AsmVariantName = V.asmvariant; 2591 let M3 = V.ccmask; 2592} 2593 2594multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode, 2595 RegisterOperand cls, ImmOpWithPattern imm> { 2596 let isCodeGenOnly = 1 in 2597 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>; 2598 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>; 2599} 2600 2601class CmpBranchRSYb<string mnemonic, bits<16> opcode, 2602 RegisterOperand cls> 2603 : InstRSYb<opcode, (outs), 2604 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3), 2605 mnemonic#"$M3\t$R1, $BD2", []>; 2606 2607class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode, 2608 RegisterOperand cls> 2609 : InstRSYb<opcode, (outs), 2610 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3), 2611 mnemonic#"\t$R1, $M3, $BD2", []>; 2612 2613multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode, 2614 RegisterOperand cls> { 2615 let isCodeGenOnly = 1 in 2616 def "" : CmpBranchRSYb<mnemonic, opcode, cls>; 2617 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>; 2618} 2619 2620class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode, 2621 RegisterOperand cls> 2622 : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2), 2623 mnemonic#V.suffix#"\t$R1, $BD2", []> { 2624 let isAsmParserOnly = V.alternate; 2625 let AsmVariantName = V.asmvariant; 2626 let M3 = V.ccmask; 2627} 2628 2629class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls> 2630 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2), 2631 mnemonic#"\t$R1, $RI2", []> { 2632 let Constraints = "$R1 = $R1src"; 2633 let DisableEncoding = "$R1src"; 2634} 2635 2636class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls> 2637 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2), 2638 mnemonic#"\t$R1, $RI2", []> { 2639 let Constraints = "$R1 = $R1src"; 2640 let DisableEncoding = "$R1src"; 2641} 2642 2643class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls> 2644 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2), 2645 mnemonic#"\t$R1, $R2", []> { 2646 let Constraints = "$R1 = $R1src"; 2647 let DisableEncoding = "$R1src"; 2648} 2649 2650class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 2651 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2), 2652 mnemonic#"\t$R1, $R2", []> { 2653 let Constraints = "$R1 = $R1src"; 2654 let DisableEncoding = "$R1src"; 2655} 2656 2657class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls> 2658 : InstRXa<opcode, (outs cls:$R1), 2659 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2660 mnemonic#"\t$R1, $XBD2", []> { 2661 let Constraints = "$R1 = $R1src"; 2662 let DisableEncoding = "$R1src"; 2663} 2664 2665class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls> 2666 : InstRXYa<opcode, (outs cls:$R1), 2667 (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2), 2668 mnemonic#"\t$R1, $XBD2", []> { 2669 let Constraints = "$R1 = $R1src"; 2670 let DisableEncoding = "$R1src"; 2671} 2672 2673class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls> 2674 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2), 2675 mnemonic#"\t$R1, $R3, $RI2", []> { 2676 let Constraints = "$R1 = $R1src"; 2677 let DisableEncoding = "$R1src"; 2678} 2679 2680class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls> 2681 : InstRIEe<opcode, (outs cls:$R1), 2682 (ins cls:$R1src, cls:$R3, brtarget16:$RI2), 2683 mnemonic#"\t$R1, $R3, $RI2", []> { 2684 let Constraints = "$R1 = $R1src"; 2685 let DisableEncoding = "$R1src"; 2686} 2687 2688class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls> 2689 : InstRSa<opcode, (outs cls:$R1), 2690 (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2), 2691 mnemonic#"\t$R1, $R3, $BD2", []> { 2692 let Constraints = "$R1 = $R1src"; 2693 let DisableEncoding = "$R1src"; 2694} 2695 2696class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls> 2697 : InstRSYa<opcode, 2698 (outs cls:$R1), 2699 (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2), 2700 mnemonic#"\t$R1, $R3, $BD2", []> { 2701 let Constraints = "$R1 = $R1src"; 2702 let DisableEncoding = "$R1src"; 2703} 2704 2705class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 2706 AddressingMode mode = bdaddr12only> 2707 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2), 2708 mnemonic#"\t$R1, $R3, $BD2", []> { 2709 let mayLoad = 1; 2710} 2711 2712class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 2713 AddressingMode mode = bdaddr20only> 2714 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2), 2715 mnemonic#"\t$R1, $R3, $BD2", []> { 2716 let mayLoad = 1; 2717} 2718 2719multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode, 2720 bits<16> rsyOpcode, RegisterOperand cls> { 2721 let DispKey = mnemonic # cls in { 2722 let DispSize = "12" in 2723 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>; 2724 let DispSize = "20" in 2725 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>; 2726 } 2727} 2728 2729class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls> 2730 : InstSSe<opcode, (outs cls:$R1, cls:$R3), 2731 (ins (bdaddr12only $B2, $D2):$BD2, (bdaddr12only $B4, $D4):$BD4), 2732 mnemonic#"\t$R1, $R3, $BD2, $BD4", []> { 2733 let mayLoad = 1; 2734} 2735 2736multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> { 2737 let mayLoad = 1 in { 2738 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), 2739 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4), 2740 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 2741 let M4 = 0 in 2742 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), 2743 (ins (bdaddr12only $B2, $D2):$BD2), 2744 mnemonic#"\t$V1, $V3, $BD2", []>; 2745 } 2746} 2747 2748class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 2749 RegisterOperand cls> 2750 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 2751 mnemonic#"\t$R1, $RI2", 2752 [(operator cls:$R1, pcrel32:$RI2)]> { 2753 let mayStore = 1; 2754 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 2755 // However, BDXs have two extra operands and are therefore 6 units more 2756 // complex. 2757 let AddedComplexity = 7; 2758} 2759 2760class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2761 RegisterOperand cls, bits<5> bytes, 2762 AddressingMode mode = bdxaddr12only> 2763 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 2764 mnemonic#"\t$R1, $XBD2", 2765 [(operator cls:$R1, mode:$XBD2)]> { 2766 let OpKey = mnemonic#"r"#cls; 2767 let OpType = "mem"; 2768 let mayStore = 1; 2769 let AccessBytes = bytes; 2770} 2771 2772class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2773 RegisterOperand cls, bits<5> bytes, 2774 AddressingMode mode = bdxaddr20only> 2775 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 2776 mnemonic#"\t$R1, $XBD2", 2777 [(operator cls:$R1, mode:$XBD2)]> { 2778 let OpKey = mnemonic#"r"#cls; 2779 let OpType = "mem"; 2780 let mayStore = 1; 2781 let AccessBytes = bytes; 2782} 2783 2784multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 2785 SDPatternOperator operator, RegisterOperand cls, 2786 bits<5> bytes> { 2787 let DispKey = mnemonic # cls in { 2788 let DispSize = "12" in 2789 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 2790 let DispSize = "20" in 2791 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 2792 bdxaddr20pair>; 2793 } 2794} 2795 2796class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2797 TypedReg tr, bits<5> bytes, bits<4> type = 0> 2798 : InstVRX<opcode, (outs), 2799 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2800 mnemonic#"\t$V1, $XBD2", 2801 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2)]> { 2802 let M3 = type; 2803 let mayStore = 1; 2804 let AccessBytes = bytes; 2805} 2806 2807class StoreVRXGeneric<string mnemonic, bits<16> opcode> 2808 : InstVRX<opcode, (outs), 2809 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 2810 mnemonic#"\t$V1, $XBD2, $M3", []> { 2811 let mayStore = 1; 2812} 2813 2814multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> { 2815 let mayStore = 1, AccessBytes = 16 in { 2816 def Align : InstVRX<opcode, (outs), 2817 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, 2818 imm32zx4:$M3), 2819 mnemonic#"\t$V1, $XBD2, $M3", []>; 2820 let M3 = 0 in 2821 def "" : InstVRX<opcode, (outs), 2822 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2823 mnemonic#"\t$V1, $XBD2", []>; 2824 } 2825} 2826 2827class StoreLengthVRSb<string mnemonic, bits<16> opcode, 2828 SDPatternOperator operator, bits<5> bytes> 2829 : InstVRSb<opcode, (outs), 2830 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 2831 mnemonic#"\t$V1, $R3, $BD2", 2832 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 2833 let M4 = 0; 2834 let mayStore = 1; 2835 let AccessBytes = bytes; 2836} 2837 2838class StoreLengthVRSd<string mnemonic, bits<16> opcode, 2839 SDPatternOperator operator, bits<5> bytes> 2840 : InstVRSd<opcode, (outs), 2841 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 2842 mnemonic#"\t$V1, $R3, $BD2", 2843 [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> { 2844 let mayStore = 1; 2845 let AccessBytes = bytes; 2846} 2847 2848class StoreLengthVSI<string mnemonic, bits<16> opcode, 2849 SDPatternOperator operator, bits<5> bytes> 2850 : InstVSI<opcode, (outs), 2851 (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 2852 mnemonic#"\t$V1, $BD2, $I3", 2853 [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> { 2854 let mayStore = 1; 2855 let AccessBytes = bytes; 2856} 2857 2858class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 2859 AddressingMode mode = bdaddr12only> 2860 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2), 2861 mnemonic#"\t$R1, $R3, $BD2", []> { 2862 let mayStore = 1; 2863} 2864 2865class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 2866 AddressingMode mode = bdaddr20only> 2867 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2), 2868 mnemonic#"\t$R1, $R3, $BD2", []> { 2869 let mayStore = 1; 2870} 2871 2872multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode, 2873 bits<16> rsyOpcode, RegisterOperand cls> { 2874 let DispKey = mnemonic # cls in { 2875 let DispSize = "12" in 2876 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>; 2877 let DispSize = "20" in 2878 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>; 2879 } 2880} 2881 2882multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> { 2883 let mayStore = 1 in { 2884 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, 2885 (bdaddr12only $B2, $D2):$BD2, 2886 imm32zx4:$M4), 2887 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 2888 let M4 = 0 in 2889 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, 2890 (bdaddr12only $B2, $D2):$BD2), 2891 mnemonic#"\t$V1, $V3, $BD2", []>; 2892 } 2893} 2894 2895// StoreSI* instructions are used to store an integer to memory, but the 2896// addresses are more restricted than for normal stores. If we are in the 2897// situation of having to force either the address into a register or the 2898// constant into a register, it's usually better to do the latter. 2899// We therefore match the address in the same way as a normal store and 2900// only use the StoreSI* instruction if the matched address is suitable. 2901class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 2902 ImmOpWithPattern imm> 2903 : InstSI<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2), 2904 mnemonic#"\t$BD1, $I2", 2905 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 2906 let mayStore = 1; 2907} 2908 2909class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2910 ImmOpWithPattern imm> 2911 : InstSIY<opcode, (outs), (ins (mviaddr20pair $B1, $D1):$BD1, imm:$I2), 2912 mnemonic#"\t$BD1, $I2", 2913 [(operator imm:$I2, mviaddr20pair:$BD1)]> { 2914 let mayStore = 1; 2915} 2916 2917class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 2918 ImmOpWithPattern imm> 2919 : InstSIL<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2), 2920 mnemonic#"\t$BD1, $I2", 2921 [(operator imm:$I2, mviaddr12pair:$BD1)]> { 2922 let mayStore = 1; 2923} 2924 2925multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 2926 SDPatternOperator operator, ImmOpWithPattern imm> { 2927 let DispKey = mnemonic in { 2928 let DispSize = "12" in 2929 def "" : StoreSI<mnemonic, siOpcode, operator, imm>; 2930 let DispSize = "20" in 2931 def Y : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>; 2932 } 2933} 2934 2935class StoreSSE<string mnemonic, bits<16> opcode> 2936 : InstSSE<opcode, (outs), 2937 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2), 2938 mnemonic#"\t$BD1, $BD2", []> { 2939 let mayStore = 1; 2940} 2941 2942class CondStoreRSY<string mnemonic, bits<16> opcode, 2943 RegisterOperand cls, bits<5> bytes, 2944 AddressingMode mode = bdaddr20only> 2945 : InstRSYb<opcode, (outs), 2946 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), 2947 mnemonic#"$M3\t$R1, $BD2", []> { 2948 let mayStore = 1; 2949 let AccessBytes = bytes; 2950 let CCMaskLast = 1; 2951} 2952 2953// Like CondStoreRSY, but used for the raw assembly form. The condition-code 2954// mask is the third operand rather than being part of the mnemonic. 2955class AsmCondStoreRSY<string mnemonic, bits<16> opcode, 2956 RegisterOperand cls, bits<5> bytes, 2957 AddressingMode mode = bdaddr20only> 2958 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3), 2959 mnemonic#"\t$R1, $BD2, $M3", []> { 2960 let mayStore = 1; 2961 let AccessBytes = bytes; 2962} 2963 2964// Like CondStoreRSY, but with a fixed CC mask. 2965class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode, 2966 RegisterOperand cls, bits<5> bytes, 2967 AddressingMode mode = bdaddr20only> 2968 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2), 2969 mnemonic#V.suffix#"\t$R1, $BD2", []> { 2970 let mayStore = 1; 2971 let AccessBytes = bytes; 2972 let isAsmParserOnly = V.alternate; 2973 let AsmVariantName = V.asmvariant; 2974 let M3 = V.ccmask; 2975} 2976 2977multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode, 2978 RegisterOperand cls, bits<5> bytes, 2979 AddressingMode mode = bdaddr20only> { 2980 let isCodeGenOnly = 1 in 2981 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>; 2982 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>; 2983} 2984 2985class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm> 2986 : InstI<opcode, (outs), (ins imm:$I1), 2987 mnemonic#"\t$I1", []>; 2988 2989class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls> 2990 : InstRR<opcode, (outs), (ins cls:$R1), 2991 mnemonic#"\t$R1", []> { 2992 let R2 = 0; 2993} 2994 2995class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls, 2996 SDPatternOperator operator> 2997 : InstRRE<opcode, (outs), (ins cls:$R1), 2998 mnemonic#"\t$R1", [(operator cls:$R1)]> { 2999 let R2 = 0; 3000} 3001 3002class SideEffectUnaryS<string mnemonic, bits<16> opcode, 3003 SDPatternOperator operator, bits<5> bytes, 3004 AddressingMode mode = bdaddr12only> 3005 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2), 3006 mnemonic#"\t$BD2", [(operator mode:$BD2)]> { 3007 let mayLoad = 1; 3008 let AccessBytes = bytes; 3009} 3010 3011class SideEffectUnarySIY<string mnemonic, bits<16> opcode, 3012 bits<5> bytes, 3013 AddressingMode mode = bdaddr20only> 3014 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1), 3015 mnemonic#"\t$BD1", []> { 3016 let mayLoad = 1; 3017 let AccessBytes = bytes; 3018 let I2 = 0; 3019} 3020 3021class SideEffectAddressS<string mnemonic, bits<16> opcode, 3022 SDPatternOperator operator, 3023 AddressingMode mode = bdaddr12only> 3024 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2), 3025 mnemonic#"\t$BD2", [(operator mode:$BD2)]>; 3026 3027class LoadAddressRX<string mnemonic, bits<8> opcode, 3028 SDPatternOperator operator, AddressingMode mode> 3029 : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3030 mnemonic#"\t$R1, $XBD2", 3031 [(set GR64:$R1, (operator mode:$XBD2))]>; 3032 3033class LoadAddressRXY<string mnemonic, bits<16> opcode, 3034 SDPatternOperator operator, AddressingMode mode> 3035 : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3036 mnemonic#"\t$R1, $XBD2", 3037 [(set GR64:$R1, (operator mode:$XBD2))]>; 3038 3039multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode, 3040 bits<16> rxyOpcode, SDPatternOperator operator> { 3041 let DispKey = mnemonic in { 3042 let DispSize = "12" in 3043 def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>; 3044 let DispSize = "20" in 3045 def Y : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>; 3046 } 3047} 3048 3049class LoadAddressRIL<string mnemonic, bits<12> opcode, 3050 SDPatternOperator operator> 3051 : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2), 3052 mnemonic#"\t$R1, $RI2", 3053 [(set GR64:$R1, (operator pcrel32:$RI2))]>; 3054 3055class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3056 RegisterOperand cls1, RegisterOperand cls2> 3057 : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2), 3058 mnemonic#"\t$R1, $R2", 3059 [(set cls1:$R1, (operator cls2:$R2))]> { 3060 let OpKey = mnemonic#cls1; 3061 let OpType = "reg"; 3062} 3063 3064class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3065 RegisterOperand cls1, RegisterOperand cls2> 3066 : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2), 3067 mnemonic#"\t$R1, $R2", 3068 [(set cls1:$R1, (operator cls2:$R2))]> { 3069 let OpKey = mnemonic#cls1; 3070 let OpType = "reg"; 3071} 3072 3073class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls> 3074 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src), 3075 mnemonic#"\t$R1", []> { 3076 let Constraints = "$R1 = $R1src"; 3077 let DisableEncoding = "$R1src"; 3078 let R2 = 0; 3079} 3080 3081class UnaryMemRRFc<string mnemonic, bits<16> opcode, 3082 RegisterOperand cls1, RegisterOperand cls2> 3083 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src), 3084 mnemonic#"\t$R1, $R2", []> { 3085 let Constraints = "$R1 = $R1src"; 3086 let DisableEncoding = "$R1src"; 3087 let M3 = 0; 3088} 3089 3090class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3091 RegisterOperand cls, ImmOpWithPattern imm> 3092 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2), 3093 mnemonic#"\t$R1, $I2", 3094 [(set cls:$R1, (operator imm:$I2))]>; 3095 3096class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3097 RegisterOperand cls, ImmOpWithPattern imm> 3098 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2), 3099 mnemonic#"\t$R1, $I2", 3100 [(set cls:$R1, (operator imm:$I2))]>; 3101 3102class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3103 RegisterOperand cls> 3104 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2), 3105 mnemonic#"\t$R1, $RI2", 3106 [(set cls:$R1, (operator pcrel32:$RI2))]> { 3107 let mayLoad = 1; 3108 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 3109 // However, BDXs have two extra operands and are therefore 6 units more 3110 // complex. 3111 let AddedComplexity = 7; 3112} 3113 3114class CondUnaryRSY<string mnemonic, bits<16> opcode, 3115 SDPatternOperator operator, RegisterOperand cls, 3116 bits<5> bytes, AddressingMode mode = bdaddr20only> 3117 : InstRSYb<opcode, (outs cls:$R1), 3118 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), 3119 mnemonic#"$M3\t$R1, $BD2", 3120 [(set cls:$R1, 3121 (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src, 3122 cond4:$valid, cond4:$M3))]> { 3123 let Constraints = "$R1 = $R1src"; 3124 let DisableEncoding = "$R1src"; 3125 let mayLoad = 1; 3126 let AccessBytes = bytes; 3127 let CCMaskLast = 1; 3128 let OpKey = mnemonic#"r"#cls; 3129 let OpType = "mem"; 3130 let MemKey = mnemonic#cls; 3131 let MemType = "target"; 3132} 3133 3134// Like CondUnaryRSY, but used for the raw assembly form. The condition-code 3135// mask is the third operand rather than being part of the mnemonic. 3136class AsmCondUnaryRSY<string mnemonic, bits<16> opcode, 3137 RegisterOperand cls, bits<5> bytes, 3138 AddressingMode mode = bdaddr20only> 3139 : InstRSYb<opcode, (outs cls:$R1), 3140 (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3), 3141 mnemonic#"\t$R1, $BD2, $M3", []> { 3142 let mayLoad = 1; 3143 let AccessBytes = bytes; 3144 let Constraints = "$R1 = $R1src"; 3145 let DisableEncoding = "$R1src"; 3146} 3147 3148// Like CondUnaryRSY, but with a fixed CC mask. 3149class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode, 3150 RegisterOperand cls, bits<5> bytes, 3151 AddressingMode mode = bdaddr20only> 3152 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2), 3153 mnemonic#V.suffix#"\t$R1, $BD2", []> { 3154 let Constraints = "$R1 = $R1src"; 3155 let DisableEncoding = "$R1src"; 3156 let mayLoad = 1; 3157 let AccessBytes = bytes; 3158 let isAsmParserOnly = V.alternate; 3159 let AsmVariantName = V.asmvariant; 3160 let M3 = V.ccmask; 3161} 3162 3163multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode, 3164 SDPatternOperator operator, 3165 RegisterOperand cls, bits<5> bytes, 3166 AddressingMode mode = bdaddr20only> { 3167 let isCodeGenOnly = 1 in 3168 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>; 3169 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>; 3170} 3171 3172class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3173 RegisterOperand cls, bits<5> bytes, 3174 AddressingMode mode = bdxaddr12only> 3175 : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3176 mnemonic#"\t$R1, $XBD2", 3177 [(set cls:$R1, (operator mode:$XBD2))]> { 3178 let OpKey = mnemonic#"r"#cls; 3179 let OpType = "mem"; 3180 let mayLoad = 1; 3181 let AccessBytes = bytes; 3182} 3183 3184class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3185 RegisterOperand cls, bits<5> bytes> 3186 : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 3187 mnemonic#"\t$R1, $XBD2", 3188 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> { 3189 let OpKey = mnemonic#"r"#cls; 3190 let OpType = "mem"; 3191 let mayLoad = 1; 3192 let AccessBytes = bytes; 3193 let M3 = 0; 3194} 3195 3196class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3197 RegisterOperand cls, bits<5> bytes, 3198 AddressingMode mode = bdxaddr20only> 3199 : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 3200 mnemonic#"\t$R1, $XBD2", 3201 [(set cls:$R1, (operator mode:$XBD2))]> { 3202 let OpKey = mnemonic#"r"#cls; 3203 let OpType = "mem"; 3204 let mayLoad = 1; 3205 let AccessBytes = bytes; 3206} 3207 3208multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 3209 SDPatternOperator operator, RegisterOperand cls, 3210 bits<5> bytes> { 3211 let DispKey = mnemonic # cls in { 3212 let DispSize = "12" in 3213 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>; 3214 let DispSize = "20" in 3215 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes, 3216 bdxaddr20pair>; 3217 } 3218} 3219 3220class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3221 TypedReg tr, ImmOpWithPattern imm, bits<4> type = 0> 3222 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2), 3223 mnemonic#"\t$V1, $I2", 3224 [(set (tr.vt tr.op:$V1), (operator (i32 timm:$I2)))]> { 3225 let M3 = type; 3226} 3227 3228class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm> 3229 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3), 3230 mnemonic#"\t$V1, $I2, $M3", []>; 3231 3232class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3233 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0, 3234 bits<4> m5 = 0, string fp_mnemonic = ""> 3235 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2), 3236 mnemonic#"\t$V1, $V2", 3237 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> { 3238 let M3 = type; 3239 let M4 = m4; 3240 let M5 = m5; 3241 let OpKey = fp_mnemonic#!subst("VR", "FP", !cast<string>(tr1.op)); 3242 let OpType = "reg"; 3243} 3244 3245class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0, 3246 bits<4> m5 = 0> 3247 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), 3248 mnemonic#"\t$V1, $V2, $M3", []> { 3249 let M4 = m4; 3250 let M5 = m5; 3251} 3252 3253class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0> 3254 : InstVRRa<opcode, (outs VR128:$V1), 3255 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4), 3256 mnemonic#"\t$V1, $V2, $M3, $M4", []> { 3257 let M5 = m5; 3258} 3259 3260// Declare a pair of instructions, one which sets CC and one which doesn't. 3261// The CC-setting form ends with "S" and sets the low bit of M5. 3262// The form that does not set CC has an extra operand to optionally allow 3263// specifying arbitrary M5 values in assembler. 3264multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode, 3265 SDPatternOperator operator, 3266 SDPatternOperator operator_cc, 3267 TypedReg tr1, TypedReg tr2, bits<4> type> { 3268 let M3 = type, M4 = 0 in 3269 def "" : InstVRRa<opcode, (outs tr1.op:$V1), 3270 (ins tr2.op:$V2, imm32zx4:$M5), 3271 mnemonic#"\t$V1, $V2, $M5", []>; 3272 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))), 3273 (!cast<Instruction>(NAME) tr2.op:$V2, 0)>; 3274 def : InstAlias<mnemonic#"\t$V1, $V2", 3275 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>; 3276 let Defs = [CC] in 3277 def S : UnaryVRRa<mnemonic#"s", opcode, operator_cc, tr1, tr2, 3278 type, 0, 1>; 3279} 3280 3281multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> { 3282 let M4 = 0, Defs = [CC] in 3283 def "" : InstVRRa<opcode, (outs VR128:$V1), 3284 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5), 3285 mnemonic#"\t$V1, $V2, $M3, $M5", []>; 3286 def : InstAlias<mnemonic#"\t$V1, $V2, $M3", 3287 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, 3288 imm32zx4:$M3, 0)>; 3289} 3290 3291class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3292 TypedReg tr, bits<5> bytes, bits<4> type = 0> 3293 : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 3294 mnemonic#"\t$V1, $XBD2", 3295 [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> { 3296 let M3 = type; 3297 let mayLoad = 1; 3298 let AccessBytes = bytes; 3299} 3300 3301class UnaryVRXGeneric<string mnemonic, bits<16> opcode> 3302 : InstVRX<opcode, (outs VR128:$V1), 3303 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 3304 mnemonic#"\t$V1, $XBD2, $M3", []> { 3305 let mayLoad = 1; 3306} 3307 3308multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> { 3309 let mayLoad = 1, AccessBytes = 16 in { 3310 def Align : InstVRX<opcode, (outs VR128:$V1), 3311 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 3312 mnemonic#"\t$V1, $XBD2, $M3", []>; 3313 let M3 = 0 in 3314 def "" : InstVRX<opcode, (outs VR128:$V1), 3315 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2), 3316 mnemonic#"\t$V1, $XBD2", []>; 3317 } 3318} 3319 3320class SideEffectBinaryRX<string mnemonic, bits<8> opcode, 3321 RegisterOperand cls> 3322 : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 3323 mnemonic#"\t$R1, $XBD2", []>; 3324 3325class SideEffectBinaryRXY<string mnemonic, bits<16> opcode, 3326 RegisterOperand cls> 3327 : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2), 3328 mnemonic#"\t$R1, $XBD2", []>; 3329 3330class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode, 3331 RegisterOperand cls> 3332 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 3333 mnemonic#"\t$R1, $RI2", []> { 3334 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 3335 // However, BDXs have two extra operands and are therefore 6 units more 3336 // complex. 3337 let AddedComplexity = 7; 3338} 3339 3340class SideEffectBinaryRRE<string mnemonic, bits<16> opcode, 3341 RegisterOperand cls1, RegisterOperand cls2> 3342 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3343 mnemonic#"\t$R1, $R2", []>; 3344 3345class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode, 3346 RegisterOperand cls1, RegisterOperand cls2> 3347 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3348 mnemonic#"\t$R1, $R2", []> { 3349 let R3 = 0; 3350 let M4 = 0; 3351} 3352 3353class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode, 3354 RegisterOperand cls1, RegisterOperand cls2> 3355 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2), 3356 mnemonic#"\t$R1, $R2", []> { 3357 let M3 = 0; 3358} 3359 3360class SideEffectBinaryIE<string mnemonic, bits<16> opcode, 3361 ImmOpWithPattern imm1, ImmOpWithPattern imm2> 3362 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2), 3363 mnemonic#"\t$I1, $I2", []>; 3364 3365class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm> 3366 : InstSI<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 3367 mnemonic#"\t$BD1, $I2", []>; 3368 3369class SideEffectBinarySIL<string mnemonic, bits<16> opcode, 3370 SDPatternOperator operator, ImmOpWithPattern imm> 3371 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 3372 mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>; 3373 3374class SideEffectBinarySSa<string mnemonic, bits<8> opcode> 3375 : InstSSa<opcode, (outs), (ins (bdladdr12onlylen8 $B1, $D1, $L1):$BDL1, 3376 (bdaddr12only $B2, $D2):$BD2), 3377 mnemonic#"\t$BDL1, $BD2", []>; 3378 3379class SideEffectBinarySSb<string mnemonic, bits<8> opcode> 3380 : InstSSb<opcode, 3381 (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1, 3382 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2), 3383 mnemonic#"\t$BDL1, $BDL2", []>; 3384 3385class SideEffectBinarySSf<string mnemonic, bits<8> opcode> 3386 : InstSSf<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, 3387 (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2), 3388 mnemonic#"\t$BD1, $BDL2", []>; 3389 3390class SideEffectBinarySSE<string mnemonic, bits<16> opcode> 3391 : InstSSE<opcode, (outs), 3392 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2), 3393 mnemonic#"\t$BD1, $BD2", []>; 3394 3395class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode, 3396 RegisterOperand cls1, RegisterOperand cls2> 3397 : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3398 mnemonic#"\t$R1, $R2", []> { 3399 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3400 let DisableEncoding = "$R1src, $R2src"; 3401} 3402 3403class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode, 3404 RegisterOperand cls1, RegisterOperand cls2> 3405 : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src), 3406 mnemonic#"\t$R1, $R2", []> { 3407 let Constraints = "$R2 = $R2src"; 3408 let DisableEncoding = "$R2src"; 3409} 3410 3411class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode, 3412 RegisterOperand cls1, RegisterOperand cls2> 3413 : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3414 mnemonic#"\t$R1, $R2", []> { 3415 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3416 let DisableEncoding = "$R1src, $R2src"; 3417} 3418 3419class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode, 3420 RegisterOperand cls1, RegisterOperand cls2> 3421 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src), 3422 mnemonic#"\t$R1, $R2", []> { 3423 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 3424 let DisableEncoding = "$R1src, $R2src"; 3425 let M3 = 0; 3426} 3427 3428class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3429 RegisterOperand cls1, RegisterOperand cls2> 3430 : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3431 mnemonic#"\t$R1, $R2", 3432 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 3433 let OpKey = mnemonic#cls1; 3434 let OpType = "reg"; 3435 let Constraints = "$R1 = $R1src"; 3436 let DisableEncoding = "$R1src"; 3437} 3438 3439class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3440 RegisterOperand cls1, RegisterOperand cls2> 3441 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3442 mnemonic#"\t$R1, $R2", 3443 [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> { 3444 let OpKey = mnemonic#cls1; 3445 let OpType = "reg"; 3446 let Constraints = "$R1 = $R1src"; 3447 let DisableEncoding = "$R1src"; 3448} 3449 3450class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3451 RegisterOperand cls1, RegisterOperand cls2> 3452 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2), 3453 mnemonic#"\t$R1, $R3, $R2", 3454 [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> { 3455 let OpKey = mnemonic#cls; 3456 let OpType = "reg"; 3457} 3458 3459class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3460 RegisterOperand cls1, RegisterOperand cls2, 3461 RegisterOperand cls3> 3462 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3), 3463 mnemonic#"\t$R1, $R2, $R3", 3464 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> { 3465 let M4 = 0; 3466 let OpKey = mnemonic#cls1; 3467 let OpType = "reg"; 3468} 3469 3470 3471class UnaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3472 RegisterOperand cls1, RegisterOperand cls2> 3473 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls2:$R3), 3474 mnemonic#"\t$R1, $R2", 3475 [(set cls1:$R1, (operator cls2:$R2, cls2:$R3))]> { 3476 let R3 = R2; 3477 let M4 = 0; 3478 let OpKey = mnemonic#cls1; 3479 let OpType = "reg"; 3480} 3481 3482 3483multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 3484 SDPatternOperator operator, RegisterOperand cls1, 3485 RegisterOperand cls2> { 3486 let NumOpsKey = mnemonic in { 3487 let NumOpsValue = "3" in 3488 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>, 3489 Requires<[FeatureDistinctOps]>; 3490 let NumOpsValue = "2" in 3491 def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>; 3492 } 3493} 3494 3495multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2, 3496 SDPatternOperator operator, RegisterOperand cls1, 3497 RegisterOperand cls2> { 3498 let NumOpsKey = mnemonic in { 3499 let NumOpsValue = "3" in 3500 def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>, 3501 Requires<[FeatureDistinctOps]>; 3502 let NumOpsValue = "2" in 3503 def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>; 3504 } 3505} 3506 3507class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3508 RegisterOperand cls1, RegisterOperand cls2, 3509 RegisterOperand cls3> 3510 : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3), 3511 mnemonic#"\t$R1, $R3, $R2", 3512 [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> { 3513 let M4 = 0; 3514} 3515 3516class BinaryRRFc<string mnemonic, bits<16> opcode, 3517 RegisterOperand cls1, RegisterOperand cls2> 3518 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3), 3519 mnemonic#"\t$R1, $R2, $M3", []>; 3520 3521class BinaryMemRRFc<string mnemonic, bits<16> opcode, 3522 RegisterOperand cls1, RegisterOperand cls2, ImmOpWithPattern imm> 3523 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3), 3524 mnemonic#"\t$R1, $R2, $M3", []> { 3525 let Constraints = "$R1 = $R1src"; 3526 let DisableEncoding = "$R1src"; 3527} 3528 3529multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode, 3530 RegisterOperand cls1, RegisterOperand cls2> { 3531 def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 3532 def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>; 3533} 3534 3535class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3536 RegisterOperand cls2> 3537 : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4), 3538 mnemonic#"\t$R1, $R2, $M4", []>; 3539 3540class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3541 RegisterOperand cls2> 3542 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2), 3543 mnemonic#"\t$R1, $M3, $R2", []> { 3544 let M4 = 0; 3545} 3546 3547class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3548 RegisterOperand cls2> 3549 : InstRRFc<opcode, (outs cls1:$R1), 3550 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), 3551 mnemonic#"$M3\t$R1, $R2", 3552 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src, 3553 cond4:$valid, cond4:$M3))]> { 3554 let Constraints = "$R1 = $R1src"; 3555 let DisableEncoding = "$R1src"; 3556 let CCMaskLast = 1; 3557 let NumOpsKey = !subst("loc", "sel", mnemonic); 3558 let NumOpsValue = "2"; 3559 let OpKey = mnemonic#cls1; 3560 let OpType = "reg"; 3561} 3562 3563// Like CondBinaryRRF, but used for the raw assembly form. The condition-code 3564// mask is the third operand rather than being part of the mnemonic. 3565class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3566 RegisterOperand cls2> 3567 : InstRRFc<opcode, (outs cls1:$R1), 3568 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3), 3569 mnemonic#"\t$R1, $R2, $M3", []> { 3570 let Constraints = "$R1 = $R1src"; 3571 let DisableEncoding = "$R1src"; 3572} 3573 3574// Like CondBinaryRRF, but with a fixed CC mask. 3575class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode, 3576 RegisterOperand cls1, RegisterOperand cls2> 3577 : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 3578 mnemonic#V.suffix#"\t$R1, $R2", []> { 3579 let Constraints = "$R1 = $R1src"; 3580 let DisableEncoding = "$R1src"; 3581 let isAsmParserOnly = V.alternate; 3582 let AsmVariantName = V.asmvariant; 3583 let M3 = V.ccmask; 3584} 3585 3586multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode, 3587 RegisterOperand cls1, RegisterOperand cls2> { 3588 let isCodeGenOnly = 1 in 3589 def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>; 3590 def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>; 3591} 3592 3593class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3594 RegisterOperand cls2, RegisterOperand cls3> 3595 : InstRRFa<opcode, (outs cls1:$R1), 3596 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4), 3597 mnemonic#"$M4\t$R1, $R2, $R3", 3598 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3, 3599 cond4:$valid, cond4:$M4))]> { 3600 let CCMaskLast = 1; 3601 let NumOpsKey = mnemonic; 3602 let NumOpsValue = "3"; 3603 let OpKey = mnemonic#cls1; 3604 let OpType = "reg"; 3605} 3606 3607// Like CondBinaryRRFa, but used for the raw assembly form. The condition-code 3608// mask is the third operand rather than being part of the mnemonic. 3609class AsmCondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1, 3610 RegisterOperand cls2, RegisterOperand cls3> 3611 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4), 3612 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 3613 3614// Like CondBinaryRRFa, but with a fixed CC mask. 3615class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode, 3616 RegisterOperand cls1, RegisterOperand cls2, 3617 RegisterOperand cls3> 3618 : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2), 3619 mnemonic#V.suffix#"\t$R1, $R2, $R3", []> { 3620 let isAsmParserOnly = V.alternate; 3621 let AsmVariantName = V.asmvariant; 3622 let M4 = V.ccmask; 3623} 3624 3625multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode, 3626 RegisterOperand cls1, RegisterOperand cls2, 3627 RegisterOperand cls3> { 3628 let isCodeGenOnly = 1 in 3629 def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 3630 def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 3631} 3632 3633class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3634 RegisterOperand cls, ImmOpWithPattern imm> 3635 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3636 mnemonic#"\t$R1, $I2", 3637 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 3638 let Constraints = "$R1 = $R1src"; 3639 let DisableEncoding = "$R1src"; 3640} 3641 3642class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3643 RegisterOperand cls, ImmOpWithPattern imm> 3644 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2), 3645 mnemonic#"\t$R1, $R3, $I2", 3646 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 3647 3648multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2, 3649 SDPatternOperator operator, RegisterOperand cls, 3650 ImmOpWithPattern imm> { 3651 let NumOpsKey = mnemonic in { 3652 let NumOpsValue = "3" in 3653 def K : BinaryRIE<mnemonic#"k", opcode2, operator, cls, imm>, 3654 Requires<[FeatureDistinctOps]>; 3655 let NumOpsValue = "2" in 3656 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>; 3657 } 3658} 3659 3660class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls, 3661 ImmOpWithPattern imm> 3662 : InstRIEg<opcode, (outs cls:$R1), 3663 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3), 3664 mnemonic#"$M3\t$R1, $I2", 3665 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src, 3666 cond4:$valid, cond4:$M3))]> { 3667 let Constraints = "$R1 = $R1src"; 3668 let DisableEncoding = "$R1src"; 3669 let CCMaskLast = 1; 3670} 3671 3672// Like CondBinaryRIE, but used for the raw assembly form. The condition-code 3673// mask is the third operand rather than being part of the mnemonic. 3674class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls, 3675 ImmOpWithPattern imm> 3676 : InstRIEg<opcode, (outs cls:$R1), 3677 (ins cls:$R1src, imm:$I2, imm32zx4:$M3), 3678 mnemonic#"\t$R1, $I2, $M3", []> { 3679 let Constraints = "$R1 = $R1src"; 3680 let DisableEncoding = "$R1src"; 3681} 3682 3683// Like CondBinaryRIE, but with a fixed CC mask. 3684class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode, 3685 RegisterOperand cls, ImmOpWithPattern imm> 3686 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3687 mnemonic#V.suffix#"\t$R1, $I2", []> { 3688 let Constraints = "$R1 = $R1src"; 3689 let DisableEncoding = "$R1src"; 3690 let isAsmParserOnly = V.alternate; 3691 let AsmVariantName = V.asmvariant; 3692 let M3 = V.ccmask; 3693} 3694 3695multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode, 3696 RegisterOperand cls, ImmOpWithPattern imm> { 3697 let isCodeGenOnly = 1 in 3698 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>; 3699 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>; 3700} 3701 3702class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 3703 RegisterOperand cls, ImmOpWithPattern imm> 3704 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 3705 mnemonic#"\t$R1, $I2", 3706 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 3707 let Constraints = "$R1 = $R1src"; 3708 let DisableEncoding = "$R1src"; 3709} 3710 3711class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3712 RegisterOperand cls> 3713 : InstRSa<opcode, (outs cls:$R1), 3714 (ins cls:$R1src, (shift12only $B2, $D2):$BD2), 3715 mnemonic#"\t$R1, $BD2", 3716 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> { 3717 let R3 = 0; 3718 let Constraints = "$R1 = $R1src"; 3719 let DisableEncoding = "$R1src"; 3720} 3721 3722class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3723 RegisterOperand cls> 3724 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2), 3725 mnemonic#"\t$R1, $R3, $BD2", 3726 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>; 3727 3728multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2, 3729 SDPatternOperator operator, RegisterOperand cls> { 3730 let NumOpsKey = mnemonic in { 3731 let NumOpsValue = "3" in 3732 def K : BinaryRSY<mnemonic#"k", opcode2, operator, cls>, 3733 Requires<[FeatureDistinctOps]>; 3734 let NumOpsValue = "2" in 3735 def "" : BinaryRS<mnemonic, opcode1, operator, cls>; 3736 } 3737} 3738 3739class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls> 3740 : InstRSLb<opcode, (outs cls:$R1), 3741 (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3), 3742 mnemonic#"\t$R1, $BDL2, $M3", []> { 3743 let mayLoad = 1; 3744} 3745 3746class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3747 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3748 AddressingMode mode = bdxaddr12only> 3749 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2), 3750 mnemonic#"\t$R1, $XBD2", 3751 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 3752 let OpKey = mnemonic#"r"#cls; 3753 let OpType = "mem"; 3754 let Constraints = "$R1 = $R1src"; 3755 let DisableEncoding = "$R1src"; 3756 let mayLoad = 1; 3757 let AccessBytes = bytes; 3758} 3759 3760class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3761 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 3762 : InstRXE<opcode, (outs cls:$R1), 3763 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2), 3764 mnemonic#"\t$R1, $XBD2", 3765 [(set cls:$R1, (operator cls:$R1src, 3766 (load bdxaddr12only:$XBD2)))]> { 3767 let OpKey = mnemonic#"r"#cls; 3768 let OpType = "mem"; 3769 let Constraints = "$R1 = $R1src"; 3770 let DisableEncoding = "$R1src"; 3771 let mayLoad = 1; 3772 let AccessBytes = bytes; 3773 let M3 = 0; 3774} 3775 3776class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3777 RegisterOperand cls1, RegisterOperand cls2, 3778 SDPatternOperator load, bits<5> bytes> 3779 : InstRXF<opcode, (outs cls1:$R1), 3780 (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 3781 mnemonic#"\t$R1, $R3, $XBD2", 3782 [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> { 3783 let OpKey = mnemonic#"r"#cls; 3784 let OpType = "mem"; 3785 let mayLoad = 1; 3786 let AccessBytes = bytes; 3787} 3788 3789class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3790 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 3791 AddressingMode mode = bdxaddr20only> 3792 : InstRXYa<opcode, (outs cls:$R1), 3793 (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2), 3794 mnemonic#"\t$R1, $XBD2", 3795 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> { 3796 let OpKey = mnemonic#"r"#cls; 3797 let OpType = "mem"; 3798 let Constraints = "$R1 = $R1src"; 3799 let DisableEncoding = "$R1src"; 3800 let mayLoad = 1; 3801 let AccessBytes = bytes; 3802} 3803 3804multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 3805 SDPatternOperator operator, RegisterOperand cls, 3806 SDPatternOperator load, bits<5> bytes> { 3807 let DispKey = mnemonic # cls in { 3808 let DispSize = "12" in 3809 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 3810 bdxaddr12pair>; 3811 let DispSize = "20" in 3812 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes, 3813 bdxaddr20pair>; 3814 } 3815} 3816 3817class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 3818 Operand imm, AddressingMode mode = bdaddr12only> 3819 : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 3820 mnemonic#"\t$BD1, $I2", 3821 [(store (operator (z_load mode:$BD1), imm:$I2), mode:$BD1)]> { 3822 let mayLoad = 1; 3823 let mayStore = 1; 3824} 3825 3826class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3827 Operand imm, AddressingMode mode = bdaddr20only> 3828 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 3829 mnemonic#"\t$BD1, $I2", 3830 [(store (operator (z_load mode:$BD1), imm:$I2), mode:$BD1)]> { 3831 let mayLoad = 1; 3832 let mayStore = 1; 3833} 3834 3835multiclass BinarySIPair<string mnemonic, bits<8> siOpcode, 3836 bits<16> siyOpcode, SDPatternOperator operator, 3837 Operand imm> { 3838 let DispKey = mnemonic # cls in { 3839 let DispSize = "12" in 3840 def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>; 3841 let DispSize = "20" in 3842 def Y : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>; 3843 } 3844} 3845 3846class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls> 3847 : InstSSF<opcode, (outs cls:$R3), 3848 (ins (bdaddr12pair $B1, $D1):$BD1, (bdaddr12pair $B2, $D2):$BD2), 3849 mnemonic#"\t$R3, $BD1, $BD2", []> { 3850 let mayLoad = 1; 3851} 3852 3853class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3854 TypedReg tr, bits<4> type> 3855 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3), 3856 mnemonic#"\t$V1, $I2, $I3", 3857 [(set (tr.vt tr.op:$V1), (operator imm32zx8_timm:$I2, imm32zx8_timm:$I3))]> { 3858 let M4 = type; 3859} 3860 3861class BinaryVRIbGeneric<string mnemonic, bits<16> opcode> 3862 : InstVRIb<opcode, (outs VR128:$V1), 3863 (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4), 3864 mnemonic#"\t$V1, $I2, $I3, $M4", []>; 3865 3866class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3867 TypedReg tr1, TypedReg tr2, bits<4> type> 3868 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2), 3869 mnemonic#"\t$V1, $V3, $I2", 3870 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3), 3871 imm32zx16_timm:$I2))]> { 3872 let M4 = type; 3873} 3874 3875class BinaryVRIcGeneric<string mnemonic, bits<16> opcode> 3876 : InstVRIc<opcode, (outs VR128:$V1), 3877 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4), 3878 mnemonic#"\t$V1, $V3, $I2, $M4", []>; 3879 3880class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3881 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5> 3882 : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3), 3883 mnemonic#"\t$V1, $V2, $I3", 3884 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3885 imm32zx12_timm:$I3))]> { 3886 let M4 = type; 3887 let M5 = m5; 3888} 3889 3890class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode> 3891 : InstVRIe<opcode, (outs VR128:$V1), 3892 (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 3893 mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>; 3894 3895class BinaryVRIh<string mnemonic, bits<16> opcode> 3896 : InstVRIh<opcode, (outs VR128:$V1), 3897 (ins imm32zx16:$I2, imm32zx4:$I3), 3898 mnemonic#"\t$V1, $I2, $I3", []>; 3899 3900class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3901 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0> 3902 : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5), 3903 mnemonic#"\t$V1, $V2, $M5", 3904 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3905 imm32zx12:$M5))]> { 3906 let M3 = type; 3907 let M4 = m4; 3908} 3909 3910class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode> 3911 : InstVRRa<opcode, (outs VR128:$V1), 3912 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5), 3913 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>; 3914 3915class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3916 TypedReg tr1, TypedReg tr2, bits<4> type = 0, 3917 bits<4> modifier = 0> 3918 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 3919 mnemonic#"\t$V1, $V2, $V3", 3920 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3921 (tr2.vt tr2.op:$V3)))]> { 3922 let M4 = type; 3923 let M5 = modifier; 3924} 3925 3926class BinaryExtraVRRb<string mnemonic, bits<16> opcode, bits<4> type = 0> 3927 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5), 3928 mnemonic#"\t$V1, $V2, $V3, $M5", []> { 3929 let M4 = type; 3930} 3931 3932class BinaryExtraVRRbGeneric<string mnemonic, bits<16> opcode> 3933 : InstVRRb<opcode, (outs VR128:$V1), 3934 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 3935 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 3936 3937// Declare a pair of instructions, one which sets CC and one which doesn't. 3938// The CC-setting form ends with "S" and sets the low bit of M5. 3939multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode, 3940 SDPatternOperator operator, 3941 SDPatternOperator operator_cc, TypedReg tr1, 3942 TypedReg tr2, bits<4> type, bits<4> modifier = 0> { 3943 def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 3944 !and (modifier, 14)>; 3945 let Defs = [CC] in 3946 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 3947 !add (!and (modifier, 14), 1)>; 3948} 3949 3950class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode> 3951 : InstVRRb<opcode, (outs VR128:$V1), 3952 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 3953 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> { 3954 let Defs = [CC]; 3955} 3956 3957// Declare a pair of instructions, one which sets CC and one which doesn't. 3958// The CC-setting form ends with "S" and sets the low bit of M5. 3959// The form that does not set CC has an extra operand to optionally allow 3960// specifying arbitrary M5 values in assembler. 3961multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode, 3962 SDPatternOperator operator, 3963 SDPatternOperator operator_cc, 3964 TypedReg tr1, TypedReg tr2, bits<4> type> { 3965 let M4 = type in 3966 def "" : InstVRRb<opcode, (outs tr1.op:$V1), 3967 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5), 3968 mnemonic#"\t$V1, $V2, $V3, $M5", []>; 3969 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))), 3970 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>; 3971 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 3972 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 3973 tr2.op:$V3, 0)>; 3974 let Defs = [CC] in 3975 def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 1>; 3976} 3977 3978multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> { 3979 let Defs = [CC] in 3980 def "" : InstVRRb<opcode, (outs VR128:$V1), 3981 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 3982 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 3983 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4", 3984 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 3985 imm32zx4:$M4, 0)>; 3986} 3987 3988class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 3989 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0, 3990 bits<4> m6 = 0, string fp_mnemonic = ""> 3991 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3), 3992 mnemonic#"\t$V1, $V2, $V3", 3993 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 3994 (tr2.vt tr2.op:$V3)))]> { 3995 let M4 = type; 3996 let M5 = m5; 3997 let M6 = m6; 3998 let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op)); 3999 let OpType = "reg"; 4000} 4001 4002class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0, 4003 bits<4> m6 = 0> 4004 : InstVRRc<opcode, (outs VR128:$V1), 4005 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4), 4006 mnemonic#"\t$V1, $V2, $V3, $M4", []> { 4007 let M5 = m5; 4008 let M6 = m6; 4009} 4010 4011class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0> 4012 : InstVRRc<opcode, (outs VR128:$V1), 4013 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4014 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> { 4015 let M6 = m6; 4016} 4017 4018// Declare a pair of instructions, one which sets CC and one which doesn't. 4019// The CC-setting form ends with "S" and sets the low bit of M5. 4020multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode, 4021 SDPatternOperator operator, 4022 SDPatternOperator operator_cc, TypedReg tr1, 4023 TypedReg tr2, bits<4> type, bits<4> m5, 4024 bits<4> modifier = 0> { 4025 def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type, 4026 m5, !and (modifier, 14)>; 4027 let Defs = [CC] in 4028 def S : BinaryVRRc<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 4029 m5, !add (!and (modifier, 14), 1)>; 4030} 4031 4032class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode> 4033 : InstVRRc<opcode, (outs VR128:$V1), 4034 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 4035 imm32zx4:$M6), 4036 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>; 4037 4038class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4039 TypedReg tr> 4040 : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3), 4041 mnemonic#"\t$V1, $R2, $R3", 4042 [(set (tr.vt tr.op:$V1), (operator GR64:$R2, GR64:$R3))]>; 4043 4044class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4045 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3), 4046 mnemonic#"\t$R1, $V2, $M3", []> { 4047 let M4 = 0; 4048} 4049 4050class BinaryVRRk<string mnemonic, bits<16> opcode> 4051 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3), 4052 mnemonic#"\t$V1, $V2, $M3", []>; 4053 4054class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4055 TypedReg tr1, TypedReg tr2, bits<4> type> 4056 : InstVRSa<opcode, (outs tr1.op:$V1), 4057 (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2), 4058 mnemonic#"\t$V1, $V3, $BD2", 4059 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3), 4060 shift12only:$BD2))]> { 4061 let M4 = type; 4062} 4063 4064class BinaryVRSaGeneric<string mnemonic, bits<16> opcode> 4065 : InstVRSa<opcode, (outs VR128:$V1), 4066 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4), 4067 mnemonic#"\t$V1, $V3, $BD2, $M4", []>; 4068 4069class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4070 bits<5> bytes> 4071 : InstVRSb<opcode, (outs VR128:$V1), 4072 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 4073 mnemonic#"\t$V1, $R3, $BD2", 4074 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 4075 let M4 = 0; 4076 let mayLoad = 1; 4077 let AccessBytes = bytes; 4078} 4079 4080class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4081 TypedReg tr, bits<4> type> 4082 : InstVRSc<opcode, (outs GR64:$R1), 4083 (ins tr.op:$V3, (shift12only $B2, $D2):$BD2), 4084 mnemonic#"\t$R1, $V3, $BD2", 4085 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> { 4086 let M4 = type; 4087} 4088 4089class BinaryVRScGeneric<string mnemonic, bits<16> opcode> 4090 : InstVRSc<opcode, (outs GR64:$R1), 4091 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4), 4092 mnemonic#"\t$R1, $V3, $BD2, $M4", []>; 4093 4094class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4095 bits<5> bytes> 4096 : InstVRSd<opcode, (outs VR128:$V1), 4097 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2), 4098 mnemonic#"\t$V1, $R3, $BD2", 4099 [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> { 4100 let mayLoad = 1; 4101 let AccessBytes = bytes; 4102} 4103 4104class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4105 TypedReg tr, bits<5> bytes> 4106 : InstVRX<opcode, (outs VR128:$V1), 4107 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 4108 mnemonic#"\t$V1, $XBD2, $M3", 4109 [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2, 4110 imm32zx4_timm:$M3))]> { 4111 let mayLoad = 1; 4112 let AccessBytes = bytes; 4113} 4114 4115class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 4116 bits<5> bytes, AddressingMode mode = bdaddr12only> 4117 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4118 mnemonic#"\t$R1, $M3, $BD2", []> { 4119 let mayStore = 1; 4120 let AccessBytes = bytes; 4121} 4122 4123class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 4124 bits<5> bytes, AddressingMode mode = bdaddr20only> 4125 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4126 mnemonic#"\t$R1, $M3, $BD2", []> { 4127 let mayStore = 1; 4128 let AccessBytes = bytes; 4129} 4130 4131multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode, 4132 bits<16> rsyOpcode, RegisterOperand cls, 4133 bits<5> bytes> { 4134 let DispKey = mnemonic # cls in { 4135 let DispSize = "12" in 4136 def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 4137 let DispSize = "20" in 4138 def Y : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, 4139 bdaddr20pair>; 4140 } 4141} 4142 4143class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls> 4144 : InstRSLb<opcode, (outs), 4145 (ins cls:$R1, (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, 4146 imm32zx4:$M3), 4147 mnemonic#"\t$R1, $BDL2, $M3", []> { 4148 let mayStore = 1; 4149} 4150 4151class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4152 bits<5> bytes> 4153 : InstVSI<opcode, (outs VR128:$V1), 4154 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 4155 mnemonic#"\t$V1, $BD2, $I3", 4156 [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> { 4157 let mayLoad = 1; 4158 let AccessBytes = bytes; 4159} 4160 4161class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 4162 ImmOpWithPattern index> 4163 : InstVRV<opcode, (outs), 4164 (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3), 4165 mnemonic#"\t$V1, $VBD2, $M3", []> { 4166 let mayStore = 1; 4167 let AccessBytes = bytes; 4168} 4169 4170class StoreBinaryVRX<string mnemonic, bits<16> opcode, 4171 SDPatternOperator operator, TypedReg tr, bits<5> bytes, 4172 ImmOpWithPattern index> 4173 : InstVRX<opcode, (outs), 4174 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3), 4175 mnemonic#"\t$V1, $XBD2, $M3", 4176 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> { 4177 let mayStore = 1; 4178 let AccessBytes = bytes; 4179} 4180 4181class MemoryBinarySSd<string mnemonic, bits<8> opcode, 4182 RegisterOperand cls> 4183 : InstSSd<opcode, (outs), 4184 (ins (bdraddr12only $B1, $D1, $R1):$RBD1, 4185 (bdaddr12only $B2, $D2):$BD2, cls:$R3), 4186 mnemonic#"\t$RBD1, $BD2, $R3", []>; 4187 4188class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator, 4189 RegisterOperand cls1, RegisterOperand cls2> 4190 : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2), 4191 mnemonic#"\t$R1, $R2", 4192 [(set CC, (operator cls1:$R1, cls2:$R2))]> { 4193 let OpKey = mnemonic#cls1; 4194 let OpType = "reg"; 4195 let isCompare = 1; 4196} 4197 4198class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4199 RegisterOperand cls1, RegisterOperand cls2> 4200 : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2), 4201 mnemonic#"\t$R1, $R2", 4202 [(set CC, (operator cls1:$R1, cls2:$R2))]> { 4203 let OpKey = mnemonic#cls1; 4204 let OpType = "reg"; 4205 let isCompare = 1; 4206} 4207 4208class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator, 4209 RegisterOperand cls, ImmOpWithPattern imm> 4210 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2), 4211 mnemonic#"\t$R1, $I2", 4212 [(set CC, (operator cls:$R1, imm:$I2))]> { 4213 let isCompare = 1; 4214} 4215 4216class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator, 4217 RegisterOperand cls, ImmOpWithPattern imm> 4218 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2), 4219 mnemonic#"\t$R1, $I2", 4220 [(set CC, (operator cls:$R1, imm:$I2))]> { 4221 let isCompare = 1; 4222} 4223 4224class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator, 4225 RegisterOperand cls, SDPatternOperator load> 4226 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2), 4227 mnemonic#"\t$R1, $RI2", 4228 [(set CC, (operator cls:$R1, (load pcrel32:$RI2)))]> { 4229 let isCompare = 1; 4230 let mayLoad = 1; 4231 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 4232 // However, BDXs have two extra operands and are therefore 6 units more 4233 // complex. 4234 let AddedComplexity = 7; 4235} 4236 4237class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator, 4238 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 4239 AddressingMode mode = bdxaddr12only> 4240 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 4241 mnemonic#"\t$R1, $XBD2", 4242 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 4243 let OpKey = mnemonic#"r"#cls; 4244 let OpType = "mem"; 4245 let isCompare = 1; 4246 let mayLoad = 1; 4247 let AccessBytes = bytes; 4248} 4249 4250class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4251 RegisterOperand cls, SDPatternOperator load, bits<5> bytes> 4252 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 4253 mnemonic#"\t$R1, $XBD2", 4254 [(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> { 4255 let OpKey = mnemonic#"r"#cls; 4256 let OpType = "mem"; 4257 let isCompare = 1; 4258 let mayLoad = 1; 4259 let AccessBytes = bytes; 4260 let M3 = 0; 4261} 4262 4263class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4264 RegisterOperand cls, SDPatternOperator load, bits<5> bytes, 4265 AddressingMode mode = bdxaddr20only> 4266 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 4267 mnemonic#"\t$R1, $XBD2", 4268 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 4269 let OpKey = mnemonic#"r"#cls; 4270 let OpType = "mem"; 4271 let isCompare = 1; 4272 let mayLoad = 1; 4273 let AccessBytes = bytes; 4274} 4275 4276multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode, 4277 SDPatternOperator operator, RegisterOperand cls, 4278 SDPatternOperator load, bits<5> bytes> { 4279 let DispKey = mnemonic # cls in { 4280 let DispSize = "12" in 4281 def "" : CompareRX<mnemonic, rxOpcode, operator, cls, 4282 load, bytes, bdxaddr12pair>; 4283 let DispSize = "20" in 4284 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls, 4285 load, bytes, bdxaddr20pair>; 4286 } 4287} 4288 4289class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 4290 bits<5> bytes, AddressingMode mode = bdaddr12only> 4291 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4292 mnemonic#"\t$R1, $M3, $BD2", []> { 4293 let mayLoad = 1; 4294 let AccessBytes = bytes; 4295} 4296 4297class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 4298 bits<5> bytes, AddressingMode mode = bdaddr20only> 4299 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4300 mnemonic#"\t$R1, $M3, $BD2", []> { 4301 let mayLoad = 1; 4302 let AccessBytes = bytes; 4303} 4304 4305multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 4306 RegisterOperand cls, bits<5> bytes> { 4307 let DispKey = mnemonic # cls in { 4308 let DispSize = "12" in 4309 def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 4310 let DispSize = "20" in 4311 def Y : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>; 4312 } 4313} 4314 4315class CompareSSb<string mnemonic, bits<8> opcode> 4316 : InstSSb<opcode, 4317 (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1, 4318 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2), 4319 mnemonic#"\t$BDL1, $BDL2", []> { 4320 let isCompare = 1; 4321 let mayLoad = 1; 4322} 4323 4324class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator, 4325 SDPatternOperator load, ImmOpWithPattern imm, 4326 AddressingMode mode = bdaddr12only> 4327 : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 4328 mnemonic#"\t$BD1, $I2", 4329 [(set CC, (operator (load mode:$BD1), imm:$I2))]> { 4330 let isCompare = 1; 4331 let mayLoad = 1; 4332} 4333 4334class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4335 SDPatternOperator load, ImmOpWithPattern imm> 4336 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 4337 mnemonic#"\t$BD1, $I2", 4338 [(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> { 4339 let isCompare = 1; 4340 let mayLoad = 1; 4341} 4342 4343class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4344 SDPatternOperator load, ImmOpWithPattern imm, 4345 AddressingMode mode = bdaddr20only> 4346 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2), 4347 mnemonic#"\t$BD1, $I2", 4348 [(set CC, (operator (load mode:$BD1), imm:$I2))]> { 4349 let isCompare = 1; 4350 let mayLoad = 1; 4351} 4352 4353multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode, 4354 SDPatternOperator operator, SDPatternOperator load, 4355 ImmOpWithPattern imm> { 4356 let DispKey = mnemonic in { 4357 let DispSize = "12" in 4358 def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>; 4359 let DispSize = "20" in 4360 def Y : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm, 4361 bdaddr20pair>; 4362 } 4363} 4364 4365class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4366 TypedReg tr, bits<4> type, string fp_mnemonic = ""> 4367 : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2), 4368 mnemonic#"\t$V1, $V2", 4369 [(set CC, (operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2)))]> { 4370 let isCompare = 1; 4371 let M3 = type; 4372 let M4 = 0; 4373 let M5 = 0; 4374 let OpKey = fp_mnemonic#!subst("VR", "FP", !cast<string>(tr.op)); 4375 let OpType = "reg"; 4376} 4377 4378class CompareVRRaGeneric<string mnemonic, bits<16> opcode> 4379 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3), 4380 mnemonic#"\t$V1, $V2, $M3", []> { 4381 let isCompare = 1; 4382 let M4 = 0; 4383 let M5 = 0; 4384} 4385 4386class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode> 4387 : InstVRRa<opcode, (outs), 4388 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4), 4389 mnemonic#"\t$V1, $V2, $M3, $M4", []> { 4390 let isCompare = 1; 4391 let M5 = 0; 4392} 4393 4394class CompareVRRh<string mnemonic, bits<16> opcode> 4395 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3), 4396 mnemonic#"\t$V1, $V2, $M3", []> { 4397 let isCompare = 1; 4398} 4399 4400class TestInherentS<string mnemonic, bits<16> opcode, 4401 SDPatternOperator operator> 4402 : InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> { 4403 let B2 = 0; 4404 let D2 = 0; 4405} 4406 4407class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4408 RegisterOperand cls> 4409 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2), 4410 mnemonic#"\t$R1, $XBD2", 4411 [(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> { 4412 let M3 = 0; 4413} 4414 4415class TestBinarySIL<string mnemonic, bits<16> opcode, 4416 SDPatternOperator operator, ImmOpWithPattern imm> 4417 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 4418 mnemonic#"\t$BD1, $I2", 4419 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>; 4420 4421class TestRSL<string mnemonic, bits<16> opcode> 4422 : InstRSLa<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1), 4423 mnemonic#"\t$BDL1", []> { 4424 let mayLoad = 1; 4425} 4426 4427class TestVRRg<string mnemonic, bits<16> opcode> 4428 : InstVRRg<opcode, (outs), (ins VR128:$V1), 4429 mnemonic#"\t$V1", []>; 4430 4431class SideEffectTernarySSc<string mnemonic, bits<8> opcode> 4432 : InstSSc<opcode, (outs), (ins (bdladdr12onlylen4 $B1, $D1, $L1):$BDL1, 4433 (shift12only $B2, $D2):$BD2, imm32zx4:$I3), 4434 mnemonic#"\t$BDL1, $BD2, $I3", []>; 4435 4436class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode, 4437 RegisterOperand cls1, RegisterOperand cls2, 4438 RegisterOperand cls3> 4439 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), 4440 mnemonic#"\t$R1, $R2, $R3", []> { 4441 let M4 = 0; 4442} 4443 4444class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode, 4445 RegisterOperand cls1, RegisterOperand cls2, 4446 RegisterOperand cls3> 4447 : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2), 4448 (ins cls1:$R1src, cls2:$R2src, cls3:$R3), 4449 mnemonic#"\t$R1, $R2, $R3", []> { 4450 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 4451 let DisableEncoding = "$R1src, $R2src"; 4452 let M4 = 0; 4453} 4454 4455class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode, 4456 RegisterOperand cls1, RegisterOperand cls2, 4457 RegisterOperand cls3> 4458 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3), 4459 mnemonic#"\t$R1, $R3, $R2", []> { 4460 let M4 = 0; 4461} 4462 4463class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode, 4464 RegisterOperand cls1, 4465 RegisterOperand cls2, 4466 RegisterOperand cls3> 4467 : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3), 4468 (ins cls1:$R1src, cls2:$R2src, cls3:$R3src), 4469 mnemonic#"\t$R1, $R3, $R2", []> { 4470 let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src"; 4471 let DisableEncoding = "$R1src, $R2src, $R3src"; 4472 let M4 = 0; 4473} 4474 4475class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode, 4476 RegisterOperand cls1, RegisterOperand cls2, 4477 ImmOpWithPattern imm> 4478 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3), 4479 mnemonic#"\t$R1, $R2, $M3", []>; 4480 4481multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode, 4482 RegisterOperand cls1, 4483 RegisterOperand cls2> { 4484 def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 4485 def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>; 4486} 4487 4488class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode, 4489 RegisterOperand cls1, RegisterOperand cls2, 4490 ImmOpWithPattern imm> 4491 : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), 4492 (ins cls1:$R1src, cls2:$R2src, imm:$M3), 4493 mnemonic#"\t$R1, $R2, $M3", []> { 4494 let Constraints = "$R1 = $R1src, $R2 = $R2src"; 4495 let DisableEncoding = "$R1src, $R2src"; 4496} 4497 4498multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode, 4499 RegisterOperand cls1, 4500 RegisterOperand cls2> { 4501 def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>; 4502 def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>; 4503} 4504 4505class SideEffectTernarySSF<string mnemonic, bits<12> opcode, 4506 RegisterOperand cls> 4507 : InstSSF<opcode, (outs), 4508 (ins (bdaddr12only $B1, $D1):$BD1, 4509 (bdaddr12only $B2, $D2):$BD2, cls:$R3), 4510 mnemonic#"\t$BD1, $BD2, $R3", []>; 4511 4512class TernaryRRFa<string mnemonic, bits<16> opcode, 4513 RegisterOperand cls1, RegisterOperand cls2, 4514 RegisterOperand cls3> 4515 : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4), 4516 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 4517 4518class TernaryRRFb<string mnemonic, bits<16> opcode, 4519 RegisterOperand cls1, RegisterOperand cls2, 4520 RegisterOperand cls3> 4521 : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3), 4522 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4), 4523 mnemonic#"\t$R1, $R3, $R2, $M4", []> { 4524 let Constraints = "$R1 = $R1src"; 4525 let DisableEncoding = "$R1src"; 4526} 4527 4528class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1, 4529 RegisterOperand cls2> 4530 : InstRRFe<opcode, (outs cls1:$R1), 4531 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4), 4532 mnemonic#"\t$R1, $M3, $R2, $M4", []>; 4533 4534class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4535 RegisterOperand cls1, RegisterOperand cls2> 4536 : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2), 4537 mnemonic#"\t$R1, $R3, $R2", 4538 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> { 4539 let OpKey = mnemonic#cls; 4540 let OpType = "reg"; 4541 let Constraints = "$R1 = $R1src"; 4542 let DisableEncoding = "$R1src"; 4543} 4544 4545class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls, 4546 bits<5> bytes, AddressingMode mode = bdaddr12only> 4547 : InstRSb<opcode, (outs cls:$R1), 4548 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4549 mnemonic#"\t$R1, $M3, $BD2", []> { 4550 4551 let Constraints = "$R1 = $R1src"; 4552 let DisableEncoding = "$R1src"; 4553 let mayLoad = 1; 4554 let AccessBytes = bytes; 4555} 4556 4557class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls, 4558 bits<5> bytes, AddressingMode mode = bdaddr20only> 4559 : InstRSYb<opcode, (outs cls:$R1), 4560 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2), 4561 mnemonic#"\t$R1, $M3, $BD2", []> { 4562 4563 let Constraints = "$R1 = $R1src"; 4564 let DisableEncoding = "$R1src"; 4565 let mayLoad = 1; 4566 let AccessBytes = bytes; 4567} 4568 4569multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 4570 RegisterOperand cls, bits<5> bytes> { 4571 let DispKey = mnemonic # cls in { 4572 let DispSize = "12" in 4573 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>; 4574 let DispSize = "20" in 4575 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>; 4576 } 4577} 4578 4579class SideEffectTernaryRS<string mnemonic, bits<8> opcode, 4580 RegisterOperand cls1, RegisterOperand cls2> 4581 : InstRSa<opcode, (outs), 4582 (ins cls1:$R1, cls2:$R3, (bdaddr12only $B2, $D2):$BD2), 4583 mnemonic#"\t$R1, $R3, $BD2", []>; 4584 4585class SideEffectTernaryRSY<string mnemonic, bits<16> opcode, 4586 RegisterOperand cls1, RegisterOperand cls2> 4587 : InstRSYa<opcode, (outs), 4588 (ins cls1:$R1, cls2:$R3, (bdaddr20only $B2, $D2):$BD2), 4589 mnemonic#"\t$R1, $R3, $BD2", []>; 4590 4591class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode, 4592 RegisterOperand cls1, RegisterOperand cls2> 4593 : InstRSa<opcode, (outs cls1:$R1, cls2:$R3), 4594 (ins cls1:$R1src, cls2:$R3src, (shift12only $B2, $D2):$BD2), 4595 mnemonic#"\t$R1, $R3, $BD2", []> { 4596 let Constraints = "$R1 = $R1src, $R3 = $R3src"; 4597 let DisableEncoding = "$R1src, $R3src"; 4598} 4599 4600class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode, 4601 RegisterOperand cls1, RegisterOperand cls2> 4602 : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3), 4603 (ins cls1:$R1src, cls2:$R3src, (shift20only $B2, $D2):$BD2), 4604 mnemonic#"\t$R1, $R3, $BD2", []> { 4605 let Constraints = "$R1 = $R1src, $R3 = $R3src"; 4606 let DisableEncoding = "$R1src, $R3src"; 4607} 4608 4609class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4610 RegisterOperand cls1, RegisterOperand cls2, 4611 SDPatternOperator load, bits<5> bytes> 4612 : InstRXF<opcode, (outs cls1:$R1), 4613 (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 4614 mnemonic#"\t$R1, $R3, $XBD2", 4615 [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, 4616 (load bdxaddr12only:$XBD2)))]> { 4617 let OpKey = mnemonic#"r"#cls; 4618 let OpType = "mem"; 4619 let Constraints = "$R1 = $R1src"; 4620 let DisableEncoding = "$R1src"; 4621 let mayLoad = 1; 4622 let AccessBytes = bytes; 4623} 4624 4625class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4626 TypedReg tr1, TypedReg tr2, ImmOpWithPattern imm, ImmOpWithPattern index> 4627 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3), 4628 mnemonic#"\t$V1, $I2, $M3", 4629 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4630 imm:$I2, index:$M3))]> { 4631 let Constraints = "$V1 = $V1src"; 4632 let DisableEncoding = "$V1src"; 4633} 4634 4635class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4636 TypedReg tr1, TypedReg tr2, bits<4> type> 4637 : InstVRId<opcode, (outs tr1.op:$V1), 4638 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 4639 mnemonic#"\t$V1, $V2, $V3, $I4", 4640 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4641 (tr2.vt tr2.op:$V3), 4642 imm32zx8_timm:$I4))]> { 4643 let M5 = type; 4644} 4645 4646class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4647 : InstVRIi<opcode, (outs VR128:$V1), 4648 (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4), 4649 mnemonic#"\t$V1, $R2, $I3, $M4", []>; 4650 4651class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4652 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or> 4653 : InstVRRa<opcode, (outs tr1.op:$V1), 4654 (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5), 4655 mnemonic#"\t$V1, $V2, $M4, $M5", 4656 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4657 imm32zx4_timm:$M4, 4658 imm32zx4_timm:$M5))], 4659 m4or> { 4660 let M3 = type; 4661} 4662 4663class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode> 4664 : InstVRRa<opcode, (outs VR128:$V1), 4665 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5), 4666 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>; 4667 4668class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4669 TypedReg tr1, TypedReg tr2, bits<4> type, 4670 SDPatternOperator m5mask, bits<4> m5or> 4671 : InstVRRb<opcode, (outs tr1.op:$V1), 4672 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5), 4673 mnemonic#"\t$V1, $V2, $V3, $M5", 4674 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4675 (tr2.vt tr2.op:$V3), 4676 m5mask:$M5))], 4677 m5or> { 4678 let M4 = type; 4679} 4680 4681// Declare a pair of instructions, one which sets CC and one which doesn't. 4682// The CC-setting form ends with "S" and sets the low bit of M5. 4683// Also create aliases to make use of M5 operand optional in assembler. 4684multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode, 4685 SDPatternOperator operator, 4686 SDPatternOperator operator_cc, 4687 TypedReg tr1, TypedReg tr2, bits<4> type, 4688 bits<4> modifier = 0> { 4689 def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type, 4690 imm32zx4even_timm, !and (modifier, 14)>; 4691 def : InstAlias<mnemonic#"\t$V1, $V2, $V3", 4692 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4693 tr2.op:$V3, 0)>; 4694 let Defs = [CC] in 4695 def S : TernaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 4696 imm32zx4even_timm, !add(!and (modifier, 14), 1)>; 4697 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3", 4698 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 4699 tr2.op:$V3, 0)>; 4700} 4701 4702multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> { 4703 let Defs = [CC] in 4704 def "" : InstVRRb<opcode, (outs VR128:$V1), 4705 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5), 4706 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>; 4707 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4", 4708 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4709 imm32zx4:$M4, 0)>; 4710} 4711 4712class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4713 TypedReg tr1, TypedReg tr2> 4714 : InstVRRc<opcode, (outs tr1.op:$V1), 4715 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4), 4716 mnemonic#"\t$V1, $V2, $V3, $M4", 4717 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4718 (tr2.vt tr2.op:$V3), 4719 imm32zx4_timm:$M4))]> { 4720 let M5 = 0; 4721 let M6 = 0; 4722} 4723 4724class TernaryVRRcFloat<string mnemonic, bits<16> opcode, 4725 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 4726 bits<4> type = 0, bits<4> m5 = 0> 4727 : InstVRRc<opcode, (outs tr1.op:$V1), 4728 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6), 4729 mnemonic#"\t$V1, $V2, $V3, $M6", 4730 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4731 (tr2.vt tr2.op:$V3), 4732 imm32zx4_timm:$M6))]> { 4733 let M4 = type; 4734 let M5 = m5; 4735} 4736 4737class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode> 4738 : InstVRRc<opcode, (outs VR128:$V1), 4739 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 4740 imm32zx4:$M6), 4741 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>; 4742 4743class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4744 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m6 = 0> 4745 : InstVRRd<opcode, (outs tr1.op:$V1), 4746 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 4747 mnemonic#"\t$V1, $V2, $V3, $V4", 4748 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4749 (tr2.vt tr2.op:$V3), 4750 (tr1.vt tr1.op:$V4)))]> { 4751 let M5 = type; 4752 let M6 = m6; 4753} 4754 4755class TernaryVRRdGeneric<string mnemonic, bits<16> opcode> 4756 : InstVRRd<opcode, (outs VR128:$V1), 4757 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5), 4758 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> { 4759 let M6 = 0; 4760} 4761 4762// Ternary operation where the assembler mnemonic has an extra operand to 4763// optionally allow specifying arbitrary M6 values. 4764multiclass TernaryExtraVRRd<string mnemonic, bits<16> opcode, 4765 SDPatternOperator operator, 4766 TypedReg tr1, TypedReg tr2, bits<4> type> { 4767 let M5 = type, Defs = [CC] in 4768 def "" : InstVRRd<opcode, (outs tr1.op:$V1), 4769 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6), 4770 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>; 4771 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3), 4772 (tr1.vt tr1.op:$V4)), 4773 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>; 4774 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 4775 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4776 tr2.op:$V3, tr1.op:$V4, 0)>; 4777} 4778 4779multiclass TernaryExtraVRRdGeneric<string mnemonic, bits<16> opcode> { 4780 let Defs = [CC] in 4781 def "" : InstVRRd<opcode, (outs VR128:$V1), 4782 (ins VR128:$V2, VR128:$V3, VR128:$V4, 4783 imm32zx4:$M5, imm32zx4:$M6), 4784 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4785 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5", 4786 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4787 VR128:$V4, imm32zx4:$M5, 0)>; 4788} 4789 4790class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4791 TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0, 4792 string fp_mnemonic = ""> 4793 : InstVRRe<opcode, (outs tr1.op:$V1), 4794 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4), 4795 mnemonic#"\t$V1, $V2, $V3, $V4", 4796 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4797 (tr2.vt tr2.op:$V3), 4798 (tr1.vt tr1.op:$V4)))]> { 4799 let M5 = m5; 4800 let M6 = type; 4801 let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op)); 4802 let OpType = "reg"; 4803} 4804 4805class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode> 4806 : InstVRRe<opcode, (outs VR128:$V1), 4807 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6), 4808 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4809 4810class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4811 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type> 4812 : InstVRSb<opcode, (outs tr1.op:$V1), 4813 (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2), 4814 mnemonic#"\t$V1, $R3, $BD2", 4815 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4816 cls:$R3, 4817 shift12only:$BD2))]> { 4818 let Constraints = "$V1 = $V1src"; 4819 let DisableEncoding = "$V1src"; 4820 let M4 = type; 4821} 4822 4823class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls> 4824 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, 4825 imm32zx4:$M3, imm32zx4:$M4), 4826 mnemonic#"\t$R1, $V2, $M3, $M4", []>; 4827 4828class TernaryVRRj<string mnemonic, bits<16> opcode> 4829 : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2, 4830 VR128:$V3, imm32zx4:$M4), 4831 mnemonic#"\t$V1, $V2, $V3, $M4", []>; 4832 4833class TernaryVRSbGeneric<string mnemonic, bits<16> opcode> 4834 : InstVRSb<opcode, (outs VR128:$V1), 4835 (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2, 4836 imm32zx4:$M4), 4837 mnemonic#"\t$V1, $R3, $BD2, $M4", []> { 4838 let Constraints = "$V1 = $V1src"; 4839 let DisableEncoding = "$V1src"; 4840} 4841 4842class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes, 4843 ImmOpWithPattern index> 4844 : InstVRV<opcode, (outs VR128:$V1), 4845 (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3), 4846 mnemonic#"\t$V1, $VBD2, $M3", []> { 4847 let Constraints = "$V1 = $V1src"; 4848 let DisableEncoding = "$V1src"; 4849 let mayLoad = 1; 4850 let AccessBytes = bytes; 4851} 4852 4853class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4854 TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index> 4855 : InstVRX<opcode, (outs tr1.op:$V1), 4856 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3), 4857 mnemonic#"\t$V1, $XBD2, $M3", 4858 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4859 bdxaddr12only:$XBD2, 4860 index:$M3))]> { 4861 let Constraints = "$V1 = $V1src"; 4862 let DisableEncoding = "$V1src"; 4863 let mayLoad = 1; 4864 let AccessBytes = bytes; 4865} 4866 4867class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4868 TypedReg tr1, TypedReg tr2, bits<4> type> 4869 : InstVRId<opcode, (outs tr1.op:$V1), 4870 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4), 4871 mnemonic#"\t$V1, $V2, $V3, $I4", 4872 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src), 4873 (tr2.vt tr2.op:$V2), 4874 (tr2.vt tr2.op:$V3), 4875 imm32zx8_timm:$I4))]> { 4876 let Constraints = "$V1 = $V1src"; 4877 let DisableEncoding = "$V1src"; 4878 let M5 = type; 4879} 4880 4881class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode> 4882 : InstVRId<opcode, (outs VR128:$V1), 4883 (ins VR128:$V1src, VR128:$V2, VR128:$V3, 4884 imm32zx8:$I4, imm32zx4:$M5), 4885 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> { 4886 let Constraints = "$V1 = $V1src"; 4887 let DisableEncoding = "$V1src"; 4888} 4889 4890class QuaternaryVRIf<string mnemonic, bits<16> opcode> 4891 : InstVRIf<opcode, (outs VR128:$V1), 4892 (ins VR128:$V2, VR128:$V3, 4893 imm32zx8:$I4, imm32zx4:$M5), 4894 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>; 4895 4896class QuaternaryVRIg<string mnemonic, bits<16> opcode> 4897 : InstVRIg<opcode, (outs VR128:$V1), 4898 (ins VR128:$V2, imm32zx8:$I3, 4899 imm32zx8:$I4, imm32zx4:$M5), 4900 mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>; 4901 4902class QuaternaryVRRd<string mnemonic, bits<16> opcode, 4903 SDPatternOperator operator, TypedReg tr1, TypedReg tr2, 4904 TypedReg tr3, TypedReg tr4, bits<4> type, 4905 SDPatternOperator m6mask = imm32zx4_timm, bits<4> m6or = 0> 4906 : InstVRRd<opcode, (outs tr1.op:$V1), 4907 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6), 4908 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", 4909 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2), 4910 (tr3.vt tr3.op:$V3), 4911 (tr4.vt tr4.op:$V4), 4912 m6mask:$M6))], 4913 m6or> { 4914 let M5 = type; 4915} 4916 4917class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode> 4918 : InstVRRd<opcode, (outs VR128:$V1), 4919 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6), 4920 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>; 4921 4922// Declare a pair of instructions, one which sets CC and one which doesn't. 4923// The CC-setting form ends with "S" and sets the low bit of M6. 4924// Also create aliases to make use of M6 operand optional in assembler. 4925multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode, 4926 SDPatternOperator operator, 4927 SDPatternOperator operator_cc, 4928 TypedReg tr1, TypedReg tr2, bits<4> type, 4929 bits<4> modifier = 0> { 4930 def "" : QuaternaryVRRd<mnemonic, opcode, operator, 4931 tr1, tr2, tr2, tr2, type, 4932 imm32zx4even_timm, !and (modifier, 14)>; 4933 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4", 4934 (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 4935 tr2.op:$V3, tr2.op:$V4, 0)>; 4936 let Defs = [CC] in 4937 def S : QuaternaryVRRd<mnemonic#"s", opcode, operator_cc, 4938 tr1, tr2, tr2, tr2, type, 4939 imm32zx4even_timm, !add (!and (modifier, 14), 1)>; 4940 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4", 4941 (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2, 4942 tr2.op:$V3, tr2.op:$V4, 0)>; 4943} 4944 4945multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> { 4946 let Defs = [CC] in 4947 def "" : QuaternaryVRRdGeneric<mnemonic, opcode>; 4948 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5", 4949 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3, 4950 VR128:$V4, imm32zx4_timm:$M5, 0)>; 4951} 4952 4953class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode, 4954 RegisterOperand cls1, RegisterOperand cls2, 4955 RegisterOperand cls3> 4956 : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), 4957 mnemonic#"\t$R1, $R2, $R3, $M4", []>; 4958 4959multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode, 4960 RegisterOperand cls1, 4961 RegisterOperand cls2, 4962 RegisterOperand cls3> { 4963 def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 4964 def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>; 4965 def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>; 4966} 4967 4968class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode, 4969 RegisterOperand cls1, RegisterOperand cls2, 4970 RegisterOperand cls3> 4971 : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4), 4972 mnemonic#"\t$R1, $R3, $R2, $M4", []>; 4973 4974multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode, 4975 RegisterOperand cls1, 4976 RegisterOperand cls2, 4977 RegisterOperand cls3> { 4978 def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; 4979 def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>; 4980} 4981 4982class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode, 4983 RegisterOperand cls> 4984 : InstSSe<opcode, (outs), 4985 (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3, 4986 (bdaddr12only $B4, $D4):$BD4), 4987 mnemonic#"\t$R1, $BD2, $R3, $BD4", []>; 4988 4989class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 4990 RegisterOperand cls, AddressingMode mode = bdaddr20only> 4991 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2), 4992 mnemonic#"\t$R1, $R3, $BD2", 4993 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> { 4994 let mayLoad = 1; 4995 let mayStore = 1; 4996} 4997 4998class CmpSwapRRE<string mnemonic, bits<16> opcode, 4999 RegisterOperand cls1, RegisterOperand cls2> 5000 : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2), 5001 mnemonic#"\t$R1, $R2", []> { 5002 let Constraints = "$R1 = $R1src"; 5003 let DisableEncoding = "$R1src"; 5004 let mayLoad = 1; 5005 let mayStore = 1; 5006} 5007 5008class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator, 5009 RegisterOperand cls, AddressingMode mode = bdaddr12only> 5010 : InstRSa<opcode, (outs cls:$R1), 5011 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2), 5012 mnemonic#"\t$R1, $R3, $BD2", 5013 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 5014 let Constraints = "$R1 = $R1src"; 5015 let DisableEncoding = "$R1src"; 5016 let mayLoad = 1; 5017 let mayStore = 1; 5018} 5019 5020class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator, 5021 RegisterOperand cls, AddressingMode mode = bdaddr20only> 5022 : InstRSYa<opcode, (outs cls:$R1), 5023 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2), 5024 mnemonic#"\t$R1, $R3, $BD2", 5025 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> { 5026 let Constraints = "$R1 = $R1src"; 5027 let DisableEncoding = "$R1src"; 5028 let mayLoad = 1; 5029 let mayStore = 1; 5030} 5031 5032multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode, 5033 SDPatternOperator operator, RegisterOperand cls> { 5034 let DispKey = mnemonic # cls in { 5035 let DispSize = "12" in 5036 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>; 5037 let DispSize = "20" in 5038 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>; 5039 } 5040} 5041 5042class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1, 5043 RegisterOperand cls2, bits<8> I3Or = 0, bits<8> I4Or = 0> 5044 : InstRIEf<opcode, (outs cls1:$R1), 5045 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 5046 imm32zx8:$I5), 5047 mnemonic#"\t$R1, $R2, $I3, $I4, $I5", [], I3Or, I4Or> { 5048 let Constraints = "$R1 = $R1src"; 5049 let DisableEncoding = "$R1src"; 5050} 5051 5052class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator> 5053 : InstRXYb<opcode, (outs), 5054 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2), 5055 mnemonic#"\t$M1, $XBD2", 5056 [(operator imm32zx4_timm:$M1, bdxaddr20only:$XBD2)]>; 5057 5058class PrefetchRILPC<string mnemonic, bits<12> opcode, 5059 SDPatternOperator operator> 5060 : InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2), 5061 mnemonic#"\t$M1, $RI2", 5062 [(operator imm32zx4_timm:$M1, pcrel32:$RI2)]> { 5063 // We want PC-relative addresses to be tried ahead of BD and BDX addresses. 5064 // However, BDXs have two extra operands and are therefore 6 units more 5065 // complex. 5066 let AddedComplexity = 7; 5067} 5068 5069class BranchPreloadSMI<string mnemonic, bits<8> opcode> 5070 : InstSMI<opcode, (outs), 5071 (ins imm32zx4:$M1, brtarget16bpp:$RI2, 5072 (bdaddr12only $B3, $D3):$BD3), 5073 mnemonic#"\t$M1, $RI2, $BD3", []>; 5074 5075class BranchPreloadMII<string mnemonic, bits<8> opcode> 5076 : InstMII<opcode, (outs), 5077 (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3), 5078 mnemonic#"\t$M1, $RI2, $RI3", []>; 5079 5080//===----------------------------------------------------------------------===// 5081// Pseudo instructions 5082//===----------------------------------------------------------------------===// 5083// 5084// Convenience instructions that get lowered to real instructions 5085// by either SystemZTargetLowering::EmitInstrWithCustomInserter() 5086// or SystemZInstrInfo::expandPostRAPseudo(). 5087// 5088//===----------------------------------------------------------------------===// 5089 5090class Pseudo<dag outs, dag ins, list<dag> pattern> 5091 : InstSystemZ<0, outs, ins, "", pattern> { 5092 let isPseudo = 1; 5093 let isCodeGenOnly = 1; 5094} 5095 5096// Like UnaryRI, but expanded after RA depending on the choice of register. 5097class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 5098 ImmOpWithPattern imm> 5099 : Pseudo<(outs cls:$R1), (ins imm:$I2), 5100 [(set cls:$R1, (operator imm:$I2))]>; 5101 5102// Like UnaryRXY, but expanded after RA depending on the choice of register. 5103class UnaryRXYPseudo<string key, SDPatternOperator operator, 5104 RegisterOperand cls, bits<5> bytes, 5105 AddressingMode mode = bdxaddr20only> 5106 : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2), 5107 [(set cls:$R1, (operator mode:$XBD2))]> { 5108 let OpKey = key#"r"#cls; 5109 let OpType = "mem"; 5110 let mayLoad = 1; 5111 let Has20BitOffset = 1; 5112 let HasIndex = 1; 5113 let AccessBytes = bytes; 5114} 5115 5116// Like UnaryRR, but expanded after RA depending on the choice of registers. 5117class UnaryRRPseudo<string key, SDPatternOperator operator, 5118 RegisterOperand cls1, RegisterOperand cls2> 5119 : Pseudo<(outs cls1:$R1), (ins cls2:$R2), 5120 [(set cls1:$R1, (operator cls2:$R2))]> { 5121 let OpKey = key#cls1; 5122 let OpType = "reg"; 5123} 5124 5125// Like BinaryRI, but expanded after RA depending on the choice of register. 5126class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls, 5127 ImmOpWithPattern imm> 5128 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2), 5129 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5130 let Constraints = "$R1 = $R1src"; 5131} 5132 5133// Like BinaryRIE, but expanded after RA depending on the choice of register. 5134class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls, 5135 ImmOpWithPattern imm> 5136 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2), 5137 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>; 5138 5139// Like BinaryRIAndK, but expanded after RA depending on the choice of register. 5140multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator, 5141 RegisterOperand cls, ImmOpWithPattern imm> { 5142 let NumOpsKey = key in { 5143 let NumOpsValue = "3" in 5144 def K : BinaryRIEPseudo<operator, cls, imm>, 5145 Requires<[FeatureHighWord, FeatureDistinctOps]>; 5146 let NumOpsValue = "2" in 5147 def "" : BinaryRIPseudo<operator, cls, imm>, 5148 Requires<[FeatureHighWord]>; 5149 } 5150} 5151 5152// A pseudo that is used during register allocation when folding a memory 5153// operand. The 3-address register instruction with a spilled source cannot 5154// be converted directly to a target 2-address reg/mem instruction. 5155// Mapping: <INSN>R -> MemFoldPseudo -> <INSN> 5156class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes, 5157 AddressingMode mode> 5158 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> { 5159 let OpKey = !subst("mscrk", "msrkc", 5160 !subst("msgcrk", "msgrkc", 5161 mnemonic#"rk"#cls)); 5162 let OpType = "mem"; 5163 let MemKey = mnemonic#cls; 5164 let MemType = "pseudo"; 5165 let mayLoad = 1; 5166 let AccessBytes = bytes; 5167 let HasIndex = 1; 5168 let hasNoSchedulingInfo = 1; 5169} 5170 5171// Same as MemFoldPseudo but for mapping a W... vector instruction 5172class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes, 5173 AddressingMode mode> 5174 : MemFoldPseudo<mnemonic, cls, bytes, mode> { 5175 let OpKey = mnemonic#"r"#"MemFold"#cls; 5176} 5177 5178class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes, 5179 AddressingMode mode> 5180 : Pseudo<(outs cls:$R1), 5181 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> { 5182 let OpKey = mnemonic#"r"#"MemFold"#cls; 5183 let OpType = "mem"; 5184 let MemKey = mnemonic#cls; 5185 let MemType = "pseudo"; 5186 let mayLoad = 1; 5187 let AccessBytes = bytes; 5188 let HasIndex = 1; 5189 let hasNoSchedulingInfo = 1; 5190} 5191 5192// Same as MemFoldPseudo but for Load On Condition with CC operands. 5193class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes, 5194 AddressingMode mode> 5195 : Pseudo<(outs cls:$R1), 5196 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> { 5197 let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls; 5198 let OpType = "mem"; 5199 let MemKey = mnemonic#cls; 5200 let MemType = "pseudo"; 5201 let mayLoad = 1; 5202 let AccessBytes = bytes; 5203 let hasNoSchedulingInfo = 1; 5204} 5205 5206// Like CompareRI, but expanded after RA depending on the choice of register. 5207class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls, 5208 ImmOpWithPattern imm> 5209 : Pseudo<(outs), (ins cls:$R1, imm:$I2), 5210 [(set CC, (operator cls:$R1, imm:$I2))]> { 5211 let isCompare = 1; 5212} 5213 5214// Like CompareRXY, but expanded after RA depending on the choice of register. 5215class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 5216 SDPatternOperator load, bits<5> bytes, 5217 AddressingMode mode = bdxaddr20only> 5218 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 5219 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> { 5220 let mayLoad = 1; 5221 let Has20BitOffset = 1; 5222 let HasIndex = 1; 5223 let AccessBytes = bytes; 5224} 5225 5226// Like TestBinarySIL, but expanded later. 5227class TestBinarySILPseudo<SDPatternOperator operator, ImmOpWithPattern imm> 5228 : Pseudo<(outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2), 5229 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>; 5230 5231// Like CondBinaryRRF, but expanded after RA depending on the choice of 5232// register. 5233class CondBinaryRRFPseudo<string mnemonic, RegisterOperand cls1, 5234 RegisterOperand cls2> 5235 : Pseudo<(outs cls1:$R1), 5236 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3), 5237 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src, 5238 cond4:$valid, cond4:$M3))]> { 5239 let Constraints = "$R1 = $R1src"; 5240 let DisableEncoding = "$R1src"; 5241 let CCMaskLast = 1; 5242 let NumOpsKey = !subst("loc", "sel", mnemonic); 5243 let NumOpsValue = "2"; 5244 let OpKey = mnemonic#cls1; 5245 let OpType = "reg"; 5246} 5247 5248// Like CondBinaryRRFa, but expanded after RA depending on the choice of 5249// register. 5250class CondBinaryRRFaPseudo<string mnemonic, RegisterOperand cls1, 5251 RegisterOperand cls2, RegisterOperand cls3> 5252 : Pseudo<(outs cls1:$R1), 5253 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4), 5254 [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3, 5255 cond4:$valid, cond4:$M4))]> { 5256 let CCMaskLast = 1; 5257 let NumOpsKey = mnemonic; 5258 let NumOpsValue = "3"; 5259 let OpKey = mnemonic#cls1; 5260 let OpType = "reg"; 5261} 5262 5263// Like CondBinaryRIE, but expanded after RA depending on the choice of 5264// register. 5265class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm> 5266 : Pseudo<(outs cls:$R1), 5267 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3), 5268 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src, 5269 cond4:$valid, cond4:$M3))]> { 5270 let Constraints = "$R1 = $R1src"; 5271 let DisableEncoding = "$R1src"; 5272 let CCMaskLast = 1; 5273} 5274 5275// Like CondUnaryRSY, but expanded after RA depending on the choice of 5276// register. 5277class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator, 5278 RegisterOperand cls, bits<5> bytes, 5279 AddressingMode mode = bdaddr20only> 5280 : Pseudo<(outs cls:$R1), 5281 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), 5282 [(set cls:$R1, 5283 (z_select_ccmask (operator mode:$BD2), cls:$R1src, 5284 cond4:$valid, cond4:$R3))]> { 5285 let Constraints = "$R1 = $R1src"; 5286 let DisableEncoding = "$R1src"; 5287 let mayLoad = 1; 5288 let AccessBytes = bytes; 5289 let CCMaskLast = 1; 5290 let OpKey = mnemonic#"r"#cls; 5291 let OpType = "mem"; 5292 let MemKey = mnemonic#cls; 5293 let MemType = "target"; 5294} 5295 5296// Like CondStoreRSY, but expanded after RA depending on the choice of 5297// register. 5298class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes, 5299 AddressingMode mode = bdaddr20only> 5300 : Pseudo<(outs), 5301 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> { 5302 let mayStore = 1; 5303 let AccessBytes = bytes; 5304 let CCMaskLast = 1; 5305} 5306 5307// Like StoreRXY, but expanded after RA depending on the choice of register. 5308class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls, 5309 bits<5> bytes, AddressingMode mode = bdxaddr20only> 5310 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2), 5311 [(operator cls:$R1, mode:$XBD2)]> { 5312 let mayStore = 1; 5313 let Has20BitOffset = 1; 5314 let HasIndex = 1; 5315 let AccessBytes = bytes; 5316} 5317 5318// Like RotateSelectRIEf, but expanded after RA depending on the choice 5319// of registers. 5320class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2> 5321 : Pseudo<(outs cls1:$R1), 5322 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 5323 imm32zx8:$I5), 5324 []> { 5325 let Constraints = "$R1 = $R1src"; 5326 let DisableEncoding = "$R1src"; 5327} 5328 5329// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is 5330// the value of the PSW's 2-bit condition code field. 5331class SelectWrapper<ValueType vt, RegisterOperand cls> 5332 : Pseudo<(outs cls:$dst), 5333 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc), 5334 [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2, 5335 imm32zx4_timm:$valid, imm32zx4_timm:$cc))]> { 5336 let usesCustomInserter = 1; 5337 let hasNoSchedulingInfo = 1; 5338 let Uses = [CC]; 5339} 5340 5341// Stores $new to $addr if $cc is true ("" case) or false (Inv case). 5342multiclass CondStores<RegisterOperand cls, SDPatternOperator store, 5343 SDPatternOperator load, AddressingMode mode> { 5344 let Uses = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1, 5345 mayLoad = 1, mayStore = 1 in { 5346 def "" : Pseudo<(outs), 5347 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 5348 [(store (z_select_ccmask cls:$new, (load mode:$addr), 5349 imm32zx4_timm:$valid, imm32zx4_timm:$cc), 5350 mode:$addr)]>; 5351 def Inv : Pseudo<(outs), 5352 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc), 5353 [(store (z_select_ccmask (load mode:$addr), cls:$new, 5354 imm32zx4_timm:$valid, imm32zx4_timm:$cc), 5355 mode:$addr)]>; 5356 } 5357} 5358 5359// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation. PAT and OPERAND 5360// describe the second (non-memory) operand. 5361class AtomicLoadWBinary<SDPatternOperator operator, dag pat, 5362 DAGOperand operand> 5363 : Pseudo<(outs GR32:$dst), 5364 (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift, 5365 ADDR32:$negbitshift, uimm32:$bitsize), 5366 [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift, 5367 ADDR32:$negbitshift, uimm32:$bitsize))]> { 5368 let Defs = [CC]; 5369 let Has20BitOffset = 1; 5370 let mayLoad = 1; 5371 let mayStore = 1; 5372 let usesCustomInserter = 1; 5373 let hasNoSchedulingInfo = 1; 5374} 5375 5376// Specializations of AtomicLoadWBinary. 5377class AtomicLoadWBinaryReg<SDPatternOperator operator> 5378 : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>; 5379class AtomicLoadWBinaryImm<SDPatternOperator operator, ImmOpWithPattern imm> 5380 : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>; 5381 5382// A pseudo instruction that is a direct alias of a real instruction. 5383// These aliases are used in cases where a particular register operand is 5384// fixed or where the same instruction is used with different register sizes. 5385// The size parameter is the size in bytes of the associated real instruction. 5386class Alias<int size, dag outs, dag ins, list<dag> pattern> 5387 : InstSystemZ<size, outs, ins, "", pattern> { 5388 let isPseudo = 1; 5389 let isCodeGenOnly = 1; 5390} 5391 5392class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2> 5393 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>; 5394 5395// An alias of a UnaryVRR*, but with different register sizes. 5396class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2> 5397 : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2), 5398 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>; 5399 5400// An alias of a UnaryVRX, but with different register sizes. 5401class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr, 5402 AddressingMode mode = bdxaddr12only> 5403 : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2), 5404 [(set (tr.vt tr.op:$V1), (operator mode:$XBD2))]>; 5405 5406// An alias of a StoreVRX, but with different register sizes. 5407class StoreAliasVRX<SDPatternOperator operator, TypedReg tr, 5408 AddressingMode mode = bdxaddr12only> 5409 : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2), 5410 [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>; 5411 5412// An alias of a BinaryRI, but with different register sizes. 5413class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls, 5414 ImmOpWithPattern imm> 5415 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 5416 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5417 let Constraints = "$R1 = $R1src"; 5418} 5419 5420// An alias of a BinaryRIL, but with different register sizes. 5421class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls, 5422 ImmOpWithPattern imm> 5423 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2), 5424 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> { 5425 let Constraints = "$R1 = $R1src"; 5426} 5427 5428// An alias of a BinaryVRRf, but with different register sizes. 5429class BinaryAliasVRRf<RegisterOperand cls> 5430 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>; 5431 5432// An alias of a CompareRI, but with different register sizes. 5433class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls, 5434 ImmOpWithPattern imm> 5435 : Alias<4, (outs), (ins cls:$R1, imm:$I2), 5436 [(set CC, (operator cls:$R1, imm:$I2))]> { 5437 let isCompare = 1; 5438} 5439 5440// An alias of a RotateSelectRIEf, but with different register sizes. 5441class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2> 5442 : Alias<6, (outs cls1:$R1), 5443 (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4, 5444 imm32zx8:$I5), []> { 5445 let Constraints = "$R1 = $R1src"; 5446} 5447 5448class MemsetPseudo<DAGOperand lenop, DAGOperand byteop> 5449 : Pseudo<(outs), (ins bdaddr12only:$dest, lenop:$length, byteop:$B), 5450 [(z_memset_mvc bdaddr12only:$dest, lenop:$length, byteop:$B)]> { 5451 let Defs = [CC]; 5452 let mayLoad = 1; 5453 let mayStore = 1; 5454 let usesCustomInserter = 1; 5455 let hasNoSchedulingInfo = 1; 5456} 5457 5458//===----------------------------------------------------------------------===// 5459// Multiclasses that emit both real and pseudo instructions 5460//===----------------------------------------------------------------------===// 5461 5462multiclass BinaryRXYAndPseudo<string mnemonic, bits<16> opcode, 5463 SDPatternOperator operator, RegisterOperand cls, 5464 SDPatternOperator load, bits<5> bytes, 5465 AddressingMode mode = bdxaddr20only> { 5466 def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> { 5467 let MemKey = mnemonic#cls; 5468 let MemType = "target"; 5469 } 5470 let Has20BitOffset = 1 in 5471 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, mode>; 5472} 5473 5474multiclass BinaryRXPairAndPseudo<string mnemonic, bits<8> rxOpcode, 5475 bits<16> rxyOpcode, SDPatternOperator operator, 5476 RegisterOperand cls, 5477 SDPatternOperator load, bits<5> bytes> { 5478 let DispKey = mnemonic # cls in { 5479 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes, 5480 bdxaddr12pair> { 5481 let DispSize = "12"; 5482 let MemKey = mnemonic#cls; 5483 let MemType = "target"; 5484 } 5485 let DispSize = "20" in 5486 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, 5487 bytes, bdxaddr20pair>; 5488 } 5489 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>; 5490} 5491 5492multiclass BinaryRXEAndPseudo<string mnemonic, bits<16> opcode, 5493 SDPatternOperator operator, RegisterOperand cls, 5494 SDPatternOperator load, bits<5> bytes> { 5495 def "" : BinaryRXE<mnemonic, opcode, operator, cls, load, bytes> { 5496 let MemKey = mnemonic#cls; 5497 let MemType = "target"; 5498 } 5499 def _MemFoldPseudo : MemFoldPseudo_FP<mnemonic, cls, bytes, bdxaddr12pair>; 5500} 5501 5502multiclass TernaryRXFAndPseudo<string mnemonic, bits<16> opcode, 5503 SDPatternOperator operator, RegisterOperand cls1, 5504 RegisterOperand cls2, SDPatternOperator load, 5505 bits<5> bytes> { 5506 def "" : TernaryRXF<mnemonic, opcode, operator, cls1, cls2, load, bytes> { 5507 let MemKey = mnemonic#cls1; 5508 let MemType = "target"; 5509 } 5510 def _MemFoldPseudo : MemFoldPseudo_FPTern<mnemonic, cls1, bytes, bdxaddr12pair>; 5511} 5512 5513multiclass CondUnaryRSYPairAndMemFold<string mnemonic, bits<16> opcode, 5514 SDPatternOperator operator, 5515 RegisterOperand cls, bits<5> bytes, 5516 AddressingMode mode = bdaddr20only> { 5517 defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>; 5518 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>; 5519} 5520 5521multiclass CondUnaryRSYPseudoAndMemFold<string mnemonic, 5522 SDPatternOperator operator, 5523 RegisterOperand cls, bits<5> bytes, 5524 AddressingMode mode = bdaddr20only> { 5525 def "" : CondUnaryRSYPseudo<mnemonic, operator, cls, bytes, mode>; 5526 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>; 5527} 5528 5529// Define an instruction that operates on two fixed-length blocks of memory, 5530// and associated pseudo instructions for operating on blocks of any size. 5531// There are two pseudos for the different cases of when the length is 5532// constant or variable. The length operand of a pseudo is actually one less 5533// than the intended number of bytes, since the register case needs to use an 5534// EXRL with a target instruction that adds one to the length always. 5535multiclass MemorySS<string mnemonic, bits<8> opcode, SDPatternOperator memop> { 5536 def "" : SideEffectBinarySSa<mnemonic, opcode>; 5537 let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [CC] in { 5538 def Imm : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5539 imm64:$length), 5540 [(memop bdaddr12only:$dest, bdaddr12only:$src, 5541 imm64:$length)]>; 5542 def Reg : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5543 ADDR64:$length), 5544 [(memop bdaddr12only:$dest, bdaddr12only:$src, 5545 ADDR64:$length)]>; 5546 } 5547} 5548 5549// The same, but setting a CC result as comparison operator. 5550multiclass CompareMemorySS<string mnemonic, bits<8> opcode, 5551 SDPatternOperator memop> { 5552 def "" : SideEffectBinarySSa<mnemonic, opcode>; 5553 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 5554 def Imm : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5555 imm64:$length), 5556 [(set CC, (memop bdaddr12only:$dest, bdaddr12only:$src, 5557 imm64:$length))]>; 5558 def Reg : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src, 5559 ADDR64:$length), 5560 [(set CC, (memop bdaddr12only:$dest, bdaddr12only:$src, 5561 ADDR64:$length))]>; 5562 } 5563} 5564 5565// Define an instruction that operates on two strings, both terminated 5566// by the character in R0. The instruction processes a CPU-determinated 5567// number of bytes at a time and sets CC to 3 if the instruction needs 5568// to be repeated. Also define a pseudo instruction that represents 5569// the full loop (the main instruction plus the branch on CC==3). 5570multiclass StringRRE<string mnemonic, bits<16> opcode, 5571 SDPatternOperator operator> { 5572 let Uses = [R0L] in 5573 def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>; 5574 let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 5575 def Loop : Pseudo<(outs GR64:$end), 5576 (ins GR64:$start1, GR64:$start2, GR32:$char), 5577 [(set GR64:$end, (operator GR64:$start1, GR64:$start2, 5578 GR32:$char))]>; 5579} 5580