xref: /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZInstrFormats.td (revision 19261079b74319502c6ffa1249920079f0f69a72)
1//==- SystemZInstrFormats.td - SystemZ Instruction Formats --*- tablegen -*-==//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10// Basic SystemZ instruction definition
11//===----------------------------------------------------------------------===//
12
13class InstSystemZ<int size, dag outs, dag ins, string asmstr,
14                  list<dag> pattern> : Instruction {
15  let Namespace = "SystemZ";
16
17  dag OutOperandList = outs;
18  dag InOperandList = ins;
19  let Size = size;
20  let Pattern = pattern;
21  let AsmString = asmstr;
22
23  let hasSideEffects = 0;
24  let mayLoad = 0;
25  let mayStore = 0;
26
27  // Some instructions come in pairs, one having a 12-bit displacement
28  // and the other having a 20-bit displacement.  Both instructions in
29  // the pair have the same DispKey and their DispSizes are "12" and "20"
30  // respectively.
31  string DispKey = "";
32  string DispSize = "none";
33
34  // Many register-based <INSN>R instructions have a memory-based <INSN>
35  // counterpart.  OpKey uniquely identifies <INSN>R, while OpType is
36  // "reg" for <INSN>R and "mem" for <INSN>.
37  string OpKey = "";
38  string OpType = "none";
39
40  // MemKey identifies a targe reg-mem opcode, while MemType can be either
41  // "pseudo" or "target". This is used to map a pseduo memory instruction to
42  // its corresponding target opcode. See comment at MemFoldPseudo.
43  string MemKey = "";
44  string MemType = "none";
45
46  // Many distinct-operands instructions have older 2-operand equivalents.
47  // NumOpsKey uniquely identifies one of these 2-operand and 3-operand pairs,
48  // with NumOpsValue being "2" or "3" as appropriate.
49  string NumOpsKey = "";
50  string NumOpsValue = "none";
51
52  // True if this instruction is a simple D(X,B) load of a register
53  // (with no sign or zero extension).
54  bit SimpleBDXLoad = 0;
55
56  // True if this instruction is a simple D(X,B) store of a register
57  // (with no truncation).
58  bit SimpleBDXStore = 0;
59
60  // True if this instruction has a 20-bit displacement field.
61  bit Has20BitOffset = 0;
62
63  // True if addresses in this instruction have an index register.
64  bit HasIndex = 0;
65
66  // True if this is a 128-bit pseudo instruction that combines two 64-bit
67  // operations.
68  bit Is128Bit = 0;
69
70  // The access size of all memory operands in bytes, or 0 if not known.
71  bits<5> AccessBytes = 0;
72
73  // If the instruction sets CC to a useful value, this gives the mask
74  // of all possible CC results.  The mask has the same form as
75  // SystemZ::CCMASK_*.
76  bits<4> CCValues = 0;
77
78  // The subset of CCValues that have the same meaning as they would after a
79  // comparison of the first operand against zero. "Logical" instructions
80  // leave this blank as they set CC in a different way.
81  bits<4> CompareZeroCCMask = 0;
82
83  // True if the instruction is conditional and if the CC mask operand
84  // comes first (as for BRC, etc.).
85  bit CCMaskFirst = 0;
86
87  // Similar, but true if the CC mask operand comes last (as for LOC, etc.).
88  bit CCMaskLast = 0;
89
90  // True if the instruction is the "logical" rather than "arithmetic" form,
91  // in cases where a distinction exists. Except for logical compares, if the
92  // instruction sets this flag along with a non-zero CCValues field, it is
93  // assumed to set CC to either CCMASK_LOGICAL_ZERO or
94  // CCMASK_LOGICAL_NONZERO.
95  bit IsLogical = 0;
96
97  // True if the (add or sub) instruction sets CC like a compare of the
98  // result against zero, but only if the 'nsw' flag is set.
99  bit CCIfNoSignedWrap = 0;
100
101  let TSFlags{0}     = SimpleBDXLoad;
102  let TSFlags{1}     = SimpleBDXStore;
103  let TSFlags{2}     = Has20BitOffset;
104  let TSFlags{3}     = HasIndex;
105  let TSFlags{4}     = Is128Bit;
106  let TSFlags{9-5}   = AccessBytes;
107  let TSFlags{13-10} = CCValues;
108  let TSFlags{17-14} = CompareZeroCCMask;
109  let TSFlags{18}    = CCMaskFirst;
110  let TSFlags{19}    = CCMaskLast;
111  let TSFlags{20}    = IsLogical;
112  let TSFlags{21}    = CCIfNoSignedWrap;
113}
114
115//===----------------------------------------------------------------------===//
116// Mappings between instructions
117//===----------------------------------------------------------------------===//
118
119// Return the version of an instruction that has an unsigned 12-bit
120// displacement.
121def getDisp12Opcode : InstrMapping {
122  let FilterClass = "InstSystemZ";
123  let RowFields = ["DispKey"];
124  let ColFields = ["DispSize"];
125  let KeyCol = ["20"];
126  let ValueCols = [["12"]];
127}
128
129// Return the version of an instruction that has a signed 20-bit displacement.
130def getDisp20Opcode : InstrMapping {
131  let FilterClass = "InstSystemZ";
132  let RowFields = ["DispKey"];
133  let ColFields = ["DispSize"];
134  let KeyCol = ["12"];
135  let ValueCols = [["20"]];
136}
137
138// Return the memory form of a register instruction. Note that this may
139// return a MemFoldPseudo instruction (see below).
140def getMemOpcode : InstrMapping {
141  let FilterClass = "InstSystemZ";
142  let RowFields = ["OpKey"];
143  let ColFields = ["OpType"];
144  let KeyCol = ["reg"];
145  let ValueCols = [["mem"]];
146}
147
148// Return the target memory instruction for a MemFoldPseudo.
149def getTargetMemOpcode : InstrMapping {
150  let FilterClass = "InstSystemZ";
151  let RowFields = ["MemKey"];
152  let ColFields = ["MemType"];
153  let KeyCol = ["pseudo"];
154  let ValueCols = [["target"]];
155}
156
157// Return the 2-operand form of a 3-operand instruction.
158def getTwoOperandOpcode : InstrMapping {
159  let FilterClass = "InstSystemZ";
160  let RowFields = ["NumOpsKey"];
161  let ColFields = ["NumOpsValue"];
162  let KeyCol = ["3"];
163  let ValueCols = [["2"]];
164}
165
166//===----------------------------------------------------------------------===//
167// Instruction formats
168//===----------------------------------------------------------------------===//
169//
170// Formats are specified using operand field declarations of the form:
171//
172//   bits<4> Rn   : register input or output for operand n
173//   bits<5> Vn   : vector register input or output for operand n
174//   bits<m> In   : immediate value of width m for operand n
175//   bits<4> BDn  : address operand n, which has a base and a displacement
176//   bits<m> XBDn : address operand n, which has an index, a base and a
177//                  displacement
178//   bits<m> VBDn : address operand n, which has a vector index, a base and a
179//                  displacement
180//   bits<4> Xn   : index register for address operand n
181//   bits<4> Mn   : mode value for operand n
182//
183// The operand numbers ("n" in the list above) follow the architecture manual.
184// Assembly operands sometimes have a different order; in particular, R3 often
185// is often written between operands 1 and 2.
186//
187//===----------------------------------------------------------------------===//
188
189class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
190  : InstSystemZ<2, outs, ins, asmstr, pattern> {
191  field bits<16> Inst;
192  field bits<16> SoftFail = 0;
193
194  let Inst = op;
195}
196
197class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
198  : InstSystemZ<2, outs, ins, asmstr, pattern> {
199  field bits<16> Inst;
200  field bits<16> SoftFail = 0;
201
202  bits<8> I1;
203
204  let Inst{15-8} = op;
205  let Inst{7-0}  = I1;
206}
207
208class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
209  : InstSystemZ<4, outs, ins, asmstr, pattern> {
210  field bits<32> Inst;
211  field bits<32> SoftFail = 0;
212
213  bits<4> I1;
214  bits<4> I2;
215
216  let Inst{31-16} = op;
217  let Inst{15-8}  = 0;
218  let Inst{7-4}   = I1;
219  let Inst{3-0}   = I2;
220}
221
222class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
223  : InstSystemZ<6, outs, ins, asmstr, pattern> {
224  field bits<48> Inst;
225  field bits<48> SoftFail = 0;
226
227  bits<4> M1;
228  bits<12> RI2;
229  bits<24> RI3;
230
231  let Inst{47-40} = op;
232  let Inst{39-36} = M1;
233  let Inst{35-24} = RI2;
234  let Inst{23-0}  = RI3;
235}
236
237class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
238  : InstSystemZ<4, outs, ins, asmstr, pattern> {
239  field bits<32> Inst;
240  field bits<32> SoftFail = 0;
241
242  bits<4> R1;
243  bits<16> I2;
244
245  let Inst{31-24} = op{11-4};
246  let Inst{23-20} = R1;
247  let Inst{19-16} = op{3-0};
248  let Inst{15-0}  = I2;
249}
250
251class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
252  : InstSystemZ<4, outs, ins, asmstr, pattern> {
253  field bits<32> Inst;
254  field bits<32> SoftFail = 0;
255
256  bits<4> R1;
257  bits<16> RI2;
258
259  let Inst{31-24} = op{11-4};
260  let Inst{23-20} = R1;
261  let Inst{19-16} = op{3-0};
262  let Inst{15-0}  = RI2;
263}
264
265class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
266  : InstSystemZ<4, outs, ins, asmstr, pattern> {
267  field bits<32> Inst;
268  field bits<32> SoftFail = 0;
269
270  bits<4> M1;
271  bits<16> RI2;
272
273  let Inst{31-24} = op{11-4};
274  let Inst{23-20} = M1;
275  let Inst{19-16} = op{3-0};
276  let Inst{15-0}  = RI2;
277}
278
279class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
280  : InstSystemZ<6, outs, ins, asmstr, pattern> {
281  field bits<48> Inst;
282  field bits<48> SoftFail = 0;
283
284  bits<4> R1;
285  bits<16> I2;
286  bits<4> M3;
287
288  let Inst{47-40} = op{15-8};
289  let Inst{39-36} = R1;
290  let Inst{35-32} = 0;
291  let Inst{31-16} = I2;
292  let Inst{15-12} = M3;
293  let Inst{11-8}  = 0;
294  let Inst{7-0}   = op{7-0};
295}
296
297class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
298  : InstSystemZ<6, outs, ins, asmstr, pattern> {
299  field bits<48> Inst;
300  field bits<48> SoftFail = 0;
301
302  bits<4> R1;
303  bits<4> R2;
304  bits<4> M3;
305  bits<16> RI4;
306
307  let Inst{47-40} = op{15-8};
308  let Inst{39-36} = R1;
309  let Inst{35-32} = R2;
310  let Inst{31-16} = RI4;
311  let Inst{15-12} = M3;
312  let Inst{11-8}  = 0;
313  let Inst{7-0}   = op{7-0};
314}
315
316class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
317  : InstSystemZ<6, outs, ins, asmstr, pattern> {
318  field bits<48> Inst;
319  field bits<48> SoftFail = 0;
320
321  bits<4> R1;
322  bits<8> I2;
323  bits<4> M3;
324  bits<16> RI4;
325
326  let Inst{47-40} = op{15-8};
327  let Inst{39-36} = R1;
328  let Inst{35-32} = M3;
329  let Inst{31-16} = RI4;
330  let Inst{15-8}  = I2;
331  let Inst{7-0}   = op{7-0};
332}
333
334class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
335  : InstSystemZ<6, outs, ins, asmstr, pattern> {
336  field bits<48> Inst;
337  field bits<48> SoftFail = 0;
338
339  bits<4> R1;
340  bits<4> R3;
341  bits<16> I2;
342
343  let Inst{47-40} = op{15-8};
344  let Inst{39-36} = R1;
345  let Inst{35-32} = R3;
346  let Inst{31-16} = I2;
347  let Inst{15-8}  = 0;
348  let Inst{7-0}   = op{7-0};
349}
350
351class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
352  : InstSystemZ<6, outs, ins, asmstr, pattern> {
353  field bits<48> Inst;
354  field bits<48> SoftFail = 0;
355
356  bits<4> R1;
357  bits<4> R3;
358  bits<16> RI2;
359
360  let Inst{47-40} = op{15-8};
361  let Inst{39-36} = R1;
362  let Inst{35-32} = R3;
363  let Inst{31-16} = RI2;
364  let Inst{15-8}  = 0;
365  let Inst{7-0}   = op{7-0};
366}
367
368class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
369  : InstSystemZ<6, outs, ins, asmstr, pattern> {
370  field bits<48> Inst;
371  field bits<48> SoftFail = 0;
372
373  bits<4> R1;
374  bits<4> R2;
375  bits<8> I3;
376  bits<8> I4;
377  bits<8> I5;
378
379  let Inst{47-40} = op{15-8};
380  let Inst{39-36} = R1;
381  let Inst{35-32} = R2;
382  let Inst{31-24} = I3;
383  let Inst{23-16} = I4;
384  let Inst{15-8}  = I5;
385  let Inst{7-0}   = op{7-0};
386}
387
388class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
389  : InstSystemZ<6, outs, ins, asmstr, pattern> {
390  field bits<48> Inst;
391  field bits<48> SoftFail = 0;
392
393  bits<4> R1;
394  bits<4> M3;
395  bits<16> I2;
396
397  let Inst{47-40} = op{15-8};
398  let Inst{39-36} = R1;
399  let Inst{35-32} = M3;
400  let Inst{31-16} = I2;
401  let Inst{15-8}  = 0;
402  let Inst{7-0}   = op{7-0};
403}
404
405class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
406  : InstSystemZ<6, outs, ins, asmstr, pattern> {
407  field bits<48> Inst;
408  field bits<48> SoftFail = 0;
409
410  bits<4> R1;
411  bits<32> I2;
412
413  let Inst{47-40} = op{11-4};
414  let Inst{39-36} = R1;
415  let Inst{35-32} = op{3-0};
416  let Inst{31-0}  = I2;
417}
418
419class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
420  : InstSystemZ<6, outs, ins, asmstr, pattern> {
421  field bits<48> Inst;
422  field bits<48> SoftFail = 0;
423
424  bits<4> R1;
425  bits<32> RI2;
426
427  let Inst{47-40} = op{11-4};
428  let Inst{39-36} = R1;
429  let Inst{35-32} = op{3-0};
430  let Inst{31-0}  = RI2;
431}
432
433class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
434  : InstSystemZ<6, outs, ins, asmstr, pattern> {
435  field bits<48> Inst;
436  field bits<48> SoftFail = 0;
437
438  bits<4> M1;
439  bits<32> RI2;
440
441  let Inst{47-40} = op{11-4};
442  let Inst{39-36} = M1;
443  let Inst{35-32} = op{3-0};
444  let Inst{31-0}  = RI2;
445}
446
447class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
448  : InstSystemZ<6, outs, ins, asmstr, pattern> {
449  field bits<48> Inst;
450  field bits<48> SoftFail = 0;
451
452  bits<4> R1;
453  bits<8> I2;
454  bits<4> M3;
455  bits<16> BD4;
456
457  let Inst{47-40} = op{15-8};
458  let Inst{39-36} = R1;
459  let Inst{35-32} = M3;
460  let Inst{31-16} = BD4;
461  let Inst{15-8}  = I2;
462  let Inst{7-0}   = op{7-0};
463}
464
465class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
466  : InstSystemZ<2, outs, ins, asmstr, pattern> {
467  field bits<16> Inst;
468  field bits<16> SoftFail = 0;
469
470  bits<4> R1;
471  bits<4> R2;
472
473  let Inst{15-8} = op;
474  let Inst{7-4}  = R1;
475  let Inst{3-0}  = R2;
476}
477
478class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
479  : InstSystemZ<4, outs, ins, asmstr, pattern> {
480  field bits<32> Inst;
481  field bits<32> SoftFail = 0;
482
483  bits<4> R1;
484  bits<4> R3;
485  bits<4> R2;
486
487  let Inst{31-16} = op;
488  let Inst{15-12} = R1;
489  let Inst{11-8}  = 0;
490  let Inst{7-4}   = R3;
491  let Inst{3-0}   = R2;
492}
493
494class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
495  : InstSystemZ<4, outs, ins, asmstr, pattern> {
496  field bits<32> Inst;
497  field bits<32> SoftFail = 0;
498
499  bits<4> R1;
500  bits<4> R2;
501
502  let Inst{31-16} = op;
503  let Inst{15-8}  = 0;
504  let Inst{7-4}   = R1;
505  let Inst{3-0}   = R2;
506}
507
508class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
509  : InstSystemZ<4, outs, ins, asmstr, pattern> {
510  field bits<32> Inst;
511  field bits<32> SoftFail = 0;
512
513  bits<4> R1;
514  bits<4> R2;
515  bits<4> R3;
516  bits<4> M4;
517
518  let Inst{31-16} = op;
519  let Inst{15-12} = R3;
520  let Inst{11-8}  = M4;
521  let Inst{7-4}   = R1;
522  let Inst{3-0}   = R2;
523}
524
525class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
526  : InstSystemZ<4, outs, ins, asmstr, pattern> {
527  field bits<32> Inst;
528  field bits<32> SoftFail = 0;
529
530  bits<4> R1;
531  bits<4> R2;
532  bits<4> R3;
533  bits<4> M4;
534
535  let Inst{31-16} = op;
536  let Inst{15-12} = R3;
537  let Inst{11-8}  = M4;
538  let Inst{7-4}   = R1;
539  let Inst{3-0}   = R2;
540}
541
542class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
543  : InstSystemZ<4, outs, ins, asmstr, pattern> {
544  field bits<32> Inst;
545  field bits<32> SoftFail = 0;
546
547  bits<4> R1;
548  bits<4> R2;
549  bits<4> M3;
550
551  let Inst{31-16} = op;
552  let Inst{15-12} = M3;
553  let Inst{11-8}  = 0;
554  let Inst{7-4}   = R1;
555  let Inst{3-0}   = R2;
556}
557
558class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
559  : InstSystemZ<4, outs, ins, asmstr, pattern> {
560  field bits<32> Inst;
561  field bits<32> SoftFail = 0;
562
563  bits<4> R1;
564  bits<4> R2;
565  bits<4> M4;
566
567  let Inst{31-16} = op;
568  let Inst{15-12} = 0;
569  let Inst{11-8}  = M4;
570  let Inst{7-4}   = R1;
571  let Inst{3-0}   = R2;
572}
573
574class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
575  : InstSystemZ<4, outs, ins, asmstr, pattern> {
576  field bits<32> Inst;
577  field bits<32> SoftFail = 0;
578
579  bits<4> R1;
580  bits<4> R2;
581  bits<4> M3;
582  bits<4> M4;
583
584  let Inst{31-16} = op;
585  let Inst{15-12} = M3;
586  let Inst{11-8}  = M4;
587  let Inst{7-4}   = R1;
588  let Inst{3-0}   = R2;
589}
590
591class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
592  : InstSystemZ<6, outs, ins, asmstr, pattern> {
593  field bits<48> Inst;
594  field bits<48> SoftFail = 0;
595
596  bits<4> R1;
597  bits<4> R2;
598  bits<4> M3;
599  bits<16> BD4;
600
601  let Inst{47-40} = op{15-8};
602  let Inst{39-36} = R1;
603  let Inst{35-32} = R2;
604  let Inst{31-16} = BD4;
605  let Inst{15-12} = M3;
606  let Inst{11-8}  = 0;
607  let Inst{7-0}   = op{7-0};
608}
609
610class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
611  : InstSystemZ<4, outs, ins, asmstr, pattern> {
612  field bits<32> Inst;
613  field bits<32> SoftFail = 0;
614
615  bits<4> R1;
616  bits<20> XBD2;
617
618  let Inst{31-24} = op;
619  let Inst{23-20} = R1;
620  let Inst{19-0}  = XBD2;
621
622  let HasIndex = 1;
623}
624
625class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
626  : InstSystemZ<4, outs, ins, asmstr, pattern> {
627  field bits<32> Inst;
628  field bits<32> SoftFail = 0;
629
630  bits<4> M1;
631  bits<20> XBD2;
632
633  let Inst{31-24} = op;
634  let Inst{23-20} = M1;
635  let Inst{19-0}  = XBD2;
636
637  let HasIndex = 1;
638}
639
640class InstRXE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
641  : InstSystemZ<6, outs, ins, asmstr, pattern> {
642  field bits<48> Inst;
643  field bits<48> SoftFail = 0;
644
645  bits<4> R1;
646  bits<20> XBD2;
647  bits<4> M3;
648
649  let Inst{47-40} = op{15-8};
650  let Inst{39-36} = R1;
651  let Inst{35-16} = XBD2;
652  let Inst{15-12} = M3;
653  let Inst{11-8}  = 0;
654  let Inst{7-0}   = op{7-0};
655
656  let HasIndex = 1;
657}
658
659class InstRXF<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
660  : InstSystemZ<6, outs, ins, asmstr, pattern> {
661  field bits<48> Inst;
662  field bits<48> SoftFail = 0;
663
664  bits<4> R1;
665  bits<4> R3;
666  bits<20> XBD2;
667
668  let Inst{47-40} = op{15-8};
669  let Inst{39-36} = R3;
670  let Inst{35-16} = XBD2;
671  let Inst{15-12} = R1;
672  let Inst{11-8}  = 0;
673  let Inst{7-0}   = op{7-0};
674
675  let HasIndex = 1;
676}
677
678class InstRXYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
679  : InstSystemZ<6, outs, ins, asmstr, pattern> {
680  field bits<48> Inst;
681  field bits<48> SoftFail = 0;
682
683  bits<4> R1;
684  bits<28> XBD2;
685
686  let Inst{47-40} = op{15-8};
687  let Inst{39-36} = R1;
688  let Inst{35-8}  = XBD2;
689  let Inst{7-0}   = op{7-0};
690
691  let Has20BitOffset = 1;
692  let HasIndex = 1;
693}
694
695class InstRXYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
696  : InstSystemZ<6, outs, ins, asmstr, pattern> {
697  field bits<48> Inst;
698  field bits<48> SoftFail = 0;
699
700  bits<4> M1;
701  bits<28> XBD2;
702
703  let Inst{47-40} = op{15-8};
704  let Inst{39-36} = M1;
705  let Inst{35-8}  = XBD2;
706  let Inst{7-0}   = op{7-0};
707
708  let Has20BitOffset = 1;
709  let HasIndex = 1;
710}
711
712class InstRSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
713  : InstSystemZ<4, outs, ins, asmstr, pattern> {
714  field bits<32> Inst;
715  field bits<32> SoftFail = 0;
716
717  bits<4> R1;
718  bits<4> R3;
719  bits<16> BD2;
720
721  let Inst{31-24} = op;
722  let Inst{23-20} = R1;
723  let Inst{19-16} = R3;
724  let Inst{15-0}  = BD2;
725}
726
727class InstRSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
728  : InstSystemZ<4, outs, ins, asmstr, pattern> {
729  field bits<32> Inst;
730  field bits<32> SoftFail = 0;
731
732  bits<4> R1;
733  bits<4> M3;
734  bits<16> BD2;
735
736  let Inst{31-24} = op;
737  let Inst{23-20} = R1;
738  let Inst{19-16} = M3;
739  let Inst{15-0}  = BD2;
740}
741
742class InstRSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
743  : InstSystemZ<4, outs, ins, asmstr, pattern> {
744  field bits<32> Inst;
745  field bits<32> SoftFail = 0;
746
747  bits<4> R1;
748  bits<4> R3;
749  bits<16> RI2;
750
751  let Inst{31-24} = op;
752  let Inst{23-20} = R1;
753  let Inst{19-16} = R3;
754  let Inst{15-0}  = RI2;
755}
756
757class InstRSLa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
758  : InstSystemZ<6, outs, ins, asmstr, pattern> {
759  field bits<48> Inst;
760  field bits<48> SoftFail = 0;
761
762  bits<20> BDL1;
763
764  let Inst{47-40} = op{15-8};
765  let Inst{39-36} = BDL1{19-16};
766  let Inst{35-32} = 0;
767  let Inst{31-16} = BDL1{15-0};
768  let Inst{15-8}  = 0;
769  let Inst{7-0}   = op{7-0};
770}
771
772class InstRSLb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
773  : InstSystemZ<6, outs, ins, asmstr, pattern> {
774  field bits<48> Inst;
775  field bits<48> SoftFail = 0;
776
777  bits<4> R1;
778  bits<24> BDL2;
779  bits<4> M3;
780
781  let Inst{47-40} = op{15-8};
782  let Inst{39-16} = BDL2;
783  let Inst{15-12} = R1;
784  let Inst{11-8}  = M3;
785  let Inst{7-0}   = op{7-0};
786}
787
788class InstRSYa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
789  : InstSystemZ<6, outs, ins, asmstr, pattern> {
790  field bits<48> Inst;
791  field bits<48> SoftFail = 0;
792
793  bits<4> R1;
794  bits<4> R3;
795  bits<24> BD2;
796
797  let Inst{47-40} = op{15-8};
798  let Inst{39-36} = R1;
799  let Inst{35-32} = R3;
800  let Inst{31-8}  = BD2;
801  let Inst{7-0}   = op{7-0};
802
803  let Has20BitOffset = 1;
804}
805
806class InstRSYb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
807  : InstSystemZ<6, outs, ins, asmstr, pattern> {
808  field bits<48> Inst;
809  field bits<48> SoftFail = 0;
810
811  bits<4> R1;
812  bits<4> M3;
813  bits<24> BD2;
814
815  let Inst{47-40} = op{15-8};
816  let Inst{39-36} = R1;
817  let Inst{35-32} = M3;
818  let Inst{31-8}  = BD2;
819  let Inst{7-0}   = op{7-0};
820
821  let Has20BitOffset = 1;
822}
823
824class InstSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
825  : InstSystemZ<4, outs, ins, asmstr, pattern> {
826  field bits<32> Inst;
827  field bits<32> SoftFail = 0;
828
829  bits<16> BD1;
830  bits<8> I2;
831
832  let Inst{31-24} = op;
833  let Inst{23-16} = I2;
834  let Inst{15-0}  = BD1;
835}
836
837class InstSIL<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
838  : InstSystemZ<6, outs, ins, asmstr, pattern> {
839  field bits<48> Inst;
840  field bits<48> SoftFail = 0;
841
842  bits<16> BD1;
843  bits<16> I2;
844
845  let Inst{47-32} = op;
846  let Inst{31-16} = BD1;
847  let Inst{15-0}  = I2;
848}
849
850class InstSIY<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
851  : InstSystemZ<6, outs, ins, asmstr, pattern> {
852  field bits<48> Inst;
853  field bits<48> SoftFail = 0;
854
855  bits<24> BD1;
856  bits<8> I2;
857
858  let Inst{47-40} = op{15-8};
859  let Inst{39-32} = I2;
860  let Inst{31-8}  = BD1;
861  let Inst{7-0}   = op{7-0};
862
863  let Has20BitOffset = 1;
864}
865
866class InstSMI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
867  : InstSystemZ<6, outs, ins, asmstr, pattern> {
868  field bits<48> Inst;
869  field bits<48> SoftFail = 0;
870
871  bits<4> M1;
872  bits<16> RI2;
873  bits<16> BD3;
874
875  let Inst{47-40} = op;
876  let Inst{39-36} = M1;
877  let Inst{35-32} = 0;
878  let Inst{31-16} = BD3;
879  let Inst{15-0}  = RI2;
880}
881
882class InstSSa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
883  : InstSystemZ<6, outs, ins, asmstr, pattern> {
884  field bits<48> Inst;
885  field bits<48> SoftFail = 0;
886
887  bits<24> BDL1;
888  bits<16> BD2;
889
890  let Inst{47-40} = op;
891  let Inst{39-16} = BDL1;
892  let Inst{15-0}  = BD2;
893}
894
895class InstSSb<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
896  : InstSystemZ<6, outs, ins, asmstr, pattern> {
897  field bits<48> Inst;
898  field bits<48> SoftFail = 0;
899
900  bits<20> BDL1;
901  bits<20> BDL2;
902
903  let Inst{47-40} = op;
904  let Inst{39-36} = BDL1{19-16};
905  let Inst{35-32} = BDL2{19-16};
906  let Inst{31-16} = BDL1{15-0};
907  let Inst{15-0}  = BDL2{15-0};
908}
909
910class InstSSc<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
911  : InstSystemZ<6, outs, ins, asmstr, pattern> {
912  field bits<48> Inst;
913  field bits<48> SoftFail = 0;
914
915  bits<20> BDL1;
916  bits<16> BD2;
917  bits<4> I3;
918
919  let Inst{47-40} = op;
920  let Inst{39-36} = BDL1{19-16};
921  let Inst{35-32} = I3;
922  let Inst{31-16} = BDL1{15-0};
923  let Inst{15-0}  = BD2;
924}
925
926class InstSSd<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
927  : InstSystemZ<6, outs, ins, asmstr, pattern> {
928  field bits<48> Inst;
929  field bits<48> SoftFail = 0;
930
931  bits<20> RBD1;
932  bits<16> BD2;
933  bits<4> R3;
934
935  let Inst{47-40} = op;
936  let Inst{39-36} = RBD1{19-16};
937  let Inst{35-32} = R3;
938  let Inst{31-16} = RBD1{15-0};
939  let Inst{15-0}  = BD2;
940}
941
942class InstSSe<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
943  : InstSystemZ<6, outs, ins, asmstr, pattern> {
944  field bits<48> Inst;
945  field bits<48> SoftFail = 0;
946
947  bits<4> R1;
948  bits<16> BD2;
949  bits<4> R3;
950  bits<16> BD4;
951
952  let Inst{47-40} = op;
953  let Inst{39-36} = R1;
954  let Inst{35-32} = R3;
955  let Inst{31-16} = BD2;
956  let Inst{15-0}  = BD4;
957}
958
959class InstSSf<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
960  : InstSystemZ<6, outs, ins, asmstr, pattern> {
961  field bits<48> Inst;
962  field bits<48> SoftFail = 0;
963
964  bits<16> BD1;
965  bits<24> BDL2;
966
967  let Inst{47-40} = op;
968  let Inst{39-32} = BDL2{23-16};
969  let Inst{31-16} = BD1;
970  let Inst{15-0}  = BDL2{15-0};
971}
972
973class InstSSE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
974  : InstSystemZ<6, outs, ins, asmstr, pattern> {
975  field bits<48> Inst;
976  field bits<48> SoftFail = 0;
977
978  bits<16> BD1;
979  bits<16> BD2;
980
981  let Inst{47-32} = op;
982  let Inst{31-16} = BD1;
983  let Inst{15-0}  = BD2;
984}
985
986class InstSSF<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
987  : InstSystemZ<6, outs, ins, asmstr, pattern> {
988  field bits<48> Inst;
989  field bits<48> SoftFail = 0;
990
991  bits<16> BD1;
992  bits<16> BD2;
993  bits<4>  R3;
994
995  let Inst{47-40} = op{11-4};
996  let Inst{39-36} = R3;
997  let Inst{35-32} = op{3-0};
998  let Inst{31-16} = BD1;
999  let Inst{15-0}  = BD2;
1000}
1001
1002class InstS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1003  : InstSystemZ<4, outs, ins, asmstr, pattern> {
1004  field bits<32> Inst;
1005  field bits<32> SoftFail = 0;
1006
1007  bits<16> BD2;
1008
1009  let Inst{31-16} = op;
1010  let Inst{15-0}  = BD2;
1011}
1012
1013class InstVRIa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1014  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1015  field bits<48> Inst;
1016  field bits<48> SoftFail = 0;
1017
1018  bits<5> V1;
1019  bits<16> I2;
1020  bits<4> M3;
1021
1022  let Inst{47-40} = op{15-8};
1023  let Inst{39-36} = V1{3-0};
1024  let Inst{35-32} = 0;
1025  let Inst{31-16} = I2;
1026  let Inst{15-12} = M3;
1027  let Inst{11}    = V1{4};
1028  let Inst{10-8}  = 0;
1029  let Inst{7-0}   = op{7-0};
1030}
1031
1032class InstVRIb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1033  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1034  field bits<48> Inst;
1035  field bits<48> SoftFail = 0;
1036
1037  bits<5> V1;
1038  bits<8> I2;
1039  bits<8> I3;
1040  bits<4> M4;
1041
1042  let Inst{47-40} = op{15-8};
1043  let Inst{39-36} = V1{3-0};
1044  let Inst{35-32} = 0;
1045  let Inst{31-24} = I2;
1046  let Inst{23-16} = I3;
1047  let Inst{15-12} = M4;
1048  let Inst{11}    = V1{4};
1049  let Inst{10-8}  = 0;
1050  let Inst{7-0}   = op{7-0};
1051}
1052
1053class InstVRIc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1054  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1055  field bits<48> Inst;
1056  field bits<48> SoftFail = 0;
1057
1058  bits<5> V1;
1059  bits<5> V3;
1060  bits<16> I2;
1061  bits<4> M4;
1062
1063  let Inst{47-40} = op{15-8};
1064  let Inst{39-36} = V1{3-0};
1065  let Inst{35-32} = V3{3-0};
1066  let Inst{31-16} = I2;
1067  let Inst{15-12} = M4;
1068  let Inst{11}    = V1{4};
1069  let Inst{10}    = V3{4};
1070  let Inst{9-8}   = 0;
1071  let Inst{7-0}   = op{7-0};
1072}
1073
1074class InstVRId<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1075  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1076  field bits<48> Inst;
1077  field bits<48> SoftFail = 0;
1078
1079  bits<5> V1;
1080  bits<5> V2;
1081  bits<5> V3;
1082  bits<8> I4;
1083  bits<4> M5;
1084
1085  let Inst{47-40} = op{15-8};
1086  let Inst{39-36} = V1{3-0};
1087  let Inst{35-32} = V2{3-0};
1088  let Inst{31-28} = V3{3-0};
1089  let Inst{27-24} = 0;
1090  let Inst{23-16} = I4;
1091  let Inst{15-12} = M5;
1092  let Inst{11}    = V1{4};
1093  let Inst{10}    = V2{4};
1094  let Inst{9}     = V3{4};
1095  let Inst{8}     = 0;
1096  let Inst{7-0}   = op{7-0};
1097}
1098
1099class InstVRIe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1100  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1101  field bits<48> Inst;
1102  field bits<48> SoftFail = 0;
1103
1104  bits<5> V1;
1105  bits<5> V2;
1106  bits<12> I3;
1107  bits<4> M4;
1108  bits<4> M5;
1109
1110  let Inst{47-40} = op{15-8};
1111  let Inst{39-36} = V1{3-0};
1112  let Inst{35-32} = V2{3-0};
1113  let Inst{31-20} = I3;
1114  let Inst{19-16} = M5;
1115  let Inst{15-12} = M4;
1116  let Inst{11}    = V1{4};
1117  let Inst{10}    = V2{4};
1118  let Inst{9-8}   = 0;
1119  let Inst{7-0}   = op{7-0};
1120}
1121
1122class InstVRIf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1123  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1124  field bits<48> Inst;
1125  field bits<48> SoftFail = 0;
1126
1127  bits<5> V1;
1128  bits<5> V2;
1129  bits<5> V3;
1130  bits<8> I4;
1131  bits<4> M5;
1132
1133  let Inst{47-40} = op{15-8};
1134  let Inst{39-36} = V1{3-0};
1135  let Inst{35-32} = V2{3-0};
1136  let Inst{31-28} = V3{3-0};
1137  let Inst{27-24} = 0;
1138  let Inst{23-20} = M5;
1139  let Inst{19-12} = I4;
1140  let Inst{11}    = V1{4};
1141  let Inst{10}    = V2{4};
1142  let Inst{9}     = V3{4};
1143  let Inst{8}     = 0;
1144  let Inst{7-0}   = op{7-0};
1145}
1146
1147class InstVRIg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1148  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1149  field bits<48> Inst;
1150  field bits<48> SoftFail = 0;
1151
1152  bits<5> V1;
1153  bits<5> V2;
1154  bits<8> I3;
1155  bits<8> I4;
1156  bits<4> M5;
1157
1158  let Inst{47-40} = op{15-8};
1159  let Inst{39-36} = V1{3-0};
1160  let Inst{35-32} = V2{3-0};
1161  let Inst{31-24} = I4;
1162  let Inst{23-20} = M5;
1163  let Inst{19-12} = I3;
1164  let Inst{11}    = V1{4};
1165  let Inst{10}    = V2{4};
1166  let Inst{9-8}   = 0;
1167  let Inst{7-0}   = op{7-0};
1168}
1169
1170class InstVRIh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1171  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1172  field bits<48> Inst;
1173  field bits<48> SoftFail = 0;
1174
1175  bits<5> V1;
1176  bits<16> I2;
1177  bits<4> I3;
1178
1179  let Inst{47-40} = op{15-8};
1180  let Inst{39-36} = V1{3-0};
1181  let Inst{35-32} = 0;
1182  let Inst{31-16} = I2;
1183  let Inst{15-12} = I3;
1184  let Inst{11}    = V1{4};
1185  let Inst{10-8}  = 0;
1186  let Inst{7-0}   = op{7-0};
1187}
1188
1189class InstVRIi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1190  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1191  field bits<48> Inst;
1192  field bits<48> SoftFail = 0;
1193
1194  bits<5> V1;
1195  bits<4> R2;
1196  bits<8> I3;
1197  bits<4> M4;
1198
1199  let Inst{47-40} = op{15-8};
1200  let Inst{39-36} = V1{3-0};
1201  let Inst{35-32} = R2;
1202  let Inst{31-24} = 0;
1203  let Inst{23-20} = M4;
1204  let Inst{19-12} = I3;
1205  let Inst{11}    = V1{4};
1206  let Inst{10-8}  = 0;
1207  let Inst{7-0}   = op{7-0};
1208}
1209
1210// Depending on the instruction mnemonic, certain bits may be or-ed into
1211// the M4 value provided as explicit operand.  These are passed as m4or.
1212class InstVRRa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1213               bits<4> m4or = 0>
1214  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1215  field bits<48> Inst;
1216  field bits<48> SoftFail = 0;
1217
1218  bits<5> V1;
1219  bits<5> V2;
1220  bits<4> M3;
1221  bits<4> M4;
1222  bits<4> M5;
1223
1224  let Inst{47-40} = op{15-8};
1225  let Inst{39-36} = V1{3-0};
1226  let Inst{35-32} = V2{3-0};
1227  let Inst{31-24} = 0;
1228  let Inst{23-20} = M5;
1229  let Inst{19}    = !if (!eq (m4or{3}, 1), 1, M4{3});
1230  let Inst{18}    = !if (!eq (m4or{2}, 1), 1, M4{2});
1231  let Inst{17}    = !if (!eq (m4or{1}, 1), 1, M4{1});
1232  let Inst{16}    = !if (!eq (m4or{0}, 1), 1, M4{0});
1233  let Inst{15-12} = M3;
1234  let Inst{11}    = V1{4};
1235  let Inst{10}    = V2{4};
1236  let Inst{9-8}   = 0;
1237  let Inst{7-0}   = op{7-0};
1238}
1239
1240// Depending on the instruction mnemonic, certain bits may be or-ed into
1241// the M5 value provided as explicit operand.  These are passed as m5or.
1242class InstVRRb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1243               bits<4> m5or = 0>
1244  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1245  field bits<48> Inst;
1246  field bits<48> SoftFail = 0;
1247
1248  bits<5> V1;
1249  bits<5> V2;
1250  bits<5> V3;
1251  bits<4> M4;
1252  bits<4> M5;
1253
1254  let Inst{47-40} = op{15-8};
1255  let Inst{39-36} = V1{3-0};
1256  let Inst{35-32} = V2{3-0};
1257  let Inst{31-28} = V3{3-0};
1258  let Inst{27-24} = 0;
1259  let Inst{23}    = !if (!eq (m5or{3}, 1), 1, M5{3});
1260  let Inst{22}    = !if (!eq (m5or{2}, 1), 1, M5{2});
1261  let Inst{21}    = !if (!eq (m5or{1}, 1), 1, M5{1});
1262  let Inst{20}    = !if (!eq (m5or{0}, 1), 1, M5{0});
1263  let Inst{19-16} = 0;
1264  let Inst{15-12} = M4;
1265  let Inst{11}    = V1{4};
1266  let Inst{10}    = V2{4};
1267  let Inst{9}     = V3{4};
1268  let Inst{8}     = 0;
1269  let Inst{7-0}   = op{7-0};
1270}
1271
1272class InstVRRc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1273  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1274  field bits<48> Inst;
1275  field bits<48> SoftFail = 0;
1276
1277  bits<5> V1;
1278  bits<5> V2;
1279  bits<5> V3;
1280  bits<4> M4;
1281  bits<4> M5;
1282  bits<4> M6;
1283
1284  let Inst{47-40} = op{15-8};
1285  let Inst{39-36} = V1{3-0};
1286  let Inst{35-32} = V2{3-0};
1287  let Inst{31-28} = V3{3-0};
1288  let Inst{27-24} = 0;
1289  let Inst{23-20} = M6;
1290  let Inst{19-16} = M5;
1291  let Inst{15-12} = M4;
1292  let Inst{11}    = V1{4};
1293  let Inst{10}    = V2{4};
1294  let Inst{9}     = V3{4};
1295  let Inst{8}     = 0;
1296  let Inst{7-0}   = op{7-0};
1297}
1298
1299// Depending on the instruction mnemonic, certain bits may be or-ed into
1300// the M6 value provided as explicit operand.  These are passed as m6or.
1301class InstVRRd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
1302               bits<4> m6or = 0>
1303  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1304  field bits<48> Inst;
1305  field bits<48> SoftFail = 0;
1306
1307  bits<5> V1;
1308  bits<5> V2;
1309  bits<5> V3;
1310  bits<5> V4;
1311  bits<4> M5;
1312  bits<4> M6;
1313
1314  let Inst{47-40} = op{15-8};
1315  let Inst{39-36} = V1{3-0};
1316  let Inst{35-32} = V2{3-0};
1317  let Inst{31-28} = V3{3-0};
1318  let Inst{27-24} = M5;
1319  let Inst{23}    = !if (!eq (m6or{3}, 1), 1, M6{3});
1320  let Inst{22}    = !if (!eq (m6or{2}, 1), 1, M6{2});
1321  let Inst{21}    = !if (!eq (m6or{1}, 1), 1, M6{1});
1322  let Inst{20}    = !if (!eq (m6or{0}, 1), 1, M6{0});
1323  let Inst{19-16} = 0;
1324  let Inst{15-12} = V4{3-0};
1325  let Inst{11}    = V1{4};
1326  let Inst{10}    = V2{4};
1327  let Inst{9}     = V3{4};
1328  let Inst{8}     = V4{4};
1329  let Inst{7-0}   = op{7-0};
1330}
1331
1332class InstVRRe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1333  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1334  field bits<48> Inst;
1335  field bits<48> SoftFail = 0;
1336
1337  bits<5> V1;
1338  bits<5> V2;
1339  bits<5> V3;
1340  bits<5> V4;
1341  bits<4> M5;
1342  bits<4> M6;
1343
1344  let Inst{47-40} = op{15-8};
1345  let Inst{39-36} = V1{3-0};
1346  let Inst{35-32} = V2{3-0};
1347  let Inst{31-28} = V3{3-0};
1348  let Inst{27-24} = M6;
1349  let Inst{23-20} = 0;
1350  let Inst{19-16} = M5;
1351  let Inst{15-12} = V4{3-0};
1352  let Inst{11}    = V1{4};
1353  let Inst{10}    = V2{4};
1354  let Inst{9}     = V3{4};
1355  let Inst{8}     = V4{4};
1356  let Inst{7-0}   = op{7-0};
1357}
1358
1359class InstVRRf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1360  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1361  field bits<48> Inst;
1362  field bits<48> SoftFail = 0;
1363
1364  bits<5> V1;
1365  bits<4> R2;
1366  bits<4> R3;
1367
1368  let Inst{47-40} = op{15-8};
1369  let Inst{39-36} = V1{3-0};
1370  let Inst{35-32} = R2;
1371  let Inst{31-28} = R3;
1372  let Inst{27-12} = 0;
1373  let Inst{11}    = V1{4};
1374  let Inst{10-8}  = 0;
1375  let Inst{7-0}   = op{7-0};
1376}
1377
1378class InstVRRg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1379  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1380  field bits<48> Inst;
1381  field bits<48> SoftFail = 0;
1382
1383  bits<5> V1;
1384
1385  let Inst{47-40} = op{15-8};
1386  let Inst{39-36} = 0;
1387  let Inst{35-32} = V1{3-0};
1388  let Inst{31-12} = 0;
1389  let Inst{11}    = 0;
1390  let Inst{10}    = V1{4};
1391  let Inst{9-8}   = 0;
1392  let Inst{7-0}   = op{7-0};
1393}
1394
1395class InstVRRh<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1396  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1397  field bits<48> Inst;
1398  field bits<48> SoftFail = 0;
1399
1400  bits<5> V1;
1401  bits<5> V2;
1402  bits<4> M3;
1403
1404  let Inst{47-40} = op{15-8};
1405  let Inst{39-36} = 0;
1406  let Inst{35-32} = V1{3-0};
1407  let Inst{31-28} = V2{3-0};
1408  let Inst{27-24} = 0;
1409  let Inst{23-20} = M3;
1410  let Inst{19-12} = 0;
1411  let Inst{11}    = 0;
1412  let Inst{10}    = V1{4};
1413  let Inst{9}     = V2{4};
1414  let Inst{8}     = 0;
1415  let Inst{7-0}   = op{7-0};
1416}
1417
1418class InstVRRi<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1419  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1420  field bits<48> Inst;
1421  field bits<48> SoftFail = 0;
1422
1423  bits<4> R1;
1424  bits<5> V2;
1425  bits<4> M3;
1426  bits<4> M4;
1427
1428  let Inst{47-40} = op{15-8};
1429  let Inst{39-36} = R1;
1430  let Inst{35-32} = V2{3-0};
1431  let Inst{31-24} = 0;
1432  let Inst{23-20} = M3;
1433  let Inst{19-16} = M4;
1434  let Inst{15-12} = 0;
1435  let Inst{11}    = 0;
1436  let Inst{10}    = V2{4};
1437  let Inst{9-8}   = 0;
1438  let Inst{7-0}   = op{7-0};
1439}
1440
1441class InstVRSa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1442  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1443  field bits<48> Inst;
1444  field bits<48> SoftFail = 0;
1445
1446  bits<5> V1;
1447  bits<16> BD2;
1448  bits<5> V3;
1449  bits<4> M4;
1450
1451  let Inst{47-40} = op{15-8};
1452  let Inst{39-36} = V1{3-0};
1453  let Inst{35-32} = V3{3-0};
1454  let Inst{31-16} = BD2;
1455  let Inst{15-12} = M4;
1456  let Inst{11}    = V1{4};
1457  let Inst{10}    = V3{4};
1458  let Inst{9-8}   = 0;
1459  let Inst{7-0}   = op{7-0};
1460}
1461
1462class InstVRSb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1463  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1464  field bits<48> Inst;
1465  field bits<48> SoftFail = 0;
1466
1467  bits<5> V1;
1468  bits<16> BD2;
1469  bits<4> R3;
1470  bits<4> M4;
1471
1472  let Inst{47-40} = op{15-8};
1473  let Inst{39-36} = V1{3-0};
1474  let Inst{35-32} = R3;
1475  let Inst{31-16} = BD2;
1476  let Inst{15-12} = M4;
1477  let Inst{11}    = V1{4};
1478  let Inst{10-8}  = 0;
1479  let Inst{7-0}   = op{7-0};
1480}
1481
1482class InstVRSc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1483  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1484  field bits<48> Inst;
1485  field bits<48> SoftFail = 0;
1486
1487  bits<4> R1;
1488  bits<16> BD2;
1489  bits<5> V3;
1490  bits<4> M4;
1491
1492  let Inst{47-40} = op{15-8};
1493  let Inst{39-36} = R1;
1494  let Inst{35-32} = V3{3-0};
1495  let Inst{31-16} = BD2;
1496  let Inst{15-12} = M4;
1497  let Inst{11}    = 0;
1498  let Inst{10}    = V3{4};
1499  let Inst{9-8}   = 0;
1500  let Inst{7-0}   = op{7-0};
1501}
1502
1503class InstVRSd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1504  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1505  field bits<48> Inst;
1506  field bits<48> SoftFail = 0;
1507
1508  bits<5> V1;
1509  bits<16> BD2;
1510  bits<4> R3;
1511
1512  let Inst{47-40} = op{15-8};
1513  let Inst{39-36} = 0;
1514  let Inst{35-32} = R3;
1515  let Inst{31-16} = BD2;
1516  let Inst{15-12} = V1{3-0};
1517  let Inst{11-9}  = 0;
1518  let Inst{8}     = V1{4};
1519  let Inst{7-0}   = op{7-0};
1520}
1521
1522class InstVRV<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1523  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1524  field bits<48> Inst;
1525  field bits<48> SoftFail = 0;
1526
1527  bits<5> V1;
1528  bits<21> VBD2;
1529  bits<4> M3;
1530
1531  let Inst{47-40} = op{15-8};
1532  let Inst{39-36} = V1{3-0};
1533  let Inst{35-16} = VBD2{19-0};
1534  let Inst{15-12} = M3;
1535  let Inst{11}    = V1{4};
1536  let Inst{10}    = VBD2{20};
1537  let Inst{9-8}   = 0;
1538  let Inst{7-0}   = op{7-0};
1539}
1540
1541class InstVRX<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1542  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1543  field bits<48> Inst;
1544  field bits<48> SoftFail = 0;
1545
1546  bits<5> V1;
1547  bits<20> XBD2;
1548  bits<4> M3;
1549
1550  let Inst{47-40} = op{15-8};
1551  let Inst{39-36} = V1{3-0};
1552  let Inst{35-16} = XBD2;
1553  let Inst{15-12} = M3;
1554  let Inst{11}    = V1{4};
1555  let Inst{10-8}  = 0;
1556  let Inst{7-0}   = op{7-0};
1557}
1558
1559class InstVSI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
1560  : InstSystemZ<6, outs, ins, asmstr, pattern> {
1561  field bits<48> Inst;
1562  field bits<48> SoftFail = 0;
1563
1564  bits<5> V1;
1565  bits<16> BD2;
1566  bits<8> I3;
1567
1568  let Inst{47-40} = op{15-8};
1569  let Inst{39-32} = I3;
1570  let Inst{31-16} = BD2;
1571  let Inst{15-12} = V1{3-0};
1572  let Inst{11-9}  = 0;
1573  let Inst{8}     = V1{4};
1574  let Inst{7-0}   = op{7-0};
1575}
1576
1577//===----------------------------------------------------------------------===//
1578// Instruction classes for .insn directives
1579//===----------------------------------------------------------------------===//
1580
1581class DirectiveInsnE<dag outs, dag ins, string asmstr, list<dag> pattern>
1582  : InstE<0, outs, ins, asmstr, pattern> {
1583  bits<16> enc;
1584
1585  let Inst = enc;
1586}
1587
1588class DirectiveInsnRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1589  : InstRIa<0, outs, ins, asmstr, pattern> {
1590  bits<32> enc;
1591
1592  let Inst{31-24} = enc{31-24};
1593  let Inst{19-16} = enc{19-16};
1594}
1595
1596class DirectiveInsnRIE<dag outs, dag ins, string asmstr, list<dag> pattern>
1597  : InstRIEd<0, outs, ins, asmstr, pattern> {
1598  bits<48> enc;
1599
1600  let Inst{47-40} = enc{47-40};
1601  let Inst{7-0}   = enc{7-0};
1602}
1603
1604class DirectiveInsnRIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1605  : InstRILa<0, outs, ins, asmstr, pattern> {
1606  bits<48> enc;
1607  string type;
1608
1609  let Inst{47-40} = enc{47-40};
1610  let Inst{35-32} = enc{35-32};
1611}
1612
1613class DirectiveInsnRIS<dag outs, dag ins, string asmstr, list<dag> pattern>
1614  : InstRIS<0, outs, ins, asmstr, pattern> {
1615  bits<48> enc;
1616
1617  let Inst{47-40} = enc{47-40};
1618  let Inst{7-0}   = enc{7-0};
1619}
1620
1621class DirectiveInsnRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1622  : InstRR<0, outs, ins, asmstr, pattern> {
1623  bits<16> enc;
1624
1625  let Inst{15-8} = enc{15-8};
1626}
1627
1628class DirectiveInsnRRE<dag outs, dag ins, string asmstr, list<dag> pattern>
1629  : InstRRE<0, outs, ins, asmstr, pattern> {
1630  bits<32> enc;
1631
1632  let Inst{31-16} = enc{31-16};
1633}
1634
1635class DirectiveInsnRRF<dag outs, dag ins, string asmstr, list<dag> pattern>
1636  : InstRRFa<0, outs, ins, asmstr, pattern> {
1637  bits<32> enc;
1638
1639  let Inst{31-16} = enc{31-16};
1640}
1641
1642class DirectiveInsnRRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1643  : InstRRS<0, outs, ins, asmstr, pattern> {
1644  bits<48> enc;
1645
1646  let Inst{47-40} = enc{47-40};
1647  let Inst{7-0}   = enc{7-0};
1648}
1649
1650class DirectiveInsnRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1651  : InstRSa<0, outs, ins, asmstr, pattern> {
1652  bits<32> enc;
1653
1654  let Inst{31-24} = enc{31-24};
1655}
1656
1657// RSE is like RSY except with a 12 bit displacement (instead of 20).
1658class DirectiveInsnRSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1659  : InstRSYa<6, outs, ins, asmstr, pattern> {
1660  bits <48> enc;
1661
1662  let Inst{47-40} = enc{47-40};
1663  let Inst{31-16} = BD2{15-0};
1664  let Inst{15-8}  = 0;
1665  let Inst{7-0}   = enc{7-0};
1666}
1667
1668class DirectiveInsnRSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1669  : InstRSI<0, outs, ins, asmstr, pattern> {
1670  bits<32> enc;
1671
1672  let Inst{31-24} = enc{31-24};
1673}
1674
1675class DirectiveInsnRSY<dag outs, dag ins, string asmstr, list<dag> pattern>
1676  : InstRSYa<0, outs, ins, asmstr, pattern> {
1677  bits<48> enc;
1678
1679  let Inst{47-40} = enc{47-40};
1680  let Inst{7-0}   = enc{7-0};
1681}
1682
1683class DirectiveInsnRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1684  : InstRXa<0, outs, ins, asmstr, pattern> {
1685  bits<32> enc;
1686
1687  let Inst{31-24} = enc{31-24};
1688}
1689
1690class DirectiveInsnRXE<dag outs, dag ins, string asmstr, list<dag> pattern>
1691  : InstRXE<0, outs, ins, asmstr, pattern> {
1692  bits<48> enc;
1693
1694  let M3 = 0;
1695
1696  let Inst{47-40} = enc{47-40};
1697  let Inst{7-0}   = enc{7-0};
1698}
1699
1700class DirectiveInsnRXF<dag outs, dag ins, string asmstr, list<dag> pattern>
1701  : InstRXF<0, outs, ins, asmstr, pattern> {
1702  bits<48> enc;
1703
1704  let Inst{47-40} = enc{47-40};
1705  let Inst{7-0}   = enc{7-0};
1706}
1707
1708class DirectiveInsnRXY<dag outs, dag ins, string asmstr, list<dag> pattern>
1709  : InstRXYa<0, outs, ins, asmstr, pattern> {
1710  bits<48> enc;
1711
1712  let Inst{47-40} = enc{47-40};
1713  let Inst{7-0}   = enc{7-0};
1714}
1715
1716class DirectiveInsnS<dag outs, dag ins, string asmstr, list<dag> pattern>
1717  : InstS<0, outs, ins, asmstr, pattern> {
1718  bits<32> enc;
1719
1720  let Inst{31-16} = enc{31-16};
1721}
1722
1723class DirectiveInsnSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1724  : InstSI<0, outs, ins, asmstr, pattern> {
1725  bits<32> enc;
1726
1727  let Inst{31-24} = enc{31-24};
1728}
1729
1730class DirectiveInsnSIY<dag outs, dag ins, string asmstr, list<dag> pattern>
1731  : InstSIY<0, outs, ins, asmstr, pattern> {
1732  bits<48> enc;
1733
1734  let Inst{47-40} = enc{47-40};
1735  let Inst{7-0}   = enc{7-0};
1736}
1737
1738class DirectiveInsnSIL<dag outs, dag ins, string asmstr, list<dag> pattern>
1739  : InstSIL<0, outs, ins, asmstr, pattern> {
1740  bits<48> enc;
1741
1742  let Inst{47-32} = enc{47-32};
1743}
1744
1745class DirectiveInsnSS<dag outs, dag ins, string asmstr, list<dag> pattern>
1746  : InstSSd<0, outs, ins, asmstr, pattern> {
1747  bits<48> enc;
1748
1749  let Inst{47-40} = enc{47-40};
1750}
1751
1752class DirectiveInsnSSE<dag outs, dag ins, string asmstr, list<dag> pattern>
1753  : InstSSE<0, outs, ins, asmstr, pattern> {
1754  bits<48> enc;
1755
1756  let Inst{47-32} = enc{47-32};
1757}
1758
1759class DirectiveInsnSSF<dag outs, dag ins, string asmstr, list<dag> pattern>
1760  : InstSSF<0, outs, ins, asmstr, pattern> {
1761  bits<48> enc;
1762
1763  let Inst{47-40} = enc{47-40};
1764  let Inst{35-32} = enc{35-32};
1765}
1766
1767class DirectiveInsnVRI<dag outs, dag ins, string asmstr, list<dag> pattern>
1768  : InstVRIe<0, outs, ins, asmstr, pattern> {
1769  bits<48> enc;
1770
1771  let Inst{47-40} = enc{47-40};
1772  let Inst{7-0}   = enc{7-0};
1773}
1774
1775class DirectiveInsnVRR<dag outs, dag ins, string asmstr, list<dag> pattern>
1776  : InstVRRc<0, outs, ins, asmstr, pattern> {
1777  bits<48> enc;
1778
1779  let Inst{47-40} = enc{47-40};
1780  let Inst{7-0}   = enc{7-0};
1781}
1782
1783class DirectiveInsnVRS<dag outs, dag ins, string asmstr, list<dag> pattern>
1784  : InstVRSc<0, outs, ins, asmstr, pattern> {
1785  bits<48> enc;
1786
1787  let Inst{47-40} = enc{47-40};
1788  let Inst{7-0}   = enc{7-0};
1789}
1790
1791class DirectiveInsnVRV<dag outs, dag ins, string asmstr, list<dag> pattern>
1792  : InstVRV<0, outs, ins, asmstr, pattern> {
1793  bits<48> enc;
1794
1795  let Inst{47-40} = enc{47-40};
1796  let Inst{7-0}   = enc{7-0};
1797}
1798
1799class DirectiveInsnVRX<dag outs, dag ins, string asmstr, list<dag> pattern>
1800  : InstVRX<0, outs, ins, asmstr, pattern> {
1801  bits<48> enc;
1802
1803  let Inst{47-40} = enc{47-40};
1804  let Inst{7-0}   = enc{7-0};
1805}
1806
1807class DirectiveInsnVSI<dag outs, dag ins, string asmstr, list<dag> pattern>
1808  : InstVSI<0, outs, ins, asmstr, pattern> {
1809  bits<48> enc;
1810
1811  let Inst{47-40} = enc{47-40};
1812  let Inst{7-0}   = enc{7-0};
1813}
1814
1815
1816//===----------------------------------------------------------------------===//
1817// Variants of instructions with condition mask
1818//===----------------------------------------------------------------------===//
1819//
1820// For instructions using a condition mask (e.g. conditional branches,
1821// compare-and-branch instructions, or conditional move instructions),
1822// we generally need to create multiple instruction patterns:
1823//
1824// - One used for code generation, which encodes the condition mask as an
1825//   MI operand, but writes out an extended mnemonic for better readability.
1826// - One pattern for the base form of the instruction with an explicit
1827//   condition mask (encoded as a plain integer MI operand).
1828// - Specific patterns for each extended mnemonic, where the condition mask
1829//   is implied by the pattern name and not otherwise encoded at all.
1830//
1831// We need the latter primarily for the assembler and disassembler, since the
1832// assembler parser is not able to decode part of an instruction mnemonic
1833// into an operand.  Thus we provide separate patterns for each mnemonic.
1834//
1835// Note that in some cases there are two different mnemonics for the same
1836// condition mask.  In this case we cannot have both instructions available
1837// to the disassembler at the same time since the encodings are not distinct.
1838// Therefore the alternate forms are marked isAsmParserOnly.
1839//
1840// We don't make one of the two names an alias of the other because
1841// we need the custom parsing routines to select the correct register class.
1842//
1843// This section provides helpers for generating the specific forms.
1844//
1845//===----------------------------------------------------------------------===//
1846
1847// A class to describe a variant of an instruction with condition mask.
1848class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
1849  // The fixed condition mask to use.
1850  bits<4> ccmask = ccmaskin;
1851
1852  // The suffix to use for the extended assembler mnemonic.
1853  string suffix = suffixin;
1854
1855  // Whether this is an alternate that needs to be marked isAsmParserOnly.
1856  bit alternate = alternatein;
1857}
1858
1859// Condition mask 15 means "always true", which is used to define
1860// unconditional branches as a variant of conditional branches.
1861def CondAlways : CondVariant<15, "", 0>;
1862
1863// Condition masks for general instructions that can set all 4 bits.
1864def CondVariantO   : CondVariant<1,  "o",   0>;
1865def CondVariantH   : CondVariant<2,  "h",   0>;
1866def CondVariantP   : CondVariant<2,  "p",   1>;
1867def CondVariantNLE : CondVariant<3,  "nle", 0>;
1868def CondVariantL   : CondVariant<4,  "l",   0>;
1869def CondVariantM   : CondVariant<4,  "m",   1>;
1870def CondVariantNHE : CondVariant<5,  "nhe", 0>;
1871def CondVariantLH  : CondVariant<6,  "lh",  0>;
1872def CondVariantNE  : CondVariant<7,  "ne",  0>;
1873def CondVariantNZ  : CondVariant<7,  "nz",  1>;
1874def CondVariantE   : CondVariant<8,  "e",   0>;
1875def CondVariantZ   : CondVariant<8,  "z",   1>;
1876def CondVariantNLH : CondVariant<9,  "nlh", 0>;
1877def CondVariantHE  : CondVariant<10, "he",  0>;
1878def CondVariantNL  : CondVariant<11, "nl",  0>;
1879def CondVariantNM  : CondVariant<11, "nm",  1>;
1880def CondVariantLE  : CondVariant<12, "le",  0>;
1881def CondVariantNH  : CondVariant<13, "nh",  0>;
1882def CondVariantNP  : CondVariant<13, "np",  1>;
1883def CondVariantNO  : CondVariant<14, "no",  0>;
1884
1885// A helper class to look up one of the above by name.
1886class CV<string name>
1887  : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
1888                !cast<CondVariant>("CondVariant"#name).suffix,
1889                !cast<CondVariant>("CondVariant"#name).alternate>;
1890
1891// Condition masks for integer instructions (e.g. compare-and-branch).
1892// This is like the list above, except that condition 3 is not possible
1893// and that the low bit of the mask is therefore always 0.  This means
1894// that each condition has two names.  Conditions "o" and "no" are not used.
1895def IntCondVariantH   : CondVariant<2,  "h",   0>;
1896def IntCondVariantNLE : CondVariant<2,  "nle", 1>;
1897def IntCondVariantL   : CondVariant<4,  "l",   0>;
1898def IntCondVariantNHE : CondVariant<4,  "nhe", 1>;
1899def IntCondVariantLH  : CondVariant<6,  "lh",  0>;
1900def IntCondVariantNE  : CondVariant<6,  "ne",  1>;
1901def IntCondVariantE   : CondVariant<8,  "e",   0>;
1902def IntCondVariantNLH : CondVariant<8,  "nlh", 1>;
1903def IntCondVariantHE  : CondVariant<10, "he",  0>;
1904def IntCondVariantNL  : CondVariant<10, "nl",  1>;
1905def IntCondVariantLE  : CondVariant<12, "le",  0>;
1906def IntCondVariantNH  : CondVariant<12, "nh",  1>;
1907
1908// A helper class to look up one of the above by name.
1909class ICV<string name>
1910  : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
1911                !cast<CondVariant>("IntCondVariant"#name).suffix,
1912                !cast<CondVariant>("IntCondVariant"#name).alternate>;
1913
1914// Defines a class that makes it easier to define
1915// a MnemonicAlias when CondVariant's are involved.
1916class MnemonicCondBranchAlias<CondVariant V, string from, string to>
1917  : MnemonicAlias<!subst("#", V.suffix, from), !subst("#", V.suffix, to)>;
1918
1919//===----------------------------------------------------------------------===//
1920// Instruction definitions with semantics
1921//===----------------------------------------------------------------------===//
1922//
1923// These classes have the form [Cond]<Category><Format>, where <Format> is one
1924// of the formats defined above and where <Category> describes the inputs
1925// and outputs.  "Cond" is used if the instruction is conditional,
1926// in which case the 4-bit condition-code mask is added as a final operand.
1927// <Category> can be one of:
1928//
1929//   Inherent:
1930//     One register output operand and no input operands.
1931//
1932//   InherentDual:
1933//     Two register output operands and no input operands.
1934//
1935//   StoreInherent:
1936//     One address operand.  The instruction stores to the address.
1937//
1938//   SideEffectInherent:
1939//     No input or output operands, but causes some side effect.
1940//
1941//   Branch:
1942//     One branch target.  The instruction branches to the target.
1943//
1944//   Call:
1945//     One output operand and one branch target.  The instruction stores
1946//     the return address to the output operand and branches to the target.
1947//
1948//   CmpBranch:
1949//     Two input operands and one optional branch target.  The instruction
1950//     compares the two input operands and branches or traps on the result.
1951//
1952//   BranchUnary:
1953//     One register output operand, one register input operand and one branch
1954//     target.  The instructions stores a modified form of the source register
1955//     in the destination register and branches on the result.
1956//
1957//   BranchBinary:
1958//     One register output operand, two register input operands and one branch
1959//     target. The instructions stores a modified form of one of the source
1960//     registers in the destination register and branches on the result.
1961//
1962//   LoadMultiple:
1963//     One address input operand and two explicit output operands.
1964//     The instruction loads a range of registers from the address,
1965//     with the explicit operands giving the first and last register
1966//     to load.  Other loaded registers are added as implicit definitions.
1967//
1968//   StoreMultiple:
1969//     Two explicit input register operands and an address operand.
1970//     The instruction stores a range of registers to the address,
1971//     with the explicit operands giving the first and last register
1972//     to store.  Other stored registers are added as implicit uses.
1973//
1974//   StoreLength:
1975//     One value operand, one length operand and one address operand.
1976//     The instruction stores the value operand to the address but
1977//     doesn't write more than the number of bytes specified by the
1978//     length operand.
1979//
1980//   LoadAddress:
1981//     One register output operand and one address operand.
1982//
1983//   SideEffectAddress:
1984//     One address operand.  No output operands, but causes some side effect.
1985//
1986//   Unary:
1987//     One register output operand and one input operand.
1988//
1989//   Store:
1990//     One address operand and one other input operand.  The instruction
1991//     stores to the address.
1992//
1993//   SideEffectUnary:
1994//     One input operand.  No output operands, but causes some side effect.
1995//
1996//   Binary:
1997//     One register output operand and two input operands.
1998//
1999//   StoreBinary:
2000//     One address operand and two other input operands.  The instruction
2001//     stores to the address.
2002//
2003//   SideEffectBinary:
2004//     Two input operands.  No output operands, but causes some side effect.
2005//
2006//   Compare:
2007//     Two input operands and an implicit CC output operand.
2008//
2009//   Test:
2010//     One or two input operands and an implicit CC output operand.  If
2011//     present, the second input operand is an "address" operand used as
2012//     a test class mask.
2013//
2014//   Ternary:
2015//     One register output operand and three input operands.
2016//
2017//   SideEffectTernary:
2018//     Three input operands.  No output operands, but causes some side effect.
2019//
2020//   Quaternary:
2021//     One register output operand and four input operands.
2022//
2023//   LoadAndOp:
2024//     One output operand and two input operands, one of which is an address.
2025//     The instruction both reads from and writes to the address.
2026//
2027//   CmpSwap:
2028//     One output operand and three input operands, one of which is an address.
2029//     The instruction both reads from and writes to the address.
2030//
2031//   RotateSelect:
2032//     One output operand and five input operands.  The first two operands
2033//     are registers and the other three are immediates.
2034//
2035//   Prefetch:
2036//     One 4-bit immediate operand and one address operand.  The immediate
2037//     operand is 1 for a load prefetch and 2 for a store prefetch.
2038//
2039//   BranchPreload:
2040//     One 4-bit immediate operand and two address operands.
2041//
2042// The format determines which input operands are tied to output operands,
2043// and also determines the shape of any address operand.
2044//
2045// Multiclasses of the form <Category><Format>Pair define two instructions,
2046// one with <Category><Format> and one with <Category><Format>Y.  The name
2047// of the first instruction has no suffix, the name of the second has
2048// an extra "y".
2049//
2050//===----------------------------------------------------------------------===//
2051
2052class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2053                  SDPatternOperator operator>
2054  : InstRRE<opcode, (outs cls:$R1), (ins),
2055            mnemonic#"\t$R1",
2056            [(set cls:$R1, (operator))]> {
2057  let R2 = 0;
2058}
2059
2060class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2061  : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2062            mnemonic#"\t$R1, $R2", []>;
2063
2064class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
2065  : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2066  let I2 = value;
2067  let M3 = 0;
2068}
2069
2070class StoreInherentS<string mnemonic, bits<16> opcode,
2071                     SDPatternOperator operator, bits<5> bytes>
2072  : InstS<opcode, (outs), (ins bdaddr12only:$BD2),
2073          mnemonic#"\t$BD2", [(operator bdaddr12only:$BD2)]> {
2074  let mayStore = 1;
2075  let AccessBytes = bytes;
2076}
2077
2078class SideEffectInherentE<string mnemonic, bits<16>opcode>
2079  : InstE<opcode, (outs), (ins), mnemonic, []>;
2080
2081class SideEffectInherentS<string mnemonic, bits<16> opcode,
2082                          SDPatternOperator operator>
2083  : InstS<opcode, (outs), (ins), mnemonic, [(operator)]> {
2084  let BD2 = 0;
2085}
2086
2087class SideEffectInherentRRE<string mnemonic, bits<16> opcode>
2088  : InstRRE<opcode, (outs), (ins), mnemonic, []> {
2089  let R1 = 0;
2090  let R2 = 0;
2091}
2092
2093// Allow an optional TLS marker symbol to generate TLS call relocations.
2094class CallRI<string mnemonic, bits<12> opcode>
2095  : InstRIb<opcode, (outs), (ins GR64:$R1, brtarget16tls:$RI2),
2096            mnemonic#"\t$R1, $RI2", []>;
2097
2098// Allow an optional TLS marker symbol to generate TLS call relocations.
2099class CallRIL<string mnemonic, bits<12> opcode>
2100  : InstRILb<opcode, (outs), (ins GR64:$R1, brtarget32tls:$RI2),
2101             mnemonic#"\t$R1, $RI2", []>;
2102
2103class CallRR<string mnemonic, bits<8> opcode>
2104  : InstRR<opcode, (outs), (ins GR64:$R1, ADDR64:$R2),
2105           mnemonic#"\t$R1, $R2", []>;
2106
2107class CallRX<string mnemonic, bits<8> opcode>
2108  : InstRXa<opcode, (outs), (ins GR64:$R1, bdxaddr12only:$XBD2),
2109            mnemonic#"\t$R1, $XBD2", []>;
2110
2111class CondBranchRI<string mnemonic, bits<12> opcode,
2112                   SDPatternOperator operator = null_frag>
2113  : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
2114            !subst("#", "${M1}", mnemonic)#"\t$RI2",
2115            [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
2116  let CCMaskFirst = 1;
2117}
2118
2119class AsmCondBranchRI<string mnemonic, bits<12> opcode>
2120  : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
2121            mnemonic#"\t$M1, $RI2", []>;
2122
2123class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
2124                        SDPatternOperator operator = null_frag>
2125  : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
2126            !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
2127  let isAsmParserOnly = V.alternate;
2128  let M1 = V.ccmask;
2129}
2130
2131class CondBranchRIL<string mnemonic, bits<12> opcode>
2132  : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
2133             !subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
2134  let CCMaskFirst = 1;
2135}
2136
2137class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
2138  : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
2139             mnemonic#"\t$M1, $RI2", []>;
2140
2141class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
2142  : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
2143             !subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
2144  let isAsmParserOnly = V.alternate;
2145  let M1 = V.ccmask;
2146}
2147
2148class CondBranchRR<string mnemonic, bits<8> opcode>
2149  : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
2150           !subst("#", "${R1}", mnemonic)#"\t$R2", []> {
2151  let CCMaskFirst = 1;
2152}
2153
2154class AsmCondBranchRR<string mnemonic, bits<8> opcode>
2155  : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
2156           mnemonic#"\t$R1, $R2", []>;
2157
2158class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
2159                      SDPatternOperator operator = null_frag>
2160  : InstRR<opcode, (outs), (ins ADDR64:$R2),
2161           !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
2162  let isAsmParserOnly = V.alternate;
2163  let R1 = V.ccmask;
2164}
2165
2166class CondBranchRX<string mnemonic, bits<8> opcode>
2167  : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
2168            !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
2169  let CCMaskFirst = 1;
2170}
2171
2172class AsmCondBranchRX<string mnemonic, bits<8> opcode>
2173  : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
2174            mnemonic#"\t$M1, $XBD2", []>;
2175
2176class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
2177  : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
2178            !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
2179  let isAsmParserOnly = V.alternate;
2180  let M1 = V.ccmask;
2181}
2182
2183class CondBranchRXY<string mnemonic, bits<16> opcode>
2184  : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
2185             !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
2186  let CCMaskFirst = 1;
2187  let mayLoad = 1;
2188}
2189
2190class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
2191  : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
2192             mnemonic#"\t$M1, $XBD2", []> {
2193  let mayLoad = 1;
2194}
2195
2196class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
2197                         SDPatternOperator operator = null_frag>
2198  : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
2199             !subst("#", V.suffix, mnemonic)#"\t$XBD2",
2200             [(operator (load bdxaddr20only:$XBD2))]> {
2201  let isAsmParserOnly = V.alternate;
2202  let M1 = V.ccmask;
2203  let mayLoad = 1;
2204}
2205
2206class CmpBranchRIEa<string mnemonic, bits<16> opcode,
2207                    RegisterOperand cls, ImmOpWithPattern imm>
2208  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2209             mnemonic#"$M3\t$R1, $I2", []>;
2210
2211class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
2212                       RegisterOperand cls, ImmOpWithPattern imm>
2213  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2214             mnemonic#"\t$R1, $I2, $M3", []>;
2215
2216class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
2217                          RegisterOperand cls, ImmOpWithPattern imm>
2218  : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2219             mnemonic#V.suffix#"\t$R1, $I2", []> {
2220  let isAsmParserOnly = V.alternate;
2221  let M3 = V.ccmask;
2222}
2223
2224multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
2225                             RegisterOperand cls, ImmOpWithPattern imm> {
2226  let isCodeGenOnly = 1 in
2227    def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
2228  def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
2229}
2230
2231class CmpBranchRIEb<string mnemonic, bits<16> opcode,
2232                    RegisterOperand cls>
2233  : InstRIEb<opcode, (outs),
2234             (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2235             mnemonic#"$M3\t$R1, $R2, $RI4", []>;
2236
2237class AsmCmpBranchRIEb<string mnemonic, bits<16> opcode,
2238                       RegisterOperand cls>
2239  : InstRIEb<opcode, (outs),
2240             (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
2241             mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
2242
2243class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
2244                         RegisterOperand cls>
2245  : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
2246             mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
2247  let isAsmParserOnly = V.alternate;
2248  let M3 = V.ccmask;
2249}
2250
2251multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
2252                             RegisterOperand cls> {
2253  let isCodeGenOnly = 1 in
2254    def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
2255  def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
2256}
2257
2258class CmpBranchRIEc<string mnemonic, bits<16> opcode,
2259                    RegisterOperand cls, ImmOpWithPattern imm>
2260  : InstRIEc<opcode, (outs),
2261             (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2262             mnemonic#"$M3\t$R1, $I2, $RI4", []>;
2263
2264class AsmCmpBranchRIEc<string mnemonic, bits<16> opcode,
2265                       RegisterOperand cls, ImmOpWithPattern imm>
2266  : InstRIEc<opcode, (outs),
2267             (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2268             mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
2269
2270class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
2271                         RegisterOperand cls, ImmOpWithPattern imm>
2272  : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2273             mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
2274  let isAsmParserOnly = V.alternate;
2275  let M3 = V.ccmask;
2276}
2277
2278multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
2279                            RegisterOperand cls, ImmOpWithPattern imm> {
2280  let isCodeGenOnly = 1 in
2281    def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
2282  def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
2283}
2284
2285class CmpBranchRRFc<string mnemonic, bits<16> opcode,
2286                    RegisterOperand cls>
2287  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2288             mnemonic#"$M3\t$R1, $R2", []>;
2289
2290class AsmCmpBranchRRFc<string mnemonic, bits<16> opcode,
2291                       RegisterOperand cls>
2292  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2293             mnemonic#"\t$R1, $R2, $M3", []>;
2294
2295multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
2296                             RegisterOperand cls> {
2297  let isCodeGenOnly = 1 in
2298    def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2299  def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2300}
2301
2302class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
2303                          RegisterOperand cls>
2304  : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2305             mnemonic#V.suffix#"\t$R1, $R2", []> {
2306  let isAsmParserOnly = V.alternate;
2307  let M3 = V.ccmask;
2308}
2309
2310class CmpBranchRRS<string mnemonic, bits<16> opcode,
2311                   RegisterOperand cls>
2312  : InstRRS<opcode, (outs),
2313            (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
2314            mnemonic#"$M3\t$R1, $R2, $BD4", []>;
2315
2316class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
2317                      RegisterOperand cls>
2318  : InstRRS<opcode, (outs),
2319            (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
2320            mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
2321
2322class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
2323                        RegisterOperand cls>
2324  : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
2325            mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
2326  let isAsmParserOnly = V.alternate;
2327  let M3 = V.ccmask;
2328}
2329
2330multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
2331                            RegisterOperand cls> {
2332  let isCodeGenOnly = 1 in
2333    def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2334  def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2335}
2336
2337class CmpBranchRIS<string mnemonic, bits<16> opcode,
2338                   RegisterOperand cls, ImmOpWithPattern imm>
2339  : InstRIS<opcode, (outs),
2340            (ins cls:$R1, imm:$I2, cond4:$M3, bdaddr12only:$BD4),
2341            mnemonic#"$M3\t$R1, $I2, $BD4", []>;
2342
2343class AsmCmpBranchRIS<string mnemonic, bits<16> opcode,
2344                      RegisterOperand cls, ImmOpWithPattern imm>
2345  : InstRIS<opcode, (outs),
2346            (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
2347            mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
2348
2349class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
2350                        RegisterOperand cls, ImmOpWithPattern imm>
2351  : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
2352            mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
2353  let isAsmParserOnly = V.alternate;
2354  let M3 = V.ccmask;
2355}
2356
2357multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
2358                            RegisterOperand cls, ImmOpWithPattern imm> {
2359  let isCodeGenOnly = 1 in
2360    def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2361  def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2362}
2363
2364class CmpBranchRSYb<string mnemonic, bits<16> opcode,
2365                    RegisterOperand cls>
2366  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, cond4:$M3),
2367             mnemonic#"$M3\t$R1, $BD2", []>;
2368
2369class AsmCmpBranchRSYb<string mnemonic, bits<16> opcode,
2370                       RegisterOperand cls>
2371  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2, imm32zx4:$M3),
2372             mnemonic#"\t$R1, $M3, $BD2", []>;
2373
2374multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
2375                             RegisterOperand cls> {
2376  let isCodeGenOnly = 1 in
2377    def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2378  def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2379}
2380
2381class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
2382                          RegisterOperand cls>
2383  : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
2384             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2385  let isAsmParserOnly = V.alternate;
2386  let M3 = V.ccmask;
2387}
2388
2389class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2390  : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
2391            mnemonic#"\t$R1, $RI2", []> {
2392  let Constraints = "$R1 = $R1src";
2393  let DisableEncoding = "$R1src";
2394}
2395
2396class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2397  : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
2398             mnemonic#"\t$R1, $RI2", []> {
2399  let Constraints = "$R1 = $R1src";
2400  let DisableEncoding = "$R1src";
2401}
2402
2403class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2404  : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2405           mnemonic#"\t$R1, $R2", []> {
2406  let Constraints = "$R1 = $R1src";
2407  let DisableEncoding = "$R1src";
2408}
2409
2410class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2411  : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2412            mnemonic#"\t$R1, $R2", []> {
2413  let Constraints = "$R1 = $R1src";
2414  let DisableEncoding = "$R1src";
2415}
2416
2417class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2418  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
2419            mnemonic#"\t$R1, $XBD2", []> {
2420  let Constraints = "$R1 = $R1src";
2421  let DisableEncoding = "$R1src";
2422}
2423
2424class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2425  : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr20only:$XBD2),
2426             mnemonic#"\t$R1, $XBD2", []> {
2427  let Constraints = "$R1 = $R1src";
2428  let DisableEncoding = "$R1src";
2429}
2430
2431class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2432  : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2433            mnemonic#"\t$R1, $R3, $RI2", []> {
2434  let Constraints = "$R1 = $R1src";
2435  let DisableEncoding = "$R1src";
2436}
2437
2438class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2439  : InstRIEe<opcode, (outs cls:$R1),
2440             (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2441             mnemonic#"\t$R1, $R3, $RI2", []> {
2442  let Constraints = "$R1 = $R1src";
2443  let DisableEncoding = "$R1src";
2444}
2445
2446class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2447  : InstRSa<opcode, (outs cls:$R1),
2448            (ins cls:$R1src, cls:$R3, bdaddr12only:$BD2),
2449            mnemonic#"\t$R1, $R3, $BD2", []> {
2450  let Constraints = "$R1 = $R1src";
2451  let DisableEncoding = "$R1src";
2452}
2453
2454class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2455  : InstRSYa<opcode,
2456             (outs cls:$R1), (ins cls:$R1src, cls:$R3, bdaddr20only:$BD2),
2457             mnemonic#"\t$R1, $R3, $BD2", []> {
2458  let Constraints = "$R1 = $R1src";
2459  let DisableEncoding = "$R1src";
2460}
2461
2462class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2463                     AddressingMode mode = bdaddr12only>
2464  : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2465            mnemonic#"\t$R1, $R3, $BD2", []> {
2466  let mayLoad = 1;
2467}
2468
2469class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2470                      AddressingMode mode = bdaddr20only>
2471  : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins mode:$BD2),
2472             mnemonic#"\t$R1, $R3, $BD2", []> {
2473  let mayLoad = 1;
2474}
2475
2476multiclass LoadMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2477                              bits<16> rsyOpcode, RegisterOperand cls> {
2478  let DispKey = mnemonic # cls in {
2479    let DispSize = "12" in
2480      def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2481    let DispSize = "20" in
2482      def Y  : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2483  }
2484}
2485
2486class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2487  : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2488            (ins bdaddr12only:$BD2, bdaddr12only:$BD4),
2489            mnemonic#"\t$R1, $R3, $BD2, $BD4", []> {
2490  let mayLoad = 1;
2491}
2492
2493multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2494  let mayLoad = 1 in {
2495    def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2496                        (ins bdaddr12only:$BD2, imm32zx4:$M4),
2497                        mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2498    let M4 = 0 in
2499      def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2500                        (ins bdaddr12only:$BD2),
2501                        mnemonic#"\t$V1, $V3, $BD2", []>;
2502  }
2503}
2504
2505class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2506                 RegisterOperand cls>
2507  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2508             mnemonic#"\t$R1, $RI2",
2509             [(operator cls:$R1, pcrel32:$RI2)]> {
2510  let mayStore = 1;
2511  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2512  // However, BDXs have two extra operands and are therefore 6 units more
2513  // complex.
2514  let AddedComplexity = 7;
2515}
2516
2517class StoreRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2518              RegisterOperand cls, bits<5> bytes,
2519              AddressingMode mode = bdxaddr12only>
2520  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2521            mnemonic#"\t$R1, $XBD2",
2522            [(operator cls:$R1, mode:$XBD2)]> {
2523  let OpKey = mnemonic#"r"#cls;
2524  let OpType = "mem";
2525  let mayStore = 1;
2526  let AccessBytes = bytes;
2527}
2528
2529class StoreRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2530               RegisterOperand cls, bits<5> bytes,
2531               AddressingMode mode = bdxaddr20only>
2532  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
2533             mnemonic#"\t$R1, $XBD2",
2534             [(operator cls:$R1, mode:$XBD2)]> {
2535  let OpKey = mnemonic#"r"#cls;
2536  let OpType = "mem";
2537  let mayStore = 1;
2538  let AccessBytes = bytes;
2539}
2540
2541multiclass StoreRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2542                       SDPatternOperator operator, RegisterOperand cls,
2543                       bits<5> bytes> {
2544  let DispKey = mnemonic # cls in {
2545    let DispSize = "12" in
2546      def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2547    let DispSize = "20" in
2548      def Y  : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2549                        bdxaddr20pair>;
2550  }
2551}
2552
2553class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2554               TypedReg tr, bits<5> bytes, bits<4> type = 0>
2555  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2),
2556            mnemonic#"\t$V1, $XBD2",
2557            [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2)]> {
2558  let M3 = type;
2559  let mayStore = 1;
2560  let AccessBytes = bytes;
2561}
2562
2563class StoreVRXGeneric<string mnemonic, bits<16> opcode>
2564  : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
2565            mnemonic#"\t$V1, $XBD2, $M3", []> {
2566  let mayStore = 1;
2567}
2568
2569multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> {
2570  let mayStore = 1, AccessBytes = 16 in {
2571    def Align : InstVRX<opcode, (outs),
2572                        (ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
2573                        mnemonic#"\t$V1, $XBD2, $M3", []>;
2574    let M3 = 0 in
2575      def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2),
2576                       mnemonic#"\t$V1, $XBD2", []>;
2577  }
2578}
2579
2580class StoreLengthVRSb<string mnemonic, bits<16> opcode,
2581                      SDPatternOperator operator, bits<5> bytes>
2582  : InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2583             mnemonic#"\t$V1, $R3, $BD2",
2584             [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2585  let M4 = 0;
2586  let mayStore = 1;
2587  let AccessBytes = bytes;
2588}
2589
2590class StoreLengthVRSd<string mnemonic, bits<16> opcode,
2591                      SDPatternOperator operator, bits<5> bytes>
2592  : InstVRSd<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
2593             mnemonic#"\t$V1, $R3, $BD2",
2594             [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2595  let mayStore = 1;
2596  let AccessBytes = bytes;
2597}
2598
2599class StoreLengthVSI<string mnemonic, bits<16> opcode,
2600                     SDPatternOperator operator, bits<5> bytes>
2601  : InstVSI<opcode, (outs), (ins VR128:$V1, bdaddr12only:$BD2, imm32zx8:$I3),
2602            mnemonic#"\t$V1, $BD2, $I3",
2603            [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
2604  let mayStore = 1;
2605  let AccessBytes = bytes;
2606}
2607
2608class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2609                      AddressingMode mode = bdaddr12only>
2610  : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2611            mnemonic#"\t$R1, $R3, $BD2", []> {
2612  let mayStore = 1;
2613}
2614
2615class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2616                       AddressingMode mode = bdaddr20only>
2617  : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, mode:$BD2),
2618             mnemonic#"\t$R1, $R3, $BD2", []> {
2619  let mayStore = 1;
2620}
2621
2622multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
2623                               bits<16> rsyOpcode, RegisterOperand cls> {
2624  let DispKey = mnemonic # cls in {
2625    let DispSize = "12" in
2626      def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2627    let DispSize = "20" in
2628      def Y  : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2629  }
2630}
2631
2632multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
2633  let mayStore = 1 in {
2634    def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2635                                              bdaddr12only:$BD2, imm32zx4:$M4),
2636                         mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2637    let M4 = 0 in
2638      def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2639                                             bdaddr12only:$BD2),
2640                        mnemonic#"\t$V1, $V3, $BD2", []>;
2641  }
2642}
2643
2644// StoreSI* instructions are used to store an integer to memory, but the
2645// addresses are more restricted than for normal stores.  If we are in the
2646// situation of having to force either the address into a register or the
2647// constant into a register, it's usually better to do the latter.
2648// We therefore match the address in the same way as a normal store and
2649// only use the StoreSI* instruction if the matched address is suitable.
2650class StoreSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2651              ImmOpWithPattern imm>
2652  : InstSI<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2653           mnemonic#"\t$BD1, $I2",
2654           [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2655  let mayStore = 1;
2656}
2657
2658class StoreSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2659               ImmOpWithPattern imm>
2660  : InstSIY<opcode, (outs), (ins mviaddr20pair:$BD1, imm:$I2),
2661            mnemonic#"\t$BD1, $I2",
2662            [(operator imm:$I2, mviaddr20pair:$BD1)]> {
2663  let mayStore = 1;
2664}
2665
2666class StoreSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2667               ImmOpWithPattern imm>
2668  : InstSIL<opcode, (outs), (ins mviaddr12pair:$BD1, imm:$I2),
2669            mnemonic#"\t$BD1, $I2",
2670            [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2671  let mayStore = 1;
2672}
2673
2674multiclass StoreSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
2675                       SDPatternOperator operator, ImmOpWithPattern imm> {
2676  let DispKey = mnemonic in {
2677    let DispSize = "12" in
2678      def "" : StoreSI<mnemonic, siOpcode, operator, imm>;
2679    let DispSize = "20" in
2680      def Y  : StoreSIY<mnemonic#"y", siyOpcode, operator, imm>;
2681  }
2682}
2683
2684class StoreSSE<string mnemonic, bits<16> opcode>
2685  : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
2686            mnemonic#"\t$BD1, $BD2", []> {
2687  let mayStore = 1;
2688}
2689
2690class CondStoreRSY<string mnemonic, bits<16> opcode,
2691                   RegisterOperand cls, bits<5> bytes,
2692                   AddressingMode mode = bdaddr20only>
2693  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$M3),
2694            mnemonic#"$M3\t$R1, $BD2", []> {
2695  let mayStore = 1;
2696  let AccessBytes = bytes;
2697  let CCMaskLast = 1;
2698}
2699
2700// Like CondStoreRSY, but used for the raw assembly form.  The condition-code
2701// mask is the third operand rather than being part of the mnemonic.
2702class AsmCondStoreRSY<string mnemonic, bits<16> opcode,
2703                      RegisterOperand cls, bits<5> bytes,
2704                      AddressingMode mode = bdaddr20only>
2705  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2, imm32zx4:$M3),
2706             mnemonic#"\t$R1, $BD2, $M3", []> {
2707  let mayStore = 1;
2708  let AccessBytes = bytes;
2709}
2710
2711// Like CondStoreRSY, but with a fixed CC mask.
2712class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
2713                        RegisterOperand cls, bits<5> bytes,
2714                        AddressingMode mode = bdaddr20only>
2715  : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
2716             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2717  let mayStore = 1;
2718  let AccessBytes = bytes;
2719  let isAsmParserOnly = V.alternate;
2720  let M3 = V.ccmask;
2721}
2722
2723multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
2724                            RegisterOperand cls, bits<5> bytes,
2725                            AddressingMode mode = bdaddr20only> {
2726  let isCodeGenOnly = 1 in
2727    def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2728  def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2729}
2730
2731class SideEffectUnaryI<string mnemonic, bits<8> opcode, ImmOpWithPattern imm>
2732  : InstI<opcode, (outs), (ins imm:$I1),
2733          mnemonic#"\t$I1", []>;
2734
2735class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2736  : InstRR<opcode, (outs), (ins cls:$R1),
2737           mnemonic#"\t$R1", []> {
2738  let R2 = 0;
2739}
2740
2741class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2742                         SDPatternOperator operator>
2743  : InstRRE<opcode, (outs), (ins cls:$R1),
2744            mnemonic#"\t$R1", [(operator cls:$R1)]> {
2745  let R2 = 0;
2746}
2747
2748class SideEffectUnaryS<string mnemonic, bits<16> opcode,
2749                       SDPatternOperator operator, bits<5> bytes,
2750                       AddressingMode mode = bdaddr12only>
2751  : InstS<opcode, (outs), (ins mode:$BD2),
2752          mnemonic#"\t$BD2", [(operator mode:$BD2)]> {
2753  let mayLoad = 1;
2754  let AccessBytes = bytes;
2755}
2756
2757class SideEffectAddressS<string mnemonic, bits<16> opcode,
2758                        SDPatternOperator operator,
2759                        AddressingMode mode = bdaddr12only>
2760  : InstS<opcode, (outs), (ins mode:$BD2),
2761          mnemonic#"\t$BD2", [(operator mode:$BD2)]>;
2762
2763class LoadAddressRX<string mnemonic, bits<8> opcode,
2764                    SDPatternOperator operator, AddressingMode mode>
2765  : InstRXa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2766            mnemonic#"\t$R1, $XBD2",
2767            [(set GR64:$R1, (operator mode:$XBD2))]>;
2768
2769class LoadAddressRXY<string mnemonic, bits<16> opcode,
2770                     SDPatternOperator operator, AddressingMode mode>
2771  : InstRXYa<opcode, (outs GR64:$R1), (ins mode:$XBD2),
2772             mnemonic#"\t$R1, $XBD2",
2773             [(set GR64:$R1, (operator mode:$XBD2))]>;
2774
2775multiclass LoadAddressRXPair<string mnemonic, bits<8> rxOpcode,
2776                             bits<16> rxyOpcode, SDPatternOperator operator> {
2777  let DispKey = mnemonic in {
2778    let DispSize = "12" in
2779      def "" : LoadAddressRX<mnemonic, rxOpcode, operator, laaddr12pair>;
2780    let DispSize = "20" in
2781      def Y  : LoadAddressRXY<mnemonic#"y", rxyOpcode, operator, laaddr20pair>;
2782  }
2783}
2784
2785class LoadAddressRIL<string mnemonic, bits<12> opcode,
2786                     SDPatternOperator operator>
2787  : InstRILb<opcode, (outs GR64:$R1), (ins pcrel32:$RI2),
2788             mnemonic#"\t$R1, $RI2",
2789             [(set GR64:$R1, (operator pcrel32:$RI2))]>;
2790
2791class UnaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2792              RegisterOperand cls1, RegisterOperand cls2>
2793  : InstRR<opcode, (outs cls1:$R1), (ins cls2:$R2),
2794           mnemonic#"\t$R1, $R2",
2795           [(set cls1:$R1, (operator cls2:$R2))]> {
2796  let OpKey = mnemonic#cls1;
2797  let OpType = "reg";
2798}
2799
2800class UnaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2801               RegisterOperand cls1, RegisterOperand cls2>
2802  : InstRRE<opcode, (outs cls1:$R1), (ins cls2:$R2),
2803            mnemonic#"\t$R1, $R2",
2804            [(set cls1:$R1, (operator cls2:$R2))]> {
2805  let OpKey = mnemonic#cls1;
2806  let OpType = "reg";
2807}
2808
2809class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2810  : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
2811            mnemonic#"\t$R1", []> {
2812  let Constraints = "$R1 = $R1src";
2813  let DisableEncoding = "$R1src";
2814  let R2 = 0;
2815}
2816
2817class UnaryMemRRFc<string mnemonic, bits<16> opcode,
2818                   RegisterOperand cls1, RegisterOperand cls2>
2819  : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src),
2820            mnemonic#"\t$R1, $R2", []> {
2821  let Constraints = "$R1 = $R1src";
2822  let DisableEncoding = "$R1src";
2823  let M3 = 0;
2824}
2825
2826class UnaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2827              RegisterOperand cls, ImmOpWithPattern imm>
2828  : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
2829            mnemonic#"\t$R1, $I2",
2830            [(set cls:$R1, (operator imm:$I2))]>;
2831
2832class UnaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2833               RegisterOperand cls, ImmOpWithPattern imm>
2834  : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
2835             mnemonic#"\t$R1, $I2",
2836             [(set cls:$R1, (operator imm:$I2))]>;
2837
2838class UnaryRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
2839                 RegisterOperand cls>
2840  : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
2841             mnemonic#"\t$R1, $RI2",
2842             [(set cls:$R1, (operator pcrel32:$RI2))]> {
2843  let mayLoad = 1;
2844  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
2845  // However, BDXs have two extra operands and are therefore 6 units more
2846  // complex.
2847  let AddedComplexity = 7;
2848}
2849
2850class CondUnaryRSY<string mnemonic, bits<16> opcode,
2851                   SDPatternOperator operator, RegisterOperand cls,
2852                   bits<5> bytes, AddressingMode mode = bdaddr20only>
2853  : InstRSYb<opcode, (outs cls:$R1),
2854             (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$M3),
2855             mnemonic#"$M3\t$R1, $BD2",
2856             [(set cls:$R1,
2857                   (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
2858                                    cond4:$valid, cond4:$M3))]> {
2859  let Constraints = "$R1 = $R1src";
2860  let DisableEncoding = "$R1src";
2861  let mayLoad = 1;
2862  let AccessBytes = bytes;
2863  let CCMaskLast = 1;
2864  let OpKey = mnemonic#"r"#cls;
2865  let OpType = "mem";
2866  let MemKey = mnemonic#cls;
2867  let MemType = "target";
2868}
2869
2870// Like CondUnaryRSY, but used for the raw assembly form.  The condition-code
2871// mask is the third operand rather than being part of the mnemonic.
2872class AsmCondUnaryRSY<string mnemonic, bits<16> opcode,
2873                      RegisterOperand cls, bits<5> bytes,
2874                      AddressingMode mode = bdaddr20only>
2875  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2, imm32zx4:$M3),
2876             mnemonic#"\t$R1, $BD2, $M3", []> {
2877  let mayLoad = 1;
2878  let AccessBytes = bytes;
2879  let Constraints = "$R1 = $R1src";
2880  let DisableEncoding = "$R1src";
2881}
2882
2883// Like CondUnaryRSY, but with a fixed CC mask.
2884class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
2885                        RegisterOperand cls, bits<5> bytes,
2886                        AddressingMode mode = bdaddr20only>
2887  : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
2888             mnemonic#V.suffix#"\t$R1, $BD2", []> {
2889  let Constraints = "$R1 = $R1src";
2890  let DisableEncoding = "$R1src";
2891  let mayLoad = 1;
2892  let AccessBytes = bytes;
2893  let isAsmParserOnly = V.alternate;
2894  let M3 = V.ccmask;
2895}
2896
2897multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
2898                            SDPatternOperator operator,
2899                            RegisterOperand cls, bits<5> bytes,
2900                            AddressingMode mode = bdaddr20only> {
2901  let isCodeGenOnly = 1 in
2902    def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
2903  def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
2904}
2905
2906class UnaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
2907              RegisterOperand cls, bits<5> bytes,
2908              AddressingMode mode = bdxaddr12only>
2909  : InstRXa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2910            mnemonic#"\t$R1, $XBD2",
2911            [(set cls:$R1, (operator mode:$XBD2))]> {
2912  let OpKey = mnemonic#"r"#cls;
2913  let OpType = "mem";
2914  let mayLoad = 1;
2915  let AccessBytes = bytes;
2916}
2917
2918class UnaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2919               RegisterOperand cls, bits<5> bytes>
2920  : InstRXE<opcode, (outs cls:$R1), (ins bdxaddr12only:$XBD2),
2921            mnemonic#"\t$R1, $XBD2",
2922            [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
2923  let OpKey = mnemonic#"r"#cls;
2924  let OpType = "mem";
2925  let mayLoad = 1;
2926  let AccessBytes = bytes;
2927  let M3 = 0;
2928}
2929
2930class UnaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2931               RegisterOperand cls, bits<5> bytes,
2932               AddressingMode mode = bdxaddr20only>
2933  : InstRXYa<opcode, (outs cls:$R1), (ins mode:$XBD2),
2934             mnemonic#"\t$R1, $XBD2",
2935             [(set cls:$R1, (operator mode:$XBD2))]> {
2936  let OpKey = mnemonic#"r"#cls;
2937  let OpType = "mem";
2938  let mayLoad = 1;
2939  let AccessBytes = bytes;
2940}
2941
2942multiclass UnaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
2943                       SDPatternOperator operator, RegisterOperand cls,
2944                       bits<5> bytes> {
2945  let DispKey = mnemonic # cls in {
2946    let DispSize = "12" in
2947      def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2948    let DispSize = "20" in
2949      def Y  : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2950                        bdxaddr20pair>;
2951  }
2952}
2953
2954class UnaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2955                TypedReg tr, ImmOpWithPattern imm, bits<4> type = 0>
2956  : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
2957             mnemonic#"\t$V1, $I2",
2958             [(set (tr.vt tr.op:$V1), (operator (i32 timm:$I2)))]> {
2959  let M3 = type;
2960}
2961
2962class UnaryVRIaGeneric<string mnemonic, bits<16> opcode, ImmOpWithPattern imm>
2963  : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
2964             mnemonic#"\t$V1, $I2, $M3", []>;
2965
2966class UnaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
2967                TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0,
2968                bits<4> m5 = 0, string fp_mnemonic = "">
2969  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2),
2970             mnemonic#"\t$V1, $V2",
2971             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]> {
2972  let M3 = type;
2973  let M4 = m4;
2974  let M5 = m5;
2975  let OpKey = fp_mnemonic#!subst("VR", "FP", !cast<string>(tr1.op));
2976  let OpType = "reg";
2977}
2978
2979class UnaryVRRaGeneric<string mnemonic, bits<16> opcode, bits<4> m4 = 0,
2980                       bits<4> m5 = 0>
2981  : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
2982             mnemonic#"\t$V1, $V2, $M3", []> {
2983  let M4 = m4;
2984  let M5 = m5;
2985}
2986
2987class UnaryVRRaFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0>
2988  : InstVRRa<opcode, (outs VR128:$V1),
2989             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
2990             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
2991  let M5 = m5;
2992}
2993
2994// Declare a pair of instructions, one which sets CC and one which doesn't.
2995// The CC-setting form ends with "S" and sets the low bit of M5.
2996// The form that does not set CC has an extra operand to optionally allow
2997// specifying arbitrary M5 values in assembler.
2998multiclass UnaryExtraVRRaSPair<string mnemonic, bits<16> opcode,
2999                               SDPatternOperator operator,
3000                               SDPatternOperator operator_cc,
3001                               TypedReg tr1, TypedReg tr2, bits<4> type> {
3002  let M3 = type, M4 = 0 in
3003    def "" : InstVRRa<opcode, (outs tr1.op:$V1),
3004                      (ins tr2.op:$V2, imm32zx4:$M5),
3005                      mnemonic#"\t$V1, $V2, $M5", []>;
3006  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2))),
3007            (!cast<Instruction>(NAME) tr2.op:$V2, 0)>;
3008  def : InstAlias<mnemonic#"\t$V1, $V2",
3009                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2, 0)>;
3010  let Defs = [CC] in
3011    def S : UnaryVRRa<mnemonic#"s", opcode, operator_cc, tr1, tr2,
3012                      type, 0, 1>;
3013}
3014
3015multiclass UnaryExtraVRRaSPairGeneric<string mnemonic, bits<16> opcode> {
3016  let M4 = 0, Defs = [CC] in
3017    def "" : InstVRRa<opcode, (outs VR128:$V1),
3018                     (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3019                     mnemonic#"\t$V1, $V2, $M3, $M5", []>;
3020  def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
3021                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
3022                                            imm32zx4:$M3, 0)>;
3023}
3024
3025class UnaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3026               TypedReg tr, bits<5> bytes, bits<4> type = 0>
3027  : InstVRX<opcode, (outs tr.op:$V1), (ins bdxaddr12only:$XBD2),
3028            mnemonic#"\t$V1, $XBD2",
3029            [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2))]> {
3030  let M3 = type;
3031  let mayLoad = 1;
3032  let AccessBytes = bytes;
3033}
3034
3035class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
3036  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3037            mnemonic#"\t$V1, $XBD2, $M3", []> {
3038  let mayLoad = 1;
3039}
3040
3041multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
3042  let mayLoad = 1, AccessBytes = 16 in {
3043    def Align : InstVRX<opcode, (outs VR128:$V1),
3044                        (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3045                        mnemonic#"\t$V1, $XBD2, $M3", []>;
3046    let M3 = 0 in
3047      def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2),
3048                       mnemonic#"\t$V1, $XBD2", []>;
3049  }
3050}
3051
3052class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
3053                         RegisterOperand cls>
3054  : InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3055            mnemonic#"\t$R1, $XBD2", []>;
3056
3057class SideEffectBinaryRXY<string mnemonic, bits<16> opcode,
3058                          RegisterOperand cls>
3059  : InstRXYa<opcode, (outs), (ins cls:$R1, bdxaddr20only:$XBD2),
3060             mnemonic#"\t$R1, $XBD2", []>;
3061
3062class SideEffectBinaryRILPC<string mnemonic, bits<12> opcode,
3063                            RegisterOperand cls>
3064  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3065             mnemonic#"\t$R1, $RI2", []> {
3066  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3067  // However, BDXs have two extra operands and are therefore 6 units more
3068  // complex.
3069  let AddedComplexity = 7;
3070}
3071
3072class SideEffectBinaryRRE<string mnemonic, bits<16> opcode,
3073                          RegisterOperand cls1, RegisterOperand cls2>
3074  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3075            mnemonic#"\t$R1, $R2", []>;
3076
3077class SideEffectBinaryRRFa<string mnemonic, bits<16> opcode,
3078                           RegisterOperand cls1, RegisterOperand cls2>
3079  : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3080             mnemonic#"\t$R1, $R2", []> {
3081  let R3 = 0;
3082  let M4 = 0;
3083}
3084
3085class SideEffectBinaryRRFc<string mnemonic, bits<16> opcode,
3086                           RegisterOperand cls1, RegisterOperand cls2>
3087  : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3088             mnemonic#"\t$R1, $R2", []> {
3089  let M3 = 0;
3090}
3091
3092class SideEffectBinaryIE<string mnemonic, bits<16> opcode,
3093                         ImmOpWithPattern imm1, ImmOpWithPattern imm2>
3094  : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
3095           mnemonic#"\t$I1, $I2", []>;
3096
3097class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
3098  : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3099           mnemonic#"\t$BD1, $I2", []>;
3100
3101class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
3102                          SDPatternOperator operator, ImmOpWithPattern imm>
3103  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
3104            mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
3105
3106class SideEffectBinarySSa<string mnemonic, bits<8> opcode>
3107  : InstSSa<opcode, (outs), (ins bdladdr12onlylen8:$BDL1, bdaddr12only:$BD2),
3108            mnemonic#"\t$BDL1, $BD2", []>;
3109
3110class SideEffectBinarySSb<string mnemonic, bits<8> opcode>
3111  : InstSSb<opcode,
3112            (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
3113            mnemonic#"\t$BDL1, $BDL2", []>;
3114
3115class SideEffectBinarySSf<string mnemonic, bits<8> opcode>
3116  : InstSSf<opcode, (outs), (ins bdaddr12only:$BD1, bdladdr12onlylen8:$BDL2),
3117            mnemonic#"\t$BD1, $BDL2", []>;
3118
3119class SideEffectBinarySSE<string mnemonic, bits<16> opcode>
3120  : InstSSE<opcode, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2),
3121            mnemonic#"\t$BD1, $BD2", []>;
3122
3123class SideEffectBinaryMemMemRR<string mnemonic, bits<8> opcode,
3124                               RegisterOperand cls1, RegisterOperand cls2>
3125  : InstRR<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3126           mnemonic#"\t$R1, $R2", []> {
3127    let Constraints = "$R1 = $R1src, $R2 = $R2src";
3128    let DisableEncoding = "$R1src, $R2src";
3129}
3130
3131class SideEffectBinaryMemRRE<string mnemonic, bits<16> opcode,
3132                             RegisterOperand cls1, RegisterOperand cls2>
3133  : InstRRE<opcode, (outs cls2:$R2), (ins cls1:$R1, cls2:$R2src),
3134            mnemonic#"\t$R1, $R2", []> {
3135  let Constraints = "$R2 = $R2src";
3136  let DisableEncoding = "$R2src";
3137}
3138
3139class SideEffectBinaryMemMemRRE<string mnemonic, bits<16> opcode,
3140                                RegisterOperand cls1, RegisterOperand cls2>
3141  : InstRRE<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3142            mnemonic#"\t$R1, $R2", []> {
3143    let Constraints = "$R1 = $R1src, $R2 = $R2src";
3144    let DisableEncoding = "$R1src, $R2src";
3145}
3146
3147class SideEffectBinaryMemMemRRFc<string mnemonic, bits<16> opcode,
3148                                 RegisterOperand cls1, RegisterOperand cls2>
3149  : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2), (ins cls1:$R1src, cls2:$R2src),
3150             mnemonic#"\t$R1, $R2", []> {
3151  let Constraints = "$R1 = $R1src, $R2 = $R2src";
3152  let DisableEncoding = "$R1src, $R2src";
3153  let M3 = 0;
3154}
3155
3156class BinaryRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3157               RegisterOperand cls1, RegisterOperand cls2>
3158  : InstRR<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3159           mnemonic#"\t$R1, $R2",
3160           [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3161  let OpKey = mnemonic#cls1;
3162  let OpType = "reg";
3163  let Constraints = "$R1 = $R1src";
3164  let DisableEncoding = "$R1src";
3165}
3166
3167class BinaryRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3168                RegisterOperand cls1, RegisterOperand cls2>
3169  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3170            mnemonic#"\t$R1, $R2",
3171            [(set cls1:$R1, (operator cls1:$R1src, cls2:$R2))]> {
3172  let OpKey = mnemonic#cls1;
3173  let OpType = "reg";
3174  let Constraints = "$R1 = $R1src";
3175  let DisableEncoding = "$R1src";
3176}
3177
3178class BinaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3179                RegisterOperand cls1, RegisterOperand cls2>
3180  : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R3, cls2:$R2),
3181            mnemonic#"\t$R1, $R3, $R2",
3182            [(set cls1:$R1, (operator cls2:$R3, cls2:$R2))]> {
3183  let OpKey = mnemonic#cls;
3184  let OpType = "reg";
3185}
3186
3187class BinaryRRFa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3188                 RegisterOperand cls1, RegisterOperand cls2,
3189                 RegisterOperand cls3>
3190  : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3191             mnemonic#"\t$R1, $R2, $R3",
3192             [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3193  let M4 = 0;
3194  let OpKey = mnemonic#cls1;
3195  let OpType = "reg";
3196}
3197
3198multiclass BinaryRRAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3199                        SDPatternOperator operator, RegisterOperand cls1,
3200                        RegisterOperand cls2> {
3201  let NumOpsKey = mnemonic in {
3202    let NumOpsValue = "3" in
3203      def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>,
3204              Requires<[FeatureDistinctOps]>;
3205    let NumOpsValue = "2" in
3206      def "" : BinaryRR<mnemonic, opcode1, operator, cls1, cls2>;
3207  }
3208}
3209
3210multiclass BinaryRREAndK<string mnemonic, bits<16> opcode1, bits<16> opcode2,
3211                         SDPatternOperator operator, RegisterOperand cls1,
3212                         RegisterOperand cls2> {
3213  let NumOpsKey = mnemonic in {
3214    let NumOpsValue = "3" in
3215      def K : BinaryRRFa<mnemonic#"k", opcode2, operator, cls1, cls1, cls2>,
3216              Requires<[FeatureDistinctOps]>;
3217    let NumOpsValue = "2" in
3218      def "" : BinaryRRE<mnemonic, opcode1, operator, cls1, cls2>;
3219  }
3220}
3221
3222class BinaryRRFb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3223                 RegisterOperand cls1, RegisterOperand cls2,
3224                 RegisterOperand cls3>
3225  : InstRRFb<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3),
3226             mnemonic#"\t$R1, $R3, $R2",
3227             [(set cls1:$R1, (operator cls2:$R2, cls3:$R3))]> {
3228  let M4 = 0;
3229}
3230
3231class BinaryRRFc<string mnemonic, bits<16> opcode,
3232                 RegisterOperand cls1, RegisterOperand cls2>
3233  : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3),
3234             mnemonic#"\t$R1, $R2, $M3", []>;
3235
3236class BinaryMemRRFc<string mnemonic, bits<16> opcode,
3237                    RegisterOperand cls1, RegisterOperand cls2, ImmOpWithPattern imm>
3238  : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3239            mnemonic#"\t$R1, $R2, $M3", []> {
3240  let Constraints = "$R1 = $R1src";
3241  let DisableEncoding = "$R1src";
3242}
3243
3244multiclass BinaryMemRRFcOpt<string mnemonic, bits<16> opcode,
3245                            RegisterOperand cls1, RegisterOperand cls2> {
3246  def "" : BinaryMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
3247  def Opt : UnaryMemRRFc<mnemonic, opcode, cls1, cls2>;
3248}
3249
3250class BinaryRRFd<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3251                RegisterOperand cls2>
3252  : InstRRFd<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M4),
3253             mnemonic#"\t$R1, $R2, $M4", []>;
3254
3255class BinaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3256                RegisterOperand cls2>
3257  : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3258             mnemonic#"\t$R1, $M3, $R2", []> {
3259  let M4 = 0;
3260}
3261
3262class CondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3263                   RegisterOperand cls2>
3264  : InstRRFc<opcode, (outs cls1:$R1),
3265             (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3266             mnemonic#"$M3\t$R1, $R2",
3267             [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
3268                                              cond4:$valid, cond4:$M3))]> {
3269  let Constraints = "$R1 = $R1src";
3270  let DisableEncoding = "$R1src";
3271  let CCMaskLast = 1;
3272  let NumOpsKey = !subst("loc", "sel", mnemonic);
3273  let NumOpsValue = "2";
3274  let OpKey = mnemonic#cls1;
3275  let OpType = "reg";
3276}
3277
3278// Like CondBinaryRRF, but used for the raw assembly form.  The condition-code
3279// mask is the third operand rather than being part of the mnemonic.
3280class AsmCondBinaryRRF<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3281                       RegisterOperand cls2>
3282  : InstRRFc<opcode, (outs cls1:$R1),
3283             (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
3284             mnemonic#"\t$R1, $R2, $M3", []> {
3285  let Constraints = "$R1 = $R1src";
3286  let DisableEncoding = "$R1src";
3287}
3288
3289// Like CondBinaryRRF, but with a fixed CC mask.
3290class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
3291                         RegisterOperand cls1, RegisterOperand cls2>
3292  : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
3293             mnemonic#V.suffix#"\t$R1, $R2", []> {
3294  let Constraints = "$R1 = $R1src";
3295  let DisableEncoding = "$R1src";
3296  let isAsmParserOnly = V.alternate;
3297  let M3 = V.ccmask;
3298}
3299
3300multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
3301                             RegisterOperand cls1, RegisterOperand cls2> {
3302  let isCodeGenOnly = 1 in
3303    def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3304  def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;
3305}
3306
3307class CondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3308                    RegisterOperand cls2, RegisterOperand cls3>
3309  : InstRRFa<opcode, (outs cls1:$R1),
3310             (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
3311             mnemonic#"$M4\t$R1, $R2, $R3",
3312             [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
3313                                              cond4:$valid, cond4:$M4))]> {
3314  let CCMaskLast = 1;
3315  let NumOpsKey = mnemonic;
3316  let NumOpsValue = "3";
3317  let OpKey = mnemonic#cls1;
3318  let OpType = "reg";
3319}
3320
3321// Like CondBinaryRRFa, but used for the raw assembly form.  The condition-code
3322// mask is the third operand rather than being part of the mnemonic.
3323class AsmCondBinaryRRFa<string mnemonic, bits<16> opcode, RegisterOperand cls1,
3324                        RegisterOperand cls2, RegisterOperand cls3>
3325  : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2, imm32zx4:$M4),
3326             mnemonic#"\t$R1, $R2, $R3, $M4", []>;
3327
3328// Like CondBinaryRRFa, but with a fixed CC mask.
3329class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode,
3330                         RegisterOperand cls1, RegisterOperand cls2,
3331                         RegisterOperand cls3>
3332  : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
3333             mnemonic#V.suffix#"\t$R1, $R2, $R3", []> {
3334  let isAsmParserOnly = V.alternate;
3335  let M4 = V.ccmask;
3336}
3337
3338multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode,
3339                             RegisterOperand cls1, RegisterOperand cls2,
3340                             RegisterOperand cls3> {
3341  let isCodeGenOnly = 1 in
3342    def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3343  def Asm : AsmCondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
3344}
3345
3346class BinaryRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3347               RegisterOperand cls, ImmOpWithPattern imm>
3348  : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3349            mnemonic#"\t$R1, $I2",
3350            [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3351  let Constraints = "$R1 = $R1src";
3352  let DisableEncoding = "$R1src";
3353}
3354
3355class BinaryRIE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3356                RegisterOperand cls, ImmOpWithPattern imm>
3357  : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3358             mnemonic#"\t$R1, $R3, $I2",
3359             [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3360
3361multiclass BinaryRIAndK<string mnemonic, bits<12> opcode1, bits<16> opcode2,
3362                        SDPatternOperator operator, RegisterOperand cls,
3363                        ImmOpWithPattern imm> {
3364  let NumOpsKey = mnemonic in {
3365    let NumOpsValue = "3" in
3366      def K : BinaryRIE<mnemonic#"k", opcode2, operator, cls, imm>,
3367              Requires<[FeatureDistinctOps]>;
3368    let NumOpsValue = "2" in
3369      def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
3370  }
3371}
3372
3373class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3374                    ImmOpWithPattern imm>
3375  : InstRIEg<opcode, (outs cls:$R1),
3376             (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3377             mnemonic#"$M3\t$R1, $I2",
3378             [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
3379                                             cond4:$valid, cond4:$M3))]> {
3380  let Constraints = "$R1 = $R1src";
3381  let DisableEncoding = "$R1src";
3382  let CCMaskLast = 1;
3383}
3384
3385// Like CondBinaryRIE, but used for the raw assembly form.  The condition-code
3386// mask is the third operand rather than being part of the mnemonic.
3387class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3388                       ImmOpWithPattern imm>
3389  : InstRIEg<opcode, (outs cls:$R1),
3390             (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3391             mnemonic#"\t$R1, $I2, $M3", []> {
3392  let Constraints = "$R1 = $R1src";
3393  let DisableEncoding = "$R1src";
3394}
3395
3396// Like CondBinaryRIE, but with a fixed CC mask.
3397class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
3398                         RegisterOperand cls, ImmOpWithPattern imm>
3399  : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3400             mnemonic#V.suffix#"\t$R1, $I2", []> {
3401  let Constraints = "$R1 = $R1src";
3402  let DisableEncoding = "$R1src";
3403  let isAsmParserOnly = V.alternate;
3404  let M3 = V.ccmask;
3405}
3406
3407multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
3408                             RegisterOperand cls, ImmOpWithPattern imm> {
3409  let isCodeGenOnly = 1 in
3410    def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3411  def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3412}
3413
3414class BinaryRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3415                RegisterOperand cls, ImmOpWithPattern imm>
3416  : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3417             mnemonic#"\t$R1, $I2",
3418             [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3419  let Constraints = "$R1 = $R1src";
3420  let DisableEncoding = "$R1src";
3421}
3422
3423class BinaryRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3424               RegisterOperand cls>
3425  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, shift12only:$BD2),
3426            mnemonic#"\t$R1, $BD2",
3427            [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
3428  let R3 = 0;
3429  let Constraints = "$R1 = $R1src";
3430  let DisableEncoding = "$R1src";
3431}
3432
3433class BinaryRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3434                RegisterOperand cls>
3435  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, shift20only:$BD2),
3436             mnemonic#"\t$R1, $R3, $BD2",
3437             [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
3438
3439multiclass BinaryRSAndK<string mnemonic, bits<8> opcode1, bits<16> opcode2,
3440                        SDPatternOperator operator, RegisterOperand cls> {
3441  let NumOpsKey = mnemonic in {
3442    let NumOpsValue = "3" in
3443      def K  : BinaryRSY<mnemonic#"k", opcode2, operator, cls>,
3444               Requires<[FeatureDistinctOps]>;
3445    let NumOpsValue = "2" in
3446      def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
3447  }
3448}
3449
3450class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3451  : InstRSLb<opcode, (outs cls:$R1),
3452             (ins bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
3453             mnemonic#"\t$R1, $BDL2, $M3", []> {
3454  let mayLoad = 1;
3455}
3456
3457class BinaryRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3458               RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3459               AddressingMode mode = bdxaddr12only>
3460  : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3461            mnemonic#"\t$R1, $XBD2",
3462            [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3463  let OpKey = mnemonic#"r"#cls;
3464  let OpType = "mem";
3465  let Constraints = "$R1 = $R1src";
3466  let DisableEncoding = "$R1src";
3467  let mayLoad = 1;
3468  let AccessBytes = bytes;
3469}
3470
3471class BinaryRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3472                  RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3473  : InstRXE<opcode, (outs cls:$R1), (ins cls:$R1src, bdxaddr12only:$XBD2),
3474            mnemonic#"\t$R1, $XBD2",
3475            [(set cls:$R1, (operator cls:$R1src,
3476                                     (load bdxaddr12only:$XBD2)))]> {
3477  let OpKey = mnemonic#"r"#cls;
3478  let OpType = "mem";
3479  let Constraints = "$R1 = $R1src";
3480  let DisableEncoding = "$R1src";
3481  let mayLoad = 1;
3482  let AccessBytes = bytes;
3483  let M3 = 0;
3484}
3485
3486class BinaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3487                RegisterOperand cls1, RegisterOperand cls2,
3488                SDPatternOperator load, bits<5> bytes>
3489  : InstRXF<opcode, (outs cls1:$R1), (ins cls2:$R3, bdxaddr12only:$XBD2),
3490            mnemonic#"\t$R1, $R3, $XBD2",
3491            [(set cls1:$R1, (operator cls2:$R3, (load bdxaddr12only:$XBD2)))]> {
3492  let OpKey = mnemonic#"r"#cls;
3493  let OpType = "mem";
3494  let mayLoad = 1;
3495  let AccessBytes = bytes;
3496}
3497
3498class BinaryRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3499                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3500                AddressingMode mode = bdxaddr20only>
3501  : InstRXYa<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$XBD2),
3502             mnemonic#"\t$R1, $XBD2",
3503             [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3504  let OpKey = mnemonic#"r"#cls;
3505  let OpType = "mem";
3506  let Constraints = "$R1 = $R1src";
3507  let DisableEncoding = "$R1src";
3508  let mayLoad = 1;
3509  let AccessBytes = bytes;
3510}
3511
3512multiclass BinaryRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3513                        SDPatternOperator operator, RegisterOperand cls,
3514                        SDPatternOperator load, bits<5> bytes> {
3515  let DispKey = mnemonic # cls in {
3516    let DispSize = "12" in
3517      def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
3518                        bdxaddr12pair>;
3519    let DispSize = "20" in
3520      def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
3521                         bdxaddr20pair>;
3522  }
3523}
3524
3525class BinarySI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3526               Operand imm, AddressingMode mode = bdaddr12only>
3527  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
3528           mnemonic#"\t$BD1, $I2",
3529           [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3530  let mayLoad = 1;
3531  let mayStore = 1;
3532}
3533
3534class BinarySIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3535                Operand imm, AddressingMode mode = bdaddr20only>
3536  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
3537            mnemonic#"\t$BD1, $I2",
3538            [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3539  let mayLoad = 1;
3540  let mayStore = 1;
3541}
3542
3543multiclass BinarySIPair<string mnemonic, bits<8> siOpcode,
3544                        bits<16> siyOpcode, SDPatternOperator operator,
3545                        Operand imm> {
3546  let DispKey = mnemonic # cls in {
3547    let DispSize = "12" in
3548      def "" : BinarySI<mnemonic, siOpcode, operator, imm, bdaddr12pair>;
3549    let DispSize = "20" in
3550      def Y  : BinarySIY<mnemonic#"y", siyOpcode, operator, imm, bdaddr20pair>;
3551  }
3552}
3553
3554class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3555  : InstSSF<opcode, (outs cls:$R3), (ins bdaddr12pair:$BD1, bdaddr12pair:$BD2),
3556            mnemonic#"\t$R3, $BD1, $BD2", []> {
3557  let mayLoad = 1;
3558}
3559
3560class BinaryVRIb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3561                 TypedReg tr, bits<4> type>
3562  : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
3563             mnemonic#"\t$V1, $I2, $I3",
3564             [(set (tr.vt tr.op:$V1), (operator imm32zx8_timm:$I2, imm32zx8_timm:$I3))]> {
3565  let M4 = type;
3566}
3567
3568class BinaryVRIbGeneric<string mnemonic, bits<16> opcode>
3569  : InstVRIb<opcode, (outs VR128:$V1),
3570             (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
3571             mnemonic#"\t$V1, $I2, $I3, $M4", []>;
3572
3573class BinaryVRIc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3574                 TypedReg tr1, TypedReg tr2, bits<4> type>
3575  : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3576             mnemonic#"\t$V1, $V3, $I2",
3577             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
3578                                                  imm32zx16_timm:$I2))]> {
3579  let M4 = type;
3580}
3581
3582class BinaryVRIcGeneric<string mnemonic, bits<16> opcode>
3583  : InstVRIc<opcode, (outs VR128:$V1),
3584             (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3585             mnemonic#"\t$V1, $V3, $I2, $M4", []>;
3586
3587class BinaryVRIe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3588                 TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m5>
3589  : InstVRIe<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx12:$I3),
3590             mnemonic#"\t$V1, $V2, $I3",
3591             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3592                                                  imm32zx12_timm:$I3))]> {
3593  let M4 = type;
3594  let M5 = m5;
3595}
3596
3597class BinaryVRIeFloatGeneric<string mnemonic, bits<16> opcode>
3598  : InstVRIe<opcode, (outs VR128:$V1),
3599             (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3600             mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>;
3601
3602class BinaryVRIh<string mnemonic, bits<16> opcode>
3603  : InstVRIh<opcode, (outs VR128:$V1),
3604             (ins imm32zx16:$I2, imm32zx4:$I3),
3605             mnemonic#"\t$V1, $I2, $I3", []>;
3606
3607class BinaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3608                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0>
3609  : InstVRRa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, imm32zx4:$M5),
3610             mnemonic#"\t$V1, $V2, $M5",
3611             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3612                                                  imm32zx12:$M5))]> {
3613  let M3 = type;
3614  let M4 = m4;
3615}
3616
3617class BinaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
3618  : InstVRRa<opcode, (outs VR128:$V1),
3619             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3620             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
3621
3622class BinaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3623                 TypedReg tr1, TypedReg tr2, bits<4> type = 0,
3624                 bits<4> modifier = 0>
3625  : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3626             mnemonic#"\t$V1, $V2, $V3",
3627             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3628                                                  (tr2.vt tr2.op:$V3)))]> {
3629  let M4 = type;
3630  let M5 = modifier;
3631}
3632
3633// Declare a pair of instructions, one which sets CC and one which doesn't.
3634// The CC-setting form ends with "S" and sets the low bit of M5.
3635multiclass BinaryVRRbSPair<string mnemonic, bits<16> opcode,
3636                           SDPatternOperator operator,
3637                           SDPatternOperator operator_cc, TypedReg tr1,
3638                           TypedReg tr2, bits<4> type, bits<4> modifier = 0> {
3639  def "" : BinaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
3640                      !and (modifier, 14)>;
3641  let Defs = [CC] in
3642    def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
3643                       !add (!and (modifier, 14), 1)>;
3644}
3645
3646class BinaryVRRbSPairGeneric<string mnemonic, bits<16> opcode>
3647  : InstVRRb<opcode, (outs VR128:$V1),
3648             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3649             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3650  let Defs = [CC];
3651}
3652
3653// Declare a pair of instructions, one which sets CC and one which doesn't.
3654// The CC-setting form ends with "S" and sets the low bit of M5.
3655// The form that does not set CC has an extra operand to optionally allow
3656// specifying arbitrary M5 values in assembler.
3657multiclass BinaryExtraVRRbSPair<string mnemonic, bits<16> opcode,
3658                                SDPatternOperator operator,
3659                                SDPatternOperator operator_cc,
3660                                TypedReg tr1, TypedReg tr2, bits<4> type> {
3661  let M4 = type in
3662    def "" : InstVRRb<opcode, (outs tr1.op:$V1),
3663                      (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
3664                      mnemonic#"\t$V1, $V2, $V3, $M5", []>;
3665  def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3666            (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
3667  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3668                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
3669                                            tr2.op:$V3, 0)>;
3670  let Defs = [CC] in
3671    def S : BinaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type, 1>;
3672}
3673
3674multiclass BinaryExtraVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
3675  let Defs = [CC] in
3676    def "" : InstVRRb<opcode, (outs VR128:$V1),
3677                     (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3678                     mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3679  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3680                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3681                                            imm32zx4:$M4, 0)>;
3682}
3683
3684class BinaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3685                 TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m5 = 0,
3686                 bits<4> m6 = 0, string fp_mnemonic = "">
3687  : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3688             mnemonic#"\t$V1, $V2, $V3",
3689             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
3690                                                  (tr2.vt tr2.op:$V3)))]> {
3691  let M4 = type;
3692  let M5 = m5;
3693  let M6 = m6;
3694  let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op));
3695  let OpType = "reg";
3696}
3697
3698class BinaryVRRcGeneric<string mnemonic, bits<16> opcode, bits<4> m5 = 0,
3699                        bits<4> m6 = 0>
3700  : InstVRRc<opcode, (outs VR128:$V1),
3701             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3702             mnemonic#"\t$V1, $V2, $V3, $M4", []> {
3703  let M5 = m5;
3704  let M6 = m6;
3705}
3706
3707class BinaryVRRcFloatGeneric<string mnemonic, bits<16> opcode, bits<4> m6 = 0>
3708  : InstVRRc<opcode, (outs VR128:$V1),
3709             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3710             mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3711  let M6 = m6;
3712}
3713
3714// Declare a pair of instructions, one which sets CC and one which doesn't.
3715// The CC-setting form ends with "S" and sets the low bit of M5.
3716multiclass BinaryVRRcSPair<string mnemonic, bits<16> opcode,
3717                           SDPatternOperator operator,
3718                           SDPatternOperator operator_cc, TypedReg tr1,
3719                           TypedReg tr2, bits<4> type, bits<4> m5,
3720                           bits<4> modifier = 0> {
3721  def "" : BinaryVRRc<mnemonic, opcode, operator, tr1, tr2, type,
3722                      m5, !and (modifier, 14)>;
3723  let Defs = [CC] in
3724    def S : BinaryVRRc<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
3725                       m5, !add (!and (modifier, 14), 1)>;
3726}
3727
3728class BinaryVRRcSPairFloatGeneric<string mnemonic, bits<16> opcode>
3729  : InstVRRc<opcode, (outs VR128:$V1),
3730             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
3731                  imm32zx4:$M6),
3732             mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
3733
3734class BinaryVRRf<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3735                 TypedReg tr>
3736  : InstVRRf<opcode, (outs tr.op:$V1), (ins GR64:$R2, GR64:$R3),
3737             mnemonic#"\t$V1, $R2, $R3",
3738             [(set (tr.vt tr.op:$V1), (operator GR64:$R2, GR64:$R3))]>;
3739
3740class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
3741  : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
3742             mnemonic#"\t$R1, $V2, $M3", []> {
3743  let M4 = 0;
3744}
3745
3746class BinaryVRSa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3747                 TypedReg tr1, TypedReg tr2, bits<4> type>
3748  : InstVRSa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, shift12only:$BD2),
3749             mnemonic#"\t$V1, $V3, $BD2",
3750             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
3751                                                  shift12only:$BD2))]> {
3752  let M4 = type;
3753}
3754
3755class BinaryVRSaGeneric<string mnemonic, bits<16> opcode>
3756  : InstVRSa<opcode, (outs VR128:$V1),
3757             (ins VR128:$V3, shift12only:$BD2, imm32zx4:$M4),
3758             mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
3759
3760class BinaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3761                 bits<5> bytes>
3762  : InstVRSb<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3763             mnemonic#"\t$V1, $R3, $BD2",
3764             [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3765  let M4 = 0;
3766  let mayLoad = 1;
3767  let AccessBytes = bytes;
3768}
3769
3770class BinaryVRSc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3771                 TypedReg tr, bits<4> type>
3772  : InstVRSc<opcode, (outs GR64:$R1), (ins tr.op:$V3, shift12only:$BD2),
3773           mnemonic#"\t$R1, $V3, $BD2",
3774           [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
3775  let M4 = type;
3776}
3777
3778class BinaryVRScGeneric<string mnemonic, bits<16> opcode>
3779  : InstVRSc<opcode, (outs GR64:$R1),
3780             (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4),
3781             mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
3782
3783class BinaryVRSd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3784                 bits<5> bytes>
3785  : InstVRSd<opcode, (outs VR128:$V1), (ins GR32:$R3, bdaddr12only:$BD2),
3786             mnemonic#"\t$V1, $R3, $BD2",
3787             [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
3788  let mayLoad = 1;
3789  let AccessBytes = bytes;
3790}
3791
3792class BinaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3793                TypedReg tr, bits<5> bytes>
3794  : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
3795            mnemonic#"\t$V1, $XBD2, $M3",
3796            [(set (tr.vt tr.op:$V1), (operator bdxaddr12only:$XBD2,
3797                                               imm32zx4_timm:$M3))]> {
3798  let mayLoad = 1;
3799  let AccessBytes = bytes;
3800}
3801
3802class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3803                    bits<5> bytes, AddressingMode mode = bdaddr12only>
3804  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3805            mnemonic#"\t$R1, $M3, $BD2", []> {
3806  let mayStore = 1;
3807  let AccessBytes = bytes;
3808}
3809
3810class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3811                     bits<5> bytes, AddressingMode mode = bdaddr20only>
3812  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3813             mnemonic#"\t$R1, $M3, $BD2", []> {
3814  let mayStore = 1;
3815  let AccessBytes = bytes;
3816}
3817
3818multiclass StoreBinaryRSPair<string mnemonic, bits<8> rsOpcode,
3819                             bits<16> rsyOpcode, RegisterOperand cls,
3820                             bits<5> bytes> {
3821  let DispKey = mnemonic # cls in {
3822    let DispSize = "12" in
3823      def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3824    let DispSize = "20" in
3825      def Y  : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
3826                              bdaddr20pair>;
3827  }
3828}
3829
3830class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3831  : InstRSLb<opcode, (outs),
3832             (ins cls:$R1, bdladdr12onlylen8:$BDL2, imm32zx4:$M3),
3833             mnemonic#"\t$R1, $BDL2, $M3", []> {
3834  let mayStore = 1;
3835}
3836
3837class BinaryVSI<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3838                bits<5> bytes>
3839  : InstVSI<opcode, (outs VR128:$V1), (ins bdaddr12only:$BD2, imm32zx8:$I3),
3840            mnemonic#"\t$V1, $BD2, $I3",
3841            [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
3842  let mayLoad = 1;
3843  let AccessBytes = bytes;
3844}
3845
3846class StoreBinaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
3847                     ImmOpWithPattern index>
3848  : InstVRV<opcode, (outs), (ins VR128:$V1, bdvaddr12only:$VBD2, index:$M3),
3849            mnemonic#"\t$V1, $VBD2, $M3", []> {
3850  let mayStore = 1;
3851  let AccessBytes = bytes;
3852}
3853
3854class StoreBinaryVRX<string mnemonic, bits<16> opcode,
3855                     SDPatternOperator operator, TypedReg tr, bits<5> bytes,
3856                     ImmOpWithPattern index>
3857  : InstVRX<opcode, (outs), (ins tr.op:$V1, bdxaddr12only:$XBD2, index:$M3),
3858            mnemonic#"\t$V1, $XBD2, $M3",
3859            [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
3860  let mayStore = 1;
3861  let AccessBytes = bytes;
3862}
3863
3864class MemoryBinarySSd<string mnemonic, bits<8> opcode,
3865                      RegisterOperand cls>
3866  : InstSSd<opcode, (outs),
3867            (ins bdraddr12only:$RBD1, bdaddr12only:$BD2, cls:$R3),
3868            mnemonic#"\t$RBD1, $BD2, $R3", []>;
3869
3870class CompareRR<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3871                RegisterOperand cls1, RegisterOperand cls2>
3872  : InstRR<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3873           mnemonic#"\t$R1, $R2",
3874           [(set CC, (operator cls1:$R1, cls2:$R2))]> {
3875  let OpKey = mnemonic#cls1;
3876  let OpType = "reg";
3877  let isCompare = 1;
3878}
3879
3880class CompareRRE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3881                 RegisterOperand cls1, RegisterOperand cls2>
3882  : InstRRE<opcode, (outs), (ins cls1:$R1, cls2:$R2),
3883            mnemonic#"\t$R1, $R2",
3884            [(set CC, (operator cls1:$R1, cls2:$R2))]> {
3885  let OpKey = mnemonic#cls1;
3886  let OpType = "reg";
3887  let isCompare = 1;
3888}
3889
3890class CompareRI<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3891                RegisterOperand cls, ImmOpWithPattern imm>
3892  : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
3893            mnemonic#"\t$R1, $I2",
3894            [(set CC, (operator cls:$R1, imm:$I2))]> {
3895  let isCompare = 1;
3896}
3897
3898class CompareRIL<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3899                 RegisterOperand cls, ImmOpWithPattern imm>
3900  : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
3901             mnemonic#"\t$R1, $I2",
3902             [(set CC, (operator cls:$R1, imm:$I2))]> {
3903  let isCompare = 1;
3904}
3905
3906class CompareRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
3907                   RegisterOperand cls, SDPatternOperator load>
3908  : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3909             mnemonic#"\t$R1, $RI2",
3910             [(set CC, (operator cls:$R1, (load pcrel32:$RI2)))]> {
3911  let isCompare = 1;
3912  let mayLoad = 1;
3913  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
3914  // However, BDXs have two extra operands and are therefore 6 units more
3915  // complex.
3916  let AddedComplexity = 7;
3917}
3918
3919class CompareRX<string mnemonic, bits<8> opcode, SDPatternOperator operator,
3920                RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3921                AddressingMode mode = bdxaddr12only>
3922  : InstRXa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3923            mnemonic#"\t$R1, $XBD2",
3924            [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
3925  let OpKey = mnemonic#"r"#cls;
3926  let OpType = "mem";
3927  let isCompare = 1;
3928  let mayLoad = 1;
3929  let AccessBytes = bytes;
3930}
3931
3932class CompareRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3933                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3934  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
3935            mnemonic#"\t$R1, $XBD2",
3936            [(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> {
3937  let OpKey = mnemonic#"r"#cls;
3938  let OpType = "mem";
3939  let isCompare = 1;
3940  let mayLoad = 1;
3941  let AccessBytes = bytes;
3942  let M3 = 0;
3943}
3944
3945class CompareRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
3946                 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3947                 AddressingMode mode = bdxaddr20only>
3948  : InstRXYa<opcode, (outs), (ins cls:$R1, mode:$XBD2),
3949             mnemonic#"\t$R1, $XBD2",
3950             [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
3951  let OpKey = mnemonic#"r"#cls;
3952  let OpType = "mem";
3953  let isCompare = 1;
3954  let mayLoad = 1;
3955  let AccessBytes = bytes;
3956}
3957
3958multiclass CompareRXPair<string mnemonic, bits<8> rxOpcode, bits<16> rxyOpcode,
3959                         SDPatternOperator operator, RegisterOperand cls,
3960                         SDPatternOperator load, bits<5> bytes> {
3961  let DispKey = mnemonic # cls in {
3962    let DispSize = "12" in
3963      def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
3964                         load, bytes, bdxaddr12pair>;
3965    let DispSize = "20" in
3966      def Y  : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
3967                          load, bytes, bdxaddr20pair>;
3968  }
3969}
3970
3971class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
3972                bits<5> bytes, AddressingMode mode = bdaddr12only>
3973  : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3974            mnemonic#"\t$R1, $M3, $BD2", []> {
3975  let mayLoad = 1;
3976  let AccessBytes = bytes;
3977}
3978
3979class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
3980                 bits<5> bytes, AddressingMode mode = bdaddr20only>
3981  : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, mode:$BD2),
3982             mnemonic#"\t$R1, $M3, $BD2", []> {
3983  let mayLoad = 1;
3984  let AccessBytes = bytes;
3985}
3986
3987multiclass CompareRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
3988                         RegisterOperand cls, bits<5> bytes> {
3989  let DispKey = mnemonic # cls in {
3990    let DispSize = "12" in
3991      def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
3992    let DispSize = "20" in
3993      def Y  : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
3994  }
3995}
3996
3997class CompareSSb<string mnemonic, bits<8> opcode>
3998  : InstSSb<opcode,
3999            (outs), (ins bdladdr12onlylen4:$BDL1, bdladdr12onlylen4:$BDL2),
4000            mnemonic#"\t$BDL1, $BDL2", []> {
4001  let isCompare = 1;
4002  let mayLoad = 1;
4003}
4004
4005class CompareSI<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4006                SDPatternOperator load, ImmOpWithPattern imm,
4007                AddressingMode mode = bdaddr12only>
4008  : InstSI<opcode, (outs), (ins mode:$BD1, imm:$I2),
4009           mnemonic#"\t$BD1, $I2",
4010           [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
4011  let isCompare = 1;
4012  let mayLoad = 1;
4013}
4014
4015class CompareSIL<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4016                 SDPatternOperator load, ImmOpWithPattern imm>
4017  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
4018            mnemonic#"\t$BD1, $I2",
4019            [(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> {
4020  let isCompare = 1;
4021  let mayLoad = 1;
4022}
4023
4024class CompareSIY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4025                 SDPatternOperator load, ImmOpWithPattern imm,
4026                 AddressingMode mode = bdaddr20only>
4027  : InstSIY<opcode, (outs), (ins mode:$BD1, imm:$I2),
4028            mnemonic#"\t$BD1, $I2",
4029            [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
4030  let isCompare = 1;
4031  let mayLoad = 1;
4032}
4033
4034multiclass CompareSIPair<string mnemonic, bits<8> siOpcode, bits<16> siyOpcode,
4035                         SDPatternOperator operator, SDPatternOperator load,
4036                         ImmOpWithPattern imm> {
4037  let DispKey = mnemonic in {
4038    let DispSize = "12" in
4039      def "" : CompareSI<mnemonic, siOpcode, operator, load, imm, bdaddr12pair>;
4040    let DispSize = "20" in
4041      def Y  : CompareSIY<mnemonic#"y", siyOpcode, operator, load, imm,
4042                          bdaddr20pair>;
4043  }
4044}
4045
4046class CompareVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4047                  TypedReg tr, bits<4> type, string fp_mnemonic = "">
4048  : InstVRRa<opcode, (outs), (ins tr.op:$V1, tr.op:$V2),
4049             mnemonic#"\t$V1, $V2",
4050             [(set CC, (operator (tr.vt tr.op:$V1), (tr.vt tr.op:$V2)))]> {
4051  let isCompare = 1;
4052  let M3 = type;
4053  let M4 = 0;
4054  let M5 = 0;
4055  let OpKey = fp_mnemonic#!subst("VR", "FP", !cast<string>(tr.op));
4056  let OpType = "reg";
4057}
4058
4059class CompareVRRaGeneric<string mnemonic, bits<16> opcode>
4060  : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4061             mnemonic#"\t$V1, $V2, $M3", []> {
4062  let isCompare = 1;
4063  let M4 = 0;
4064  let M5 = 0;
4065}
4066
4067class CompareVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4068  : InstVRRa<opcode, (outs),
4069             (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
4070             mnemonic#"\t$V1, $V2, $M3, $M4", []> {
4071  let isCompare = 1;
4072  let M5 = 0;
4073}
4074
4075class CompareVRRh<string mnemonic, bits<16> opcode>
4076  : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4077             mnemonic#"\t$V1, $V2, $M3", []> {
4078  let isCompare = 1;
4079}
4080
4081class TestInherentS<string mnemonic, bits<16> opcode,
4082                    SDPatternOperator operator>
4083  : InstS<opcode, (outs), (ins), mnemonic, [(set CC, (operator))]> {
4084  let BD2 = 0;
4085}
4086
4087class TestRXE<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4088              RegisterOperand cls>
4089  : InstRXE<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
4090            mnemonic#"\t$R1, $XBD2",
4091            [(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> {
4092  let M3 = 0;
4093}
4094
4095class TestBinarySIL<string mnemonic, bits<16> opcode,
4096                    SDPatternOperator operator, ImmOpWithPattern imm>
4097  : InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
4098            mnemonic#"\t$BD1, $I2",
4099            [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
4100
4101class TestRSL<string mnemonic, bits<16> opcode>
4102  : InstRSLa<opcode, (outs), (ins bdladdr12onlylen4:$BDL1),
4103             mnemonic#"\t$BDL1", []> {
4104  let mayLoad = 1;
4105}
4106
4107class TestVRRg<string mnemonic, bits<16> opcode>
4108  : InstVRRg<opcode, (outs), (ins VR128:$V1),
4109             mnemonic#"\t$V1", []>;
4110
4111class SideEffectTernarySSc<string mnemonic, bits<8> opcode>
4112  : InstSSc<opcode, (outs), (ins bdladdr12onlylen4:$BDL1,
4113                                 shift12only:$BD2, imm32zx4:$I3),
4114            mnemonic#"\t$BDL1, $BD2, $I3", []>;
4115
4116class SideEffectTernaryRRFa<string mnemonic, bits<16> opcode,
4117                            RegisterOperand cls1, RegisterOperand cls2,
4118                            RegisterOperand cls3>
4119  : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4120             mnemonic#"\t$R1, $R2, $R3", []> {
4121  let M4 = 0;
4122}
4123
4124class SideEffectTernaryMemMemRRFa<string mnemonic, bits<16> opcode,
4125                                  RegisterOperand cls1, RegisterOperand cls2,
4126                                  RegisterOperand cls3>
4127  : InstRRFa<opcode, (outs cls1:$R1, cls2:$R2),
4128             (ins cls1:$R1src, cls2:$R2src, cls3:$R3),
4129             mnemonic#"\t$R1, $R2, $R3", []> {
4130  let Constraints = "$R1 = $R1src, $R2 = $R2src";
4131  let DisableEncoding = "$R1src, $R2src";
4132  let M4 = 0;
4133}
4134
4135class SideEffectTernaryRRFb<string mnemonic, bits<16> opcode,
4136                            RegisterOperand cls1, RegisterOperand cls2,
4137                            RegisterOperand cls3>
4138  : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3),
4139             mnemonic#"\t$R1, $R3, $R2", []> {
4140  let M4 = 0;
4141}
4142
4143class SideEffectTernaryMemMemMemRRFb<string mnemonic, bits<16> opcode,
4144                                     RegisterOperand cls1,
4145                                     RegisterOperand cls2,
4146                                     RegisterOperand cls3>
4147  : InstRRFb<opcode, (outs cls1:$R1, cls2:$R2, cls3:$R3),
4148             (ins cls1:$R1src, cls2:$R2src, cls3:$R3src),
4149             mnemonic#"\t$R1, $R3, $R2", []> {
4150  let Constraints = "$R1 = $R1src, $R2 = $R2src, $R3 = $R3src";
4151  let DisableEncoding = "$R1src, $R2src, $R3src";
4152  let M4 = 0;
4153}
4154
4155class SideEffectTernaryRRFc<string mnemonic, bits<16> opcode,
4156                            RegisterOperand cls1, RegisterOperand cls2,
4157                            ImmOpWithPattern imm>
4158  : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4159             mnemonic#"\t$R1, $R2, $M3", []>;
4160
4161multiclass SideEffectTernaryRRFcOpt<string mnemonic, bits<16> opcode,
4162                                    RegisterOperand cls1,
4163                                    RegisterOperand cls2> {
4164  def "" : SideEffectTernaryRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4165  def Opt : SideEffectBinaryRRFc<mnemonic, opcode, cls1, cls2>;
4166}
4167
4168class SideEffectTernaryMemMemRRFc<string mnemonic, bits<16> opcode,
4169                                  RegisterOperand cls1, RegisterOperand cls2,
4170                                  ImmOpWithPattern imm>
4171  : InstRRFc<opcode, (outs cls1:$R1, cls2:$R2),
4172             (ins cls1:$R1src, cls2:$R2src, imm:$M3),
4173             mnemonic#"\t$R1, $R2, $M3", []> {
4174  let Constraints = "$R1 = $R1src, $R2 = $R2src";
4175  let DisableEncoding = "$R1src, $R2src";
4176}
4177
4178multiclass SideEffectTernaryMemMemRRFcOpt<string mnemonic, bits<16> opcode,
4179                                          RegisterOperand cls1,
4180                                          RegisterOperand cls2> {
4181  def "" : SideEffectTernaryMemMemRRFc<mnemonic, opcode, cls1, cls2, imm32zx4>;
4182  def Opt : SideEffectBinaryMemMemRRFc<mnemonic, opcode, cls1, cls2>;
4183}
4184
4185class SideEffectTernarySSF<string mnemonic, bits<12> opcode,
4186                           RegisterOperand cls>
4187  : InstSSF<opcode, (outs),
4188            (ins bdaddr12only:$BD1, bdaddr12only:$BD2, cls:$R3),
4189            mnemonic#"\t$BD1, $BD2, $R3", []>;
4190
4191class TernaryRRFa<string mnemonic, bits<16> opcode,
4192                 RegisterOperand cls1, RegisterOperand cls2,
4193                 RegisterOperand cls3>
4194  : InstRRFa<opcode, (outs cls1:$R1), (ins cls2:$R2, cls3:$R3, imm32zx4:$M4),
4195             mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4196
4197class TernaryRRFb<string mnemonic, bits<16> opcode,
4198                  RegisterOperand cls1, RegisterOperand cls2,
4199                  RegisterOperand cls3>
4200  : InstRRFb<opcode, (outs cls1:$R1, cls3:$R3),
4201             (ins cls1:$R1src, cls2:$R2, imm32zx4:$M4),
4202             mnemonic#"\t$R1, $R3, $R2, $M4", []> {
4203  let Constraints = "$R1 = $R1src";
4204  let DisableEncoding = "$R1src";
4205}
4206
4207class TernaryRRFe<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4208                  RegisterOperand cls2>
4209  : InstRRFe<opcode, (outs cls1:$R1),
4210             (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
4211             mnemonic#"\t$R1, $M3, $R2, $M4", []>;
4212
4213class TernaryRRD<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4214                 RegisterOperand cls1, RegisterOperand cls2>
4215  : InstRRD<opcode, (outs cls1:$R1), (ins cls2:$R1src, cls2:$R3, cls2:$R2),
4216            mnemonic#"\t$R1, $R3, $R2",
4217            [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3, cls2:$R2))]> {
4218  let OpKey = mnemonic#cls;
4219  let OpType = "reg";
4220  let Constraints = "$R1 = $R1src";
4221  let DisableEncoding = "$R1src";
4222}
4223
4224class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4225                bits<5> bytes, AddressingMode mode = bdaddr12only>
4226  : InstRSb<opcode, (outs cls:$R1),
4227            (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
4228            mnemonic#"\t$R1, $M3, $BD2", []> {
4229
4230  let Constraints = "$R1 = $R1src";
4231  let DisableEncoding = "$R1src";
4232  let mayLoad = 1;
4233  let AccessBytes = bytes;
4234}
4235
4236class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4237                bits<5> bytes, AddressingMode mode = bdaddr20only>
4238  : InstRSYb<opcode, (outs cls:$R1),
4239             (ins cls:$R1src, imm32zx4:$M3, mode:$BD2),
4240             mnemonic#"\t$R1, $M3, $BD2", []> {
4241
4242  let Constraints = "$R1 = $R1src";
4243  let DisableEncoding = "$R1src";
4244  let mayLoad = 1;
4245  let AccessBytes = bytes;
4246}
4247
4248multiclass TernaryRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4249                         RegisterOperand cls, bits<5> bytes> {
4250  let DispKey = mnemonic # cls in {
4251    let DispSize = "12" in
4252      def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4253    let DispSize = "20" in
4254      def Y  : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
4255  }
4256}
4257
4258class SideEffectTernaryRS<string mnemonic, bits<8> opcode,
4259                          RegisterOperand cls1, RegisterOperand cls2>
4260  : InstRSa<opcode, (outs),
4261            (ins cls1:$R1, cls2:$R3, bdaddr12only:$BD2),
4262            mnemonic#"\t$R1, $R3, $BD2", []>;
4263
4264class SideEffectTernaryRSY<string mnemonic, bits<16> opcode,
4265                           RegisterOperand cls1, RegisterOperand cls2>
4266  : InstRSYa<opcode, (outs),
4267             (ins cls1:$R1, cls2:$R3, bdaddr20only:$BD2),
4268             mnemonic#"\t$R1, $R3, $BD2", []>;
4269
4270class SideEffectTernaryMemMemRS<string mnemonic, bits<8> opcode,
4271                                RegisterOperand cls1, RegisterOperand cls2>
4272  : InstRSa<opcode, (outs cls1:$R1, cls2:$R3),
4273            (ins cls1:$R1src, cls2:$R3src, shift12only:$BD2),
4274            mnemonic#"\t$R1, $R3, $BD2", []> {
4275    let Constraints = "$R1 = $R1src, $R3 = $R3src";
4276    let DisableEncoding = "$R1src, $R3src";
4277}
4278
4279class SideEffectTernaryMemMemRSY<string mnemonic, bits<16> opcode,
4280                                 RegisterOperand cls1, RegisterOperand cls2>
4281  : InstRSYa<opcode, (outs cls1:$R1, cls2:$R3),
4282             (ins cls1:$R1src, cls2:$R3src, shift20only:$BD2),
4283             mnemonic#"\t$R1, $R3, $BD2", []> {
4284    let Constraints = "$R1 = $R1src, $R3 = $R3src";
4285    let DisableEncoding = "$R1src, $R3src";
4286}
4287
4288class TernaryRXF<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4289                 RegisterOperand cls1, RegisterOperand cls2,
4290                 SDPatternOperator load, bits<5> bytes>
4291  : InstRXF<opcode, (outs cls1:$R1),
4292            (ins cls2:$R1src, cls2:$R3, bdxaddr12only:$XBD2),
4293            mnemonic#"\t$R1, $R3, $XBD2",
4294            [(set cls1:$R1, (operator cls2:$R1src, cls2:$R3,
4295                                      (load bdxaddr12only:$XBD2)))]> {
4296  let OpKey = mnemonic#"r"#cls;
4297  let OpType = "mem";
4298  let Constraints = "$R1 = $R1src";
4299  let DisableEncoding = "$R1src";
4300  let mayLoad = 1;
4301  let AccessBytes = bytes;
4302}
4303
4304class TernaryVRIa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4305                  TypedReg tr1, TypedReg tr2, ImmOpWithPattern imm, ImmOpWithPattern index>
4306  : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4307             mnemonic#"\t$V1, $I2, $M3",
4308             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4309                                                  imm:$I2, index:$M3))]> {
4310  let Constraints = "$V1 = $V1src";
4311  let DisableEncoding = "$V1src";
4312}
4313
4314class TernaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4315                  TypedReg tr1, TypedReg tr2, bits<4> type>
4316  : InstVRId<opcode, (outs tr1.op:$V1),
4317             (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4318             mnemonic#"\t$V1, $V2, $V3, $I4",
4319             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4320                                                  (tr2.vt tr2.op:$V3),
4321                                                  imm32zx8_timm:$I4))]> {
4322  let M5 = type;
4323}
4324
4325class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4326  : InstVRIi<opcode, (outs VR128:$V1),
4327             (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4),
4328             mnemonic#"\t$V1, $R2, $I3, $M4", []>;
4329
4330class TernaryVRRa<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4331                  TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or>
4332  : InstVRRa<opcode, (outs tr1.op:$V1),
4333             (ins tr2.op:$V2, imm32zx4:$M4, imm32zx4:$M5),
4334             mnemonic#"\t$V1, $V2, $M4, $M5",
4335             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4336                                                  imm32zx4_timm:$M4,
4337                                                  imm32zx4_timm:$M5))],
4338             m4or> {
4339  let M3 = type;
4340}
4341
4342class TernaryVRRaFloatGeneric<string mnemonic, bits<16> opcode>
4343  : InstVRRa<opcode, (outs VR128:$V1),
4344             (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4345             mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4346
4347class TernaryVRRb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4348                  TypedReg tr1, TypedReg tr2, bits<4> type,
4349                  SDPatternOperator m5mask, bits<4> m5or>
4350  : InstVRRb<opcode, (outs tr1.op:$V1),
4351             (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
4352             mnemonic#"\t$V1, $V2, $V3, $M5",
4353             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4354                                                  (tr2.vt tr2.op:$V3),
4355                                                  m5mask:$M5))],
4356             m5or> {
4357  let M4 = type;
4358}
4359
4360// Declare a pair of instructions, one which sets CC and one which doesn't.
4361// The CC-setting form ends with "S" and sets the low bit of M5.
4362// Also create aliases to make use of M5 operand optional in assembler.
4363multiclass TernaryOptVRRbSPair<string mnemonic, bits<16> opcode,
4364                               SDPatternOperator operator,
4365                               SDPatternOperator operator_cc,
4366                               TypedReg tr1, TypedReg tr2, bits<4> type,
4367                               bits<4> modifier = 0> {
4368  def "" : TernaryVRRb<mnemonic, opcode, operator, tr1, tr2, type,
4369                       imm32zx4even_timm, !and (modifier, 14)>;
4370  def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
4371                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4372                                            tr2.op:$V3, 0)>;
4373  let Defs = [CC] in
4374    def S : TernaryVRRb<mnemonic#"s", opcode, operator_cc, tr1, tr2, type,
4375                        imm32zx4even_timm, !add(!and (modifier, 14), 1)>;
4376  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
4377                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4378                                                tr2.op:$V3, 0)>;
4379}
4380
4381multiclass TernaryOptVRRbSPairGeneric<string mnemonic, bits<16> opcode> {
4382  let Defs = [CC] in
4383    def "" : InstVRRb<opcode, (outs VR128:$V1),
4384                     (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4385                     mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
4386  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
4387                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4388                                            imm32zx4:$M4, 0)>;
4389}
4390
4391class TernaryVRRc<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4392                  TypedReg tr1, TypedReg tr2>
4393  : InstVRRc<opcode, (outs tr1.op:$V1),
4394             (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
4395             mnemonic#"\t$V1, $V2, $V3, $M4",
4396             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4397                                                  (tr2.vt tr2.op:$V3),
4398                                                  imm32zx4_timm:$M4))]> {
4399  let M5 = 0;
4400  let M6 = 0;
4401}
4402
4403class TernaryVRRcFloat<string mnemonic, bits<16> opcode,
4404                       SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
4405                       bits<4> type = 0, bits<4> m5 = 0>
4406  : InstVRRc<opcode, (outs tr1.op:$V1),
4407             (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
4408             mnemonic#"\t$V1, $V2, $V3, $M6",
4409             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4410                                                  (tr2.vt tr2.op:$V3),
4411                                                  imm32zx4_timm:$M6))]> {
4412  let M4 = type;
4413  let M5 = m5;
4414}
4415
4416class TernaryVRRcFloatGeneric<string mnemonic, bits<16> opcode>
4417  : InstVRRc<opcode, (outs VR128:$V1),
4418             (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4419                  imm32zx4:$M6),
4420             mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4421
4422class TernaryVRRd<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4423                  TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m6 = 0>
4424  : InstVRRd<opcode, (outs tr1.op:$V1),
4425             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4426             mnemonic#"\t$V1, $V2, $V3, $V4",
4427             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4428                                                  (tr2.vt tr2.op:$V3),
4429                                                  (tr1.vt tr1.op:$V4)))]> {
4430  let M5 = type;
4431  let M6 = m6;
4432}
4433
4434class TernaryVRRdGeneric<string mnemonic, bits<16> opcode>
4435  : InstVRRd<opcode, (outs VR128:$V1),
4436             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4437             mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
4438  let M6 = 0;
4439}
4440
4441// Ternary operation where the assembler mnemonic has an extra operand to
4442// optionally allow specifying arbitrary M6 values.
4443multiclass TernaryExtraVRRd<string mnemonic, bits<16> opcode,
4444                             SDPatternOperator operator,
4445                             TypedReg tr1, TypedReg tr2, bits<4> type> {
4446  let M5 = type, Defs = [CC] in
4447    def "" : InstVRRd<opcode, (outs tr1.op:$V1),
4448                      (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6),
4449                      mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>;
4450  def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3),
4451                      (tr1.vt tr1.op:$V4)),
4452            (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>;
4453  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4454                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4455                                            tr2.op:$V3, tr1.op:$V4, 0)>;
4456}
4457
4458multiclass TernaryExtraVRRdGeneric<string mnemonic, bits<16> opcode> {
4459  let Defs = [CC] in
4460    def "" : InstVRRd<opcode, (outs VR128:$V1),
4461                      (ins VR128:$V2, VR128:$V3, VR128:$V4,
4462                       imm32zx4:$M5, imm32zx4:$M6),
4463                      mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4464  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4465                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4466                                            VR128:$V4, imm32zx4:$M5, 0)>;
4467}
4468
4469class TernaryVRRe<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4470                  TypedReg tr1, TypedReg tr2, bits<4> m5 = 0, bits<4> type = 0,
4471                  string fp_mnemonic = "">
4472  : InstVRRe<opcode, (outs tr1.op:$V1),
4473             (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4474             mnemonic#"\t$V1, $V2, $V3, $V4",
4475             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4476                                                  (tr2.vt tr2.op:$V3),
4477                                                  (tr1.vt tr1.op:$V4)))]> {
4478  let M5 = m5;
4479  let M6 = type;
4480  let OpKey = fp_mnemonic#"MemFold"#!subst("VR", "FP", !cast<string>(tr1.op));
4481  let OpType = "reg";
4482}
4483
4484class TernaryVRReFloatGeneric<string mnemonic, bits<16> opcode>
4485  : InstVRRe<opcode, (outs VR128:$V1),
4486             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4487             mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4488
4489class TernaryVRSb<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4490                  TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
4491  : InstVRSb<opcode, (outs tr1.op:$V1),
4492             (ins tr2.op:$V1src, cls:$R3, shift12only:$BD2),
4493             mnemonic#"\t$V1, $R3, $BD2",
4494             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4495                                                  cls:$R3,
4496                                                  shift12only:$BD2))]> {
4497  let Constraints = "$V1 = $V1src";
4498  let DisableEncoding = "$V1src";
4499  let M4 = type;
4500}
4501
4502class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4503  : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4504                                      imm32zx4:$M3, imm32zx4:$M4),
4505             mnemonic#"\t$R1, $V2, $M3, $M4", []>;
4506
4507class TernaryVRSbGeneric<string mnemonic, bits<16> opcode>
4508  : InstVRSb<opcode, (outs VR128:$V1),
4509             (ins VR128:$V1src, GR64:$R3, shift12only:$BD2, imm32zx4:$M4),
4510             mnemonic#"\t$V1, $R3, $BD2, $M4", []> {
4511  let Constraints = "$V1 = $V1src";
4512  let DisableEncoding = "$V1src";
4513}
4514
4515class TernaryVRV<string mnemonic, bits<16> opcode, bits<5> bytes,
4516                 ImmOpWithPattern index>
4517  : InstVRV<opcode, (outs VR128:$V1),
4518           (ins VR128:$V1src, bdvaddr12only:$VBD2, index:$M3),
4519           mnemonic#"\t$V1, $VBD2, $M3", []> {
4520  let Constraints = "$V1 = $V1src";
4521  let DisableEncoding = "$V1src";
4522  let mayLoad = 1;
4523  let AccessBytes = bytes;
4524}
4525
4526class TernaryVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4527                 TypedReg tr1, TypedReg tr2, bits<5> bytes, ImmOpWithPattern index>
4528  : InstVRX<opcode, (outs tr1.op:$V1),
4529           (ins tr2.op:$V1src, bdxaddr12only:$XBD2, index:$M3),
4530           mnemonic#"\t$V1, $XBD2, $M3",
4531           [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4532                                                bdxaddr12only:$XBD2,
4533                                                index:$M3))]> {
4534  let Constraints = "$V1 = $V1src";
4535  let DisableEncoding = "$V1src";
4536  let mayLoad = 1;
4537  let AccessBytes = bytes;
4538}
4539
4540class QuaternaryVRId<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4541                     TypedReg tr1, TypedReg tr2, bits<4> type>
4542  : InstVRId<opcode, (outs tr1.op:$V1),
4543             (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4544             mnemonic#"\t$V1, $V2, $V3, $I4",
4545             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V1src),
4546                                                  (tr2.vt tr2.op:$V2),
4547                                                  (tr2.vt tr2.op:$V3),
4548                                                  imm32zx8_timm:$I4))]> {
4549  let Constraints = "$V1 = $V1src";
4550  let DisableEncoding = "$V1src";
4551  let M5 = type;
4552}
4553
4554class QuaternaryVRIdGeneric<string mnemonic, bits<16> opcode>
4555  : InstVRId<opcode, (outs VR128:$V1),
4556             (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4557                  imm32zx8:$I4, imm32zx4:$M5),
4558             mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
4559  let Constraints = "$V1 = $V1src";
4560  let DisableEncoding = "$V1src";
4561}
4562
4563class QuaternaryVRIf<string mnemonic, bits<16> opcode>
4564  : InstVRIf<opcode, (outs VR128:$V1),
4565             (ins VR128:$V2, VR128:$V3,
4566                  imm32zx8:$I4, imm32zx4:$M5),
4567            mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>;
4568
4569class QuaternaryVRIg<string mnemonic, bits<16> opcode>
4570  : InstVRIg<opcode, (outs VR128:$V1),
4571             (ins VR128:$V2, imm32zx8:$I3,
4572                  imm32zx8:$I4, imm32zx4:$M5),
4573             mnemonic#"\t$V1, $V2, $I3, $I4, $M5", []>;
4574
4575class QuaternaryVRRd<string mnemonic, bits<16> opcode,
4576                     SDPatternOperator operator, TypedReg tr1, TypedReg tr2,
4577                     TypedReg tr3, TypedReg tr4, bits<4> type,
4578                     SDPatternOperator m6mask = imm32zx4_timm, bits<4> m6or = 0>
4579  : InstVRRd<opcode, (outs tr1.op:$V1),
4580             (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
4581             mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
4582             [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2),
4583                                                  (tr3.vt tr3.op:$V3),
4584                                                  (tr4.vt tr4.op:$V4),
4585                                                  m6mask:$M6))],
4586             m6or> {
4587  let M5 = type;
4588}
4589
4590class QuaternaryVRRdGeneric<string mnemonic, bits<16> opcode>
4591  : InstVRRd<opcode, (outs VR128:$V1),
4592             (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4593             mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4594
4595// Declare a pair of instructions, one which sets CC and one which doesn't.
4596// The CC-setting form ends with "S" and sets the low bit of M6.
4597// Also create aliases to make use of M6 operand optional in assembler.
4598multiclass QuaternaryOptVRRdSPair<string mnemonic, bits<16> opcode,
4599                                  SDPatternOperator operator,
4600                                SDPatternOperator operator_cc,
4601                                TypedReg tr1, TypedReg tr2, bits<4> type,
4602                                bits<4> modifier = 0> {
4603  def "" : QuaternaryVRRd<mnemonic, opcode, operator,
4604                          tr1, tr2, tr2, tr2, type,
4605                          imm32zx4even_timm, !and (modifier, 14)>;
4606  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4607                  (!cast<Instruction>(NAME) tr1.op:$V1, tr2.op:$V2,
4608                                            tr2.op:$V3, tr2.op:$V4, 0)>;
4609  let Defs = [CC] in
4610    def S : QuaternaryVRRd<mnemonic#"s", opcode, operator_cc,
4611                           tr1, tr2, tr2, tr2, type,
4612                           imm32zx4even_timm, !add (!and (modifier, 14), 1)>;
4613  def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4614                  (!cast<Instruction>(NAME#"S") tr1.op:$V1, tr2.op:$V2,
4615                                                tr2.op:$V3, tr2.op:$V4, 0)>;
4616}
4617
4618multiclass QuaternaryOptVRRdSPairGeneric<string mnemonic, bits<16> opcode> {
4619  let Defs = [CC] in
4620    def "" : QuaternaryVRRdGeneric<mnemonic, opcode>;
4621  def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4622                  (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4623                                            VR128:$V4, imm32zx4_timm:$M5, 0)>;
4624}
4625
4626class SideEffectQuaternaryRRFa<string mnemonic, bits<16> opcode,
4627                               RegisterOperand cls1, RegisterOperand cls2,
4628                               RegisterOperand cls3>
4629  : InstRRFa<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4630             mnemonic#"\t$R1, $R2, $R3, $M4", []>;
4631
4632multiclass SideEffectQuaternaryRRFaOptOpt<string mnemonic, bits<16> opcode,
4633                                          RegisterOperand cls1,
4634                                          RegisterOperand cls2,
4635                                          RegisterOperand cls3> {
4636  def "" : SideEffectQuaternaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4637  def Opt : SideEffectTernaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;
4638  def OptOpt : SideEffectBinaryRRFa<mnemonic, opcode, cls1, cls2>;
4639}
4640
4641class SideEffectQuaternaryRRFb<string mnemonic, bits<16> opcode,
4642                               RegisterOperand cls1, RegisterOperand cls2,
4643                               RegisterOperand cls3>
4644  : InstRRFb<opcode, (outs), (ins cls1:$R1, cls2:$R2, cls3:$R3, imm32zx4:$M4),
4645             mnemonic#"\t$R1, $R3, $R2, $M4", []>;
4646
4647multiclass SideEffectQuaternaryRRFbOpt<string mnemonic, bits<16> opcode,
4648                                       RegisterOperand cls1,
4649                                       RegisterOperand cls2,
4650                                       RegisterOperand cls3> {
4651  def "" : SideEffectQuaternaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4652  def Opt : SideEffectTernaryRRFb<mnemonic, opcode, cls1, cls2, cls3>;
4653}
4654
4655class SideEffectQuaternarySSe<string mnemonic, bits<8> opcode,
4656                              RegisterOperand cls>
4657  : InstSSe<opcode, (outs),
4658            (ins cls:$R1, bdaddr12only:$BD2, cls:$R3, bdaddr12only:$BD4),
4659            mnemonic#"\t$R1, $BD2, $R3, $BD4", []>;
4660
4661class LoadAndOpRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4662                  RegisterOperand cls, AddressingMode mode = bdaddr20only>
4663  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, mode:$BD2),
4664             mnemonic#"\t$R1, $R3, $BD2",
4665             [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
4666  let mayLoad = 1;
4667  let mayStore = 1;
4668}
4669
4670class CmpSwapRRE<string mnemonic, bits<16> opcode,
4671                 RegisterOperand cls1, RegisterOperand cls2>
4672  : InstRRE<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
4673            mnemonic#"\t$R1, $R2", []> {
4674  let Constraints = "$R1 = $R1src";
4675  let DisableEncoding = "$R1src";
4676  let mayLoad = 1;
4677  let mayStore = 1;
4678}
4679
4680class CmpSwapRS<string mnemonic, bits<8> opcode, SDPatternOperator operator,
4681                RegisterOperand cls, AddressingMode mode = bdaddr12only>
4682  : InstRSa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4683            mnemonic#"\t$R1, $R3, $BD2",
4684            [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4685  let Constraints = "$R1 = $R1src";
4686  let DisableEncoding = "$R1src";
4687  let mayLoad = 1;
4688  let mayStore = 1;
4689}
4690
4691class CmpSwapRSY<string mnemonic, bits<16> opcode, SDPatternOperator operator,
4692                 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4693  : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, mode:$BD2),
4694             mnemonic#"\t$R1, $R3, $BD2",
4695             [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4696  let Constraints = "$R1 = $R1src";
4697  let DisableEncoding = "$R1src";
4698  let mayLoad = 1;
4699  let mayStore = 1;
4700}
4701
4702multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
4703                         SDPatternOperator operator, RegisterOperand cls> {
4704  let DispKey = mnemonic # cls in {
4705    let DispSize = "12" in
4706      def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
4707    let DispSize = "20" in
4708      def Y  : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
4709  }
4710}
4711
4712class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
4713                       RegisterOperand cls2>
4714  : InstRIEf<opcode, (outs cls1:$R1),
4715             (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
4716                  imm32zx6:$I5),
4717             mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
4718  let Constraints = "$R1 = $R1src";
4719  let DisableEncoding = "$R1src";
4720}
4721
4722class PrefetchRXY<string mnemonic, bits<16> opcode, SDPatternOperator operator>
4723  : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
4724             mnemonic#"\t$M1, $XBD2",
4725             [(operator imm32zx4_timm:$M1, bdxaddr20only:$XBD2)]>;
4726
4727class PrefetchRILPC<string mnemonic, bits<12> opcode,
4728                    SDPatternOperator operator>
4729  : InstRILc<opcode, (outs), (ins imm32zx4_timm:$M1, pcrel32:$RI2),
4730             mnemonic#"\t$M1, $RI2",
4731             [(operator imm32zx4_timm:$M1, pcrel32:$RI2)]> {
4732  // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
4733  // However, BDXs have two extra operands and are therefore 6 units more
4734  // complex.
4735  let AddedComplexity = 7;
4736}
4737
4738class BranchPreloadSMI<string mnemonic, bits<8> opcode>
4739  : InstSMI<opcode, (outs),
4740            (ins imm32zx4:$M1, brtarget16bpp:$RI2, bdxaddr12only:$BD3),
4741            mnemonic#"\t$M1, $RI2, $BD3", []>;
4742
4743class BranchPreloadMII<string mnemonic, bits<8> opcode>
4744  : InstMII<opcode, (outs),
4745            (ins imm32zx4:$M1, brtarget12bpp:$RI2, brtarget24bpp:$RI3),
4746            mnemonic#"\t$M1, $RI2, $RI3", []>;
4747
4748// A floating-point load-and test operation.  Create both a normal unary
4749// operation and one that acts as a comparison against zero.
4750// Note that the comparison against zero operation is not available if we
4751// have vector support, since load-and-test instructions will partially
4752// clobber the target (vector) register.
4753multiclass LoadAndTestRRE<string mnemonic, bits<16> opcode,
4754                          RegisterOperand cls> {
4755  def "" : UnaryRRE<mnemonic, opcode, null_frag, cls, cls>;
4756  let isCodeGenOnly = 1, Predicates = [FeatureNoVector] in
4757    def Compare : CompareRRE<mnemonic, opcode, null_frag, cls, cls>;
4758}
4759
4760//===----------------------------------------------------------------------===//
4761// Pseudo instructions
4762//===----------------------------------------------------------------------===//
4763//
4764// Convenience instructions that get lowered to real instructions
4765// by either SystemZTargetLowering::EmitInstrWithCustomInserter()
4766// or SystemZInstrInfo::expandPostRAPseudo().
4767//
4768//===----------------------------------------------------------------------===//
4769
4770class Pseudo<dag outs, dag ins, list<dag> pattern>
4771  : InstSystemZ<0, outs, ins, "", pattern> {
4772  let isPseudo = 1;
4773  let isCodeGenOnly = 1;
4774}
4775
4776// Like UnaryRI, but expanded after RA depending on the choice of register.
4777class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4778                    ImmOpWithPattern imm>
4779  : Pseudo<(outs cls:$R1), (ins imm:$I2),
4780           [(set cls:$R1, (operator imm:$I2))]>;
4781
4782// Like UnaryRXY, but expanded after RA depending on the choice of register.
4783class UnaryRXYPseudo<string key, SDPatternOperator operator,
4784                     RegisterOperand cls, bits<5> bytes,
4785                     AddressingMode mode = bdxaddr20only>
4786  : Pseudo<(outs cls:$R1), (ins mode:$XBD2),
4787           [(set cls:$R1, (operator mode:$XBD2))]> {
4788  let OpKey = key#"r"#cls;
4789  let OpType = "mem";
4790  let mayLoad = 1;
4791  let Has20BitOffset = 1;
4792  let HasIndex = 1;
4793  let AccessBytes = bytes;
4794}
4795
4796// Like UnaryRR, but expanded after RA depending on the choice of registers.
4797class UnaryRRPseudo<string key, SDPatternOperator operator,
4798                    RegisterOperand cls1, RegisterOperand cls2>
4799  : Pseudo<(outs cls1:$R1), (ins cls2:$R2),
4800           [(set cls1:$R1, (operator cls2:$R2))]> {
4801  let OpKey = key#cls1;
4802  let OpType = "reg";
4803}
4804
4805// Like BinaryRI, but expanded after RA depending on the choice of register.
4806class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4807                     ImmOpWithPattern imm>
4808  : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
4809           [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
4810  let Constraints = "$R1 = $R1src";
4811}
4812
4813// Like BinaryRIE, but expanded after RA depending on the choice of register.
4814class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
4815                      ImmOpWithPattern imm>
4816  : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
4817           [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
4818
4819// Like BinaryRIAndK, but expanded after RA depending on the choice of register.
4820multiclass BinaryRIAndKPseudo<string key, SDPatternOperator operator,
4821                              RegisterOperand cls, ImmOpWithPattern imm> {
4822  let NumOpsKey = key in {
4823    let NumOpsValue = "3" in
4824      def K : BinaryRIEPseudo<operator, cls, imm>,
4825              Requires<[FeatureHighWord, FeatureDistinctOps]>;
4826    let NumOpsValue = "2" in
4827      def "" : BinaryRIPseudo<operator, cls, imm>,
4828               Requires<[FeatureHighWord]>;
4829  }
4830}
4831
4832// A pseudo that is used during register allocation when folding a memory
4833// operand. The 3-address register instruction with a spilled source cannot
4834// be converted directly to a target 2-address reg/mem instruction.
4835// Mapping:  <INSN>R  ->  MemFoldPseudo  ->  <INSN>
4836class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes,
4837                    AddressingMode mode>
4838  : Pseudo<(outs cls:$R1), (ins cls:$R2, mode:$XBD2), []> {
4839    let OpKey = !subst("mscrk", "msrkc",
4840                !subst("msgcrk", "msgrkc",
4841                mnemonic#"rk"#cls));
4842    let OpType = "mem";
4843    let MemKey = mnemonic#cls;
4844    let MemType = "pseudo";
4845    let mayLoad = 1;
4846    let AccessBytes = bytes;
4847    let HasIndex = 1;
4848    let hasNoSchedulingInfo = 1;
4849}
4850
4851// Same as MemFoldPseudo but for mapping a W... vector instruction
4852class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes,
4853                    AddressingMode mode>
4854  : MemFoldPseudo<mnemonic, cls, bytes, mode> {
4855    let OpKey = mnemonic#"r"#"MemFold"#cls;
4856}
4857
4858class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes,
4859                           AddressingMode mode>
4860  : Pseudo<(outs cls:$R1), (ins cls:$R2, cls:$R3, mode:$XBD2), []> {
4861    let OpKey = mnemonic#"r"#"MemFold"#cls;
4862    let OpType = "mem";
4863    let MemKey = mnemonic#cls;
4864    let MemType = "pseudo";
4865    let mayLoad = 1;
4866    let AccessBytes = bytes;
4867    let HasIndex = 1;
4868    let hasNoSchedulingInfo = 1;
4869}
4870
4871// Same as MemFoldPseudo but for Load On Condition with CC operands.
4872class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes,
4873                             AddressingMode mode>
4874  : Pseudo<(outs cls:$R1),
4875           (ins cls:$R2, mode:$XBD2, cond4:$valid, cond4:$M3), []> {
4876    let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls;
4877    let OpType = "mem";
4878    let MemKey = mnemonic#cls;
4879    let MemType = "pseudo";
4880    let mayLoad = 1;
4881    let AccessBytes = bytes;
4882    let hasNoSchedulingInfo = 1;
4883}
4884
4885// Like CompareRI, but expanded after RA depending on the choice of register.
4886class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
4887                      ImmOpWithPattern imm>
4888  : Pseudo<(outs), (ins cls:$R1, imm:$I2),
4889           [(set CC, (operator cls:$R1, imm:$I2))]> {
4890  let isCompare = 1;
4891}
4892
4893// Like CompareRXY, but expanded after RA depending on the choice of register.
4894class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
4895                       SDPatternOperator load, bits<5> bytes,
4896                       AddressingMode mode = bdxaddr20only>
4897  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
4898           [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
4899  let mayLoad = 1;
4900  let Has20BitOffset = 1;
4901  let HasIndex = 1;
4902  let AccessBytes = bytes;
4903}
4904
4905// Like TestBinarySIL, but expanded later.
4906class TestBinarySILPseudo<SDPatternOperator operator, ImmOpWithPattern imm>
4907  : Pseudo<(outs), (ins bdaddr12only:$BD1, imm:$I2),
4908           [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
4909
4910// Like CondBinaryRRF, but expanded after RA depending on the choice of
4911// register.
4912class CondBinaryRRFPseudo<string mnemonic, RegisterOperand cls1,
4913                          RegisterOperand cls2>
4914  : Pseudo<(outs cls1:$R1),
4915           (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
4916           [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls1:$R1src,
4917                                            cond4:$valid, cond4:$M3))]> {
4918  let Constraints = "$R1 = $R1src";
4919  let DisableEncoding = "$R1src";
4920  let CCMaskLast = 1;
4921  let NumOpsKey = !subst("loc", "sel", mnemonic);
4922  let NumOpsValue = "2";
4923  let OpKey = mnemonic#cls1;
4924  let OpType = "reg";
4925}
4926
4927// Like CondBinaryRRFa, but expanded after RA depending on the choice of
4928// register.
4929class CondBinaryRRFaPseudo<string mnemonic, RegisterOperand cls1,
4930                           RegisterOperand cls2, RegisterOperand cls3>
4931  : Pseudo<(outs cls1:$R1),
4932           (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
4933           [(set cls1:$R1, (z_select_ccmask cls2:$R2, cls3:$R3,
4934                                            cond4:$valid, cond4:$M4))]> {
4935  let CCMaskLast = 1;
4936  let NumOpsKey = mnemonic;
4937  let NumOpsValue = "3";
4938  let OpKey = mnemonic#cls1;
4939  let OpType = "reg";
4940}
4941
4942// Like CondBinaryRIE, but expanded after RA depending on the choice of
4943// register.
4944class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm>
4945  : Pseudo<(outs cls:$R1),
4946           (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
4947           [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
4948                                           cond4:$valid, cond4:$M3))]> {
4949  let Constraints = "$R1 = $R1src";
4950  let DisableEncoding = "$R1src";
4951  let CCMaskLast = 1;
4952}
4953
4954// Like CondUnaryRSY, but expanded after RA depending on the choice of
4955// register.
4956class CondUnaryRSYPseudo<string mnemonic, SDPatternOperator operator,
4957                         RegisterOperand cls, bits<5> bytes,
4958                         AddressingMode mode = bdaddr20only>
4959  : Pseudo<(outs cls:$R1),
4960           (ins cls:$R1src, mode:$BD2, cond4:$valid, cond4:$R3),
4961           [(set cls:$R1,
4962                 (z_select_ccmask (operator mode:$BD2), cls:$R1src,
4963                                  cond4:$valid, cond4:$R3))]> {
4964  let Constraints = "$R1 = $R1src";
4965  let DisableEncoding = "$R1src";
4966  let mayLoad = 1;
4967  let AccessBytes = bytes;
4968  let CCMaskLast = 1;
4969  let OpKey = mnemonic#"r"#cls;
4970  let OpType = "mem";
4971  let MemKey = mnemonic#cls;
4972  let MemType = "target";
4973}
4974
4975// Like CondStoreRSY, but expanded after RA depending on the choice of
4976// register.
4977class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
4978                         AddressingMode mode = bdaddr20only>
4979  : Pseudo<(outs), (ins cls:$R1, mode:$BD2, cond4:$valid, cond4:$R3), []> {
4980  let mayStore = 1;
4981  let AccessBytes = bytes;
4982  let CCMaskLast = 1;
4983}
4984
4985// Like StoreRXY, but expanded after RA depending on the choice of register.
4986class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
4987                     bits<5> bytes, AddressingMode mode = bdxaddr20only>
4988  : Pseudo<(outs), (ins cls:$R1, mode:$XBD2),
4989           [(operator cls:$R1, mode:$XBD2)]> {
4990  let mayStore = 1;
4991  let Has20BitOffset = 1;
4992  let HasIndex = 1;
4993  let AccessBytes = bytes;
4994}
4995
4996// Like RotateSelectRIEf, but expanded after RA depending on the choice
4997// of registers.
4998class RotateSelectRIEfPseudo<RegisterOperand cls1, RegisterOperand cls2>
4999  : Pseudo<(outs cls1:$R1),
5000           (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
5001                imm32zx6:$I5),
5002           []> {
5003  let Constraints = "$R1 = $R1src";
5004  let DisableEncoding = "$R1src";
5005}
5006
5007// Implements "$dst = $cc & (8 >> CC) ? $src1 : $src2", where CC is
5008// the value of the PSW's 2-bit condition code field.
5009class SelectWrapper<ValueType vt, RegisterOperand cls>
5010  : Pseudo<(outs cls:$dst),
5011           (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
5012           [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2,
5013                                            imm32zx4_timm:$valid, imm32zx4_timm:$cc))]> {
5014  let usesCustomInserter = 1;
5015  let hasNoSchedulingInfo = 1;
5016  let Uses = [CC];
5017}
5018
5019// Stores $new to $addr if $cc is true ("" case) or false (Inv case).
5020multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
5021                      SDPatternOperator load, AddressingMode mode> {
5022  let Uses = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1,
5023      mayLoad = 1, mayStore = 1 in {
5024    def "" : Pseudo<(outs),
5025                    (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
5026                    [(store (z_select_ccmask cls:$new, (load mode:$addr),
5027                                             imm32zx4_timm:$valid, imm32zx4_timm:$cc),
5028                            mode:$addr)]>;
5029    def Inv : Pseudo<(outs),
5030                     (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
5031                     [(store (z_select_ccmask (load mode:$addr), cls:$new,
5032                                              imm32zx4_timm:$valid, imm32zx4_timm:$cc),
5033                              mode:$addr)]>;
5034  }
5035}
5036
5037// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation.  PAT and OPERAND
5038// describe the second (non-memory) operand.
5039class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
5040                       dag pat, DAGOperand operand>
5041  : Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
5042           [(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
5043  let Defs = [CC];
5044  let Has20BitOffset = 1;
5045  let mayLoad = 1;
5046  let mayStore = 1;
5047  let usesCustomInserter = 1;
5048  let hasNoSchedulingInfo = 1;
5049}
5050
5051// Specializations of AtomicLoadWBinary.
5052class AtomicLoadBinaryReg32<SDPatternOperator operator>
5053  : AtomicLoadBinary<operator, GR32, (i32 GR32:$src2), GR32>;
5054class AtomicLoadBinaryImm32<SDPatternOperator operator, ImmOpWithPattern imm>
5055  : AtomicLoadBinary<operator, GR32, (i32 imm:$src2), imm>;
5056class AtomicLoadBinaryReg64<SDPatternOperator operator>
5057  : AtomicLoadBinary<operator, GR64, (i64 GR64:$src2), GR64>;
5058class AtomicLoadBinaryImm64<SDPatternOperator operator, ImmOpWithPattern imm>
5059  : AtomicLoadBinary<operator, GR64, (i64 imm:$src2), imm>;
5060
5061// OPERATOR is ATOMIC_SWAPW or an ATOMIC_LOADW_* operation.  PAT and OPERAND
5062// describe the second (non-memory) operand.
5063class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
5064                        DAGOperand operand>
5065  : Pseudo<(outs GR32:$dst),
5066           (ins bdaddr20only:$ptr, operand:$src2, ADDR32:$bitshift,
5067                ADDR32:$negbitshift, uimm32:$bitsize),
5068           [(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
5069                                      ADDR32:$negbitshift, uimm32:$bitsize))]> {
5070  let Defs = [CC];
5071  let Has20BitOffset = 1;
5072  let mayLoad = 1;
5073  let mayStore = 1;
5074  let usesCustomInserter = 1;
5075  let hasNoSchedulingInfo = 1;
5076}
5077
5078// Specializations of AtomicLoadWBinary.
5079class AtomicLoadWBinaryReg<SDPatternOperator operator>
5080  : AtomicLoadWBinary<operator, (i32 GR32:$src2), GR32>;
5081class AtomicLoadWBinaryImm<SDPatternOperator operator, ImmOpWithPattern imm>
5082  : AtomicLoadWBinary<operator, (i32 imm:$src2), imm>;
5083
5084// A pseudo instruction that is a direct alias of a real instruction.
5085// These aliases are used in cases where a particular register operand is
5086// fixed or where the same instruction is used with different register sizes.
5087// The size parameter is the size in bytes of the associated real instruction.
5088class Alias<int size, dag outs, dag ins, list<dag> pattern>
5089  : InstSystemZ<size, outs, ins, "", pattern> {
5090  let isPseudo = 1;
5091  let isCodeGenOnly = 1;
5092}
5093
5094class UnaryAliasVRS<RegisterOperand cls1, RegisterOperand cls2>
5095 : Alias<6, (outs cls1:$src1), (ins cls2:$src2), []>;
5096
5097// An alias of a UnaryVRR*, but with different register sizes.
5098class UnaryAliasVRR<SDPatternOperator operator, TypedReg tr1, TypedReg tr2>
5099  : Alias<6, (outs tr1.op:$V1), (ins tr2.op:$V2),
5100          [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V2)))]>;
5101
5102// An alias of a UnaryVRX, but with different register sizes.
5103class UnaryAliasVRX<SDPatternOperator operator, TypedReg tr,
5104                    AddressingMode mode = bdxaddr12only>
5105  : Alias<6, (outs tr.op:$V1), (ins mode:$XBD2),
5106          [(set (tr.vt tr.op:$V1), (operator mode:$XBD2))]>;
5107
5108// An alias of a StoreVRX, but with different register sizes.
5109class StoreAliasVRX<SDPatternOperator operator, TypedReg tr,
5110                    AddressingMode mode = bdxaddr12only>
5111  : Alias<6, (outs), (ins tr.op:$V1, mode:$XBD2),
5112          [(operator (tr.vt tr.op:$V1), mode:$XBD2)]>;
5113
5114// An alias of a BinaryRI, but with different register sizes.
5115class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
5116                    ImmOpWithPattern imm>
5117  : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5118          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5119  let Constraints = "$R1 = $R1src";
5120}
5121
5122// An alias of a BinaryRIL, but with different register sizes.
5123class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
5124                     ImmOpWithPattern imm>
5125  : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5126          [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5127  let Constraints = "$R1 = $R1src";
5128}
5129
5130// An alias of a BinaryVRRf, but with different register sizes.
5131class BinaryAliasVRRf<RegisterOperand cls>
5132  : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
5133
5134// An alias of a CompareRI, but with different register sizes.
5135class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
5136                     ImmOpWithPattern imm>
5137  : Alias<4, (outs), (ins cls:$R1, imm:$I2),
5138          [(set CC, (operator cls:$R1, imm:$I2))]> {
5139  let isCompare = 1;
5140}
5141
5142// An alias of a RotateSelectRIEf, but with different register sizes.
5143class RotateSelectAliasRIEf<RegisterOperand cls1, RegisterOperand cls2>
5144  : Alias<6, (outs cls1:$R1),
5145          (ins cls1:$R1src, cls2:$R2, imm32zx8:$I3, imm32zx8:$I4,
5146               imm32zx6:$I5), []> {
5147  let Constraints = "$R1 = $R1src";
5148}
5149
5150//===----------------------------------------------------------------------===//
5151// Multiclasses that emit both real and pseudo instructions
5152//===----------------------------------------------------------------------===//
5153
5154multiclass BinaryRXYAndPseudo<string mnemonic, bits<16> opcode,
5155                              SDPatternOperator operator, RegisterOperand cls,
5156                              SDPatternOperator load, bits<5> bytes,
5157                              AddressingMode mode = bdxaddr20only> {
5158  def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> {
5159    let MemKey = mnemonic#cls;
5160    let MemType = "target";
5161  }
5162  let Has20BitOffset = 1 in
5163    def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, mode>;
5164}
5165
5166multiclass BinaryRXPairAndPseudo<string mnemonic, bits<8> rxOpcode,
5167                                 bits<16> rxyOpcode, SDPatternOperator operator,
5168                                 RegisterOperand cls,
5169                                 SDPatternOperator load, bits<5> bytes> {
5170  let DispKey = mnemonic # cls in {
5171    def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
5172                      bdxaddr12pair> {
5173      let DispSize = "12";
5174      let MemKey = mnemonic#cls;
5175      let MemType = "target";
5176    }
5177    let DispSize = "20" in
5178      def Y  : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load,
5179                         bytes, bdxaddr20pair>;
5180  }
5181  def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>;
5182}
5183
5184multiclass BinaryRXEAndPseudo<string mnemonic, bits<16> opcode,
5185                              SDPatternOperator operator, RegisterOperand cls,
5186                              SDPatternOperator load, bits<5> bytes> {
5187  def "" : BinaryRXE<mnemonic, opcode, operator, cls, load, bytes> {
5188    let MemKey = mnemonic#cls;
5189    let MemType = "target";
5190  }
5191  def _MemFoldPseudo : MemFoldPseudo_FP<mnemonic, cls, bytes, bdxaddr12pair>;
5192}
5193
5194multiclass TernaryRXFAndPseudo<string mnemonic, bits<16> opcode,
5195                               SDPatternOperator operator, RegisterOperand cls1,
5196                               RegisterOperand cls2, SDPatternOperator load,
5197                               bits<5> bytes> {
5198  def "" : TernaryRXF<mnemonic, opcode, operator, cls1, cls2, load, bytes> {
5199    let MemKey = mnemonic#cls1;
5200    let MemType = "target";
5201  }
5202  def _MemFoldPseudo : MemFoldPseudo_FPTern<mnemonic, cls1, bytes, bdxaddr12pair>;
5203}
5204
5205multiclass CondUnaryRSYPairAndMemFold<string mnemonic, bits<16> opcode,
5206                                      SDPatternOperator operator,
5207                                      RegisterOperand cls, bits<5> bytes,
5208                                      AddressingMode mode = bdaddr20only> {
5209  defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>;
5210  def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;
5211}
5212
5213multiclass CondUnaryRSYPseudoAndMemFold<string mnemonic,
5214                                        SDPatternOperator operator,
5215                                        RegisterOperand cls, bits<5> bytes,
5216                                        AddressingMode mode = bdaddr20only> {
5217  def "" : CondUnaryRSYPseudo<mnemonic, operator, cls, bytes, mode>;
5218  def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;
5219}
5220
5221// Define an instruction that operates on two fixed-length blocks of memory,
5222// and associated pseudo instructions for operating on blocks of any size.
5223// The Sequence form uses a straight-line sequence of instructions and
5224// the Loop form uses a loop of length-256 instructions followed by
5225// another instruction to handle the excess.
5226multiclass MemorySS<string mnemonic, bits<8> opcode,
5227                    SDPatternOperator sequence, SDPatternOperator loop> {
5228  def "" : SideEffectBinarySSa<mnemonic, opcode>;
5229  let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [CC] in {
5230    def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5231                                       imm64:$length),
5232                           [(sequence bdaddr12only:$dest, bdaddr12only:$src,
5233                                      imm64:$length)]>;
5234    def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5235                                   imm64:$length, GR64:$count256),
5236                      [(loop bdaddr12only:$dest, bdaddr12only:$src,
5237                             imm64:$length, GR64:$count256)]>;
5238  }
5239}
5240
5241// The same, but setting a CC result as comparison operator.
5242multiclass CompareMemorySS<string mnemonic, bits<8> opcode,
5243                          SDPatternOperator sequence, SDPatternOperator loop> {
5244  def "" : SideEffectBinarySSa<mnemonic, opcode>;
5245  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in {
5246    def Sequence : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5247                                       imm64:$length),
5248                           [(set CC, (sequence bdaddr12only:$dest, bdaddr12only:$src,
5249                                               imm64:$length))]>;
5250    def Loop : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
5251                                   imm64:$length, GR64:$count256),
5252                      [(set CC, (loop bdaddr12only:$dest, bdaddr12only:$src,
5253                                      imm64:$length, GR64:$count256))]>;
5254  }
5255}
5256
5257// Define an instruction that operates on two strings, both terminated
5258// by the character in R0.  The instruction processes a CPU-determinated
5259// number of bytes at a time and sets CC to 3 if the instruction needs
5260// to be repeated.  Also define a pseudo instruction that represents
5261// the full loop (the main instruction plus the branch on CC==3).
5262multiclass StringRRE<string mnemonic, bits<16> opcode,
5263                     SDPatternOperator operator> {
5264  let Uses = [R0L] in
5265    def "" : SideEffectBinaryMemMemRRE<mnemonic, opcode, GR64, GR64>;
5266  let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
5267    def Loop : Pseudo<(outs GR64:$end),
5268                      (ins GR64:$start1, GR64:$start2, GR32:$char),
5269                      [(set GR64:$end, (operator GR64:$start1, GR64:$start2,
5270                                                 GR32:$char))]>;
5271}
5272