1//==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// TODO: Most floating-point instructions (except for simple moves and the 10// like) can raise exceptions -- should they have hasSideEffects=1 ? 11 12//===----------------------------------------------------------------------===// 13// Select instructions 14//===----------------------------------------------------------------------===// 15 16// C's ?: operator for floating-point operands. 17let Predicates = [FeatureVector] in { 18 def SelectVR32 : SelectWrapper<f32, VR32>; 19 def SelectVR64 : SelectWrapper<f64, VR64>; 20} 21def SelectF32 : SelectWrapper<f32, FP32>; 22def SelectF64 : SelectWrapper<f64, FP64>; 23let Predicates = [FeatureNoVectorEnhancements1] in 24 def SelectF128 : SelectWrapper<f128, FP128>; 25let Predicates = [FeatureVectorEnhancements1] in 26 def SelectVR128 : SelectWrapper<f128, VR128>; 27 28defm CondStoreF32 : CondStores<FP32, simple_store, 29 simple_load, bdxaddr20only>; 30defm CondStoreF64 : CondStores<FP64, simple_store, 31 simple_load, bdxaddr20only>; 32 33//===----------------------------------------------------------------------===// 34// Move instructions 35//===----------------------------------------------------------------------===// 36 37// Load zero. 38let isAsCheapAsAMove = 1, isMoveImm = 1 in { 39 def LZER : InherentRRE<"lzer", 0xB374, FP32, fpimm0>; 40 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, fpimm0>; 41 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, fpimm0>; 42} 43 44// Moves between two floating-point registers. 45def LER : UnaryRR <"ler", 0x38, null_frag, FP32, FP32>; 46def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>; 47def LXR : UnaryRRE<"lxr", 0xB365, null_frag, FP128, FP128>; 48 49// For z13 we prefer LDR over LER to avoid partial register dependencies. 50let isCodeGenOnly = 1 in 51 def LDR32 : UnaryRR<"ldr", 0x28, null_frag, FP32, FP32>; 52 53// Moves between two floating-point registers that also set the condition 54// codes. Note that these instructions will turn SNaNs into QNaNs and should 55// not be used for comparison if the result will be used afterwards. 56let Uses = [FPC], mayRaiseFPException = 1, 57 Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 58 def LTEBR : UnaryRRE<"ltebr", 0xB302, null_frag, FP32, FP32>; 59 def LTDBR : UnaryRRE<"ltdbr", 0xB312, null_frag, FP64, FP64>; 60 def LTXBR : UnaryRRE<"ltxbr", 0xB342, null_frag, FP128, FP128>; 61} 62 63// Use a load-and-test for compare against zero (via a pseudo to simplify 64// instruction selection). 65let Uses = [FPC], mayRaiseFPException = 1, 66 Defs = [CC], usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { 67 def LTEBRCompare_Pseudo : Pseudo<(outs), (ins FP32:$R1), []>; 68 def LTDBRCompare_Pseudo : Pseudo<(outs), (ins FP64:$R1), []>; 69 def LTXBRCompare_Pseudo : Pseudo<(outs), (ins FP128:$R1), []>; 70} 71defm : CompareZeroFP<LTEBRCompare_Pseudo, FP32>; 72defm : CompareZeroFP<LTDBRCompare_Pseudo, FP64>; 73let Predicates = [FeatureNoVectorEnhancements1] in 74 defm : CompareZeroFP<LTXBRCompare_Pseudo, FP128>; 75 76// Moves between 64-bit integer and floating-point registers. 77def LGDR : UnaryRRE<"lgdr", 0xB3CD, bitconvert, GR64, FP64>; 78def LDGR : UnaryRRE<"ldgr", 0xB3C1, bitconvert, FP64, GR64>; 79 80// fcopysign with an FP32 result. 81let isCodeGenOnly = 1 in { 82 def CPSDRss : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP32>; 83 def CPSDRsd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP32, FP32, FP64>; 84} 85 86// The sign of an FP128 is in the high register. 87let Predicates = [FeatureNoVectorEnhancements1] in 88 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))), 89 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 90let Predicates = [FeatureVectorEnhancements1] in 91 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))), 92 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>; 93 94// fcopysign with an FP64 result. 95let isCodeGenOnly = 1 in 96 def CPSDRds : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP32>; 97def CPSDRdd : BinaryRRFb<"cpsdr", 0xB372, fcopysign, FP64, FP64, FP64>; 98 99// The sign of an FP128 is in the high register. 100let Predicates = [FeatureNoVectorEnhancements1] in 101 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))), 102 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 103let Predicates = [FeatureVectorEnhancements1] in 104 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))), 105 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG VR128:$src2, subreg_h64))>; 106 107// fcopysign with an FP128 result. Use "upper" as the high half and leave 108// the low half as-is. 109class CopySign128<RegisterOperand cls, dag upper> 110 : Pat<(fcopysign FP128:$src1, cls:$src2), 111 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>; 112 113let Predicates = [FeatureNoVectorEnhancements1] in { 114 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64), 115 FP32:$src2)>; 116 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 117 FP64:$src2)>; 118 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64), 119 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>; 120} 121 122// The length is given as one less for MVCImm. 123defm LoadStoreF32 : MVCLoadStore<load, f32, MVCImm, 3>; 124defm LoadStoreF64 : MVCLoadStore<load, f64, MVCImm, 7>; 125defm LoadStoreF128 : MVCLoadStore<load, f128, MVCImm, 15>; 126 127//===----------------------------------------------------------------------===// 128// Load instructions 129//===----------------------------------------------------------------------===// 130 131let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 132 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>; 133 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>; 134 135 // For z13 we prefer LDE over LE to avoid partial register dependencies. 136 let isCodeGenOnly = 1 in 137 def LDE32 : UnaryRXE<"lde", 0xED24, null_frag, FP32, 4>; 138 139 // These instructions are split after register allocation, so we don't 140 // want a custom inserter. 141 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 142 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src), 143 [(set FP128:$dst, (load bdxaddr20only128:$src))]>; 144 } 145} 146 147//===----------------------------------------------------------------------===// 148// Store instructions 149//===----------------------------------------------------------------------===// 150 151let SimpleBDXStore = 1, mayStore = 1 in { 152 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>; 153 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>; 154 155 // These instructions are split after register allocation, so we don't 156 // want a custom inserter. 157 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 158 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst), 159 [(store FP128:$src, bdxaddr20only128:$dst)]>; 160 } 161} 162 163//===----------------------------------------------------------------------===// 164// Conversion instructions 165//===----------------------------------------------------------------------===// 166 167// Convert floating-point values to narrower representations, rounding 168// according to the current mode. The destination of LEXBR and LDXBR 169// is a 128-bit value, but only the first register of the pair is used. 170let Uses = [FPC], mayRaiseFPException = 1 in { 171 def LEDBR : UnaryRRE<"ledbr", 0xB344, any_fpround, FP32, FP64>; 172 def LEXBR : UnaryRRE<"lexbr", 0xB346, null_frag, FP128, FP128>; 173 def LDXBR : UnaryRRE<"ldxbr", 0xB345, null_frag, FP128, FP128>; 174 175 def LEDBRA : TernaryRRFe<"ledbra", 0xB344, FP32, FP64>, 176 Requires<[FeatureFPExtension]>; 177 def LEXBRA : TernaryRRFe<"lexbra", 0xB346, FP128, FP128>, 178 Requires<[FeatureFPExtension]>; 179 def LDXBRA : TernaryRRFe<"ldxbra", 0xB345, FP128, FP128>, 180 Requires<[FeatureFPExtension]>; 181} 182 183let Predicates = [FeatureNoVectorEnhancements1] in { 184 def : Pat<(f32 (any_fpround FP128:$src)), 185 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_h32)>; 186 def : Pat<(f64 (any_fpround FP128:$src)), 187 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>; 188} 189 190// Extend register floating-point values to wider representations. 191let Uses = [FPC], mayRaiseFPException = 1 in { 192 def LDEBR : UnaryRRE<"ldebr", 0xB304, any_fpextend, FP64, FP32>; 193 def LXEBR : UnaryRRE<"lxebr", 0xB306, null_frag, FP128, FP32>; 194 def LXDBR : UnaryRRE<"lxdbr", 0xB305, null_frag, FP128, FP64>; 195} 196let Predicates = [FeatureNoVectorEnhancements1] in { 197 def : Pat<(f128 (any_fpextend (f32 FP32:$src))), (LXEBR FP32:$src)>; 198 def : Pat<(f128 (any_fpextend (f64 FP64:$src))), (LXDBR FP64:$src)>; 199} 200 201// Extend memory floating-point values to wider representations. 202let Uses = [FPC], mayRaiseFPException = 1 in { 203 def LDEB : UnaryRXE<"ldeb", 0xED04, any_extloadf32, FP64, 4>; 204 def LXEB : UnaryRXE<"lxeb", 0xED06, null_frag, FP128, 4>; 205 def LXDB : UnaryRXE<"lxdb", 0xED05, null_frag, FP128, 8>; 206} 207let Predicates = [FeatureNoVectorEnhancements1] in { 208 def : Pat<(f128 (any_extloadf32 bdxaddr12only:$src)), 209 (LXEB bdxaddr12only:$src)>; 210 def : Pat<(f128 (any_extloadf64 bdxaddr12only:$src)), 211 (LXDB bdxaddr12only:$src)>; 212} 213 214// Convert a signed integer register value to a floating-point one. 215let Uses = [FPC], mayRaiseFPException = 1 in { 216 def CEFBR : UnaryRRE<"cefbr", 0xB394, any_sint_to_fp, FP32, GR32>; 217 def CDFBR : UnaryRRE<"cdfbr", 0xB395, any_sint_to_fp, FP64, GR32>; 218 def CXFBR : UnaryRRE<"cxfbr", 0xB396, any_sint_to_fp, FP128, GR32>; 219 220 def CEGBR : UnaryRRE<"cegbr", 0xB3A4, any_sint_to_fp, FP32, GR64>; 221 def CDGBR : UnaryRRE<"cdgbr", 0xB3A5, any_sint_to_fp, FP64, GR64>; 222 def CXGBR : UnaryRRE<"cxgbr", 0xB3A6, any_sint_to_fp, FP128, GR64>; 223} 224 225// The FP extension feature provides versions of the above that allow 226// specifying rounding mode and inexact-exception suppression flags. 227let Uses = [FPC], mayRaiseFPException = 1, Predicates = [FeatureFPExtension] in { 228 def CEFBRA : TernaryRRFe<"cefbra", 0xB394, FP32, GR32>; 229 def CDFBRA : TernaryRRFe<"cdfbra", 0xB395, FP64, GR32>; 230 def CXFBRA : TernaryRRFe<"cxfbra", 0xB396, FP128, GR32>; 231 232 def CEGBRA : TernaryRRFe<"cegbra", 0xB3A4, FP32, GR64>; 233 def CDGBRA : TernaryRRFe<"cdgbra", 0xB3A5, FP64, GR64>; 234 def CXGBRA : TernaryRRFe<"cxgbra", 0xB3A6, FP128, GR64>; 235} 236 237// Convert am unsigned integer register value to a floating-point one. 238let Predicates = [FeatureFPExtension] in { 239 let Uses = [FPC], mayRaiseFPException = 1 in { 240 def CELFBR : TernaryRRFe<"celfbr", 0xB390, FP32, GR32>; 241 def CDLFBR : TernaryRRFe<"cdlfbr", 0xB391, FP64, GR32>; 242 def CXLFBR : TernaryRRFe<"cxlfbr", 0xB392, FP128, GR32>; 243 244 def CELGBR : TernaryRRFe<"celgbr", 0xB3A0, FP32, GR64>; 245 def CDLGBR : TernaryRRFe<"cdlgbr", 0xB3A1, FP64, GR64>; 246 def CXLGBR : TernaryRRFe<"cxlgbr", 0xB3A2, FP128, GR64>; 247 } 248 249 def : Pat<(f32 (any_uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>; 250 def : Pat<(f64 (any_uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>; 251 def : Pat<(f128 (any_uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>; 252 253 def : Pat<(f32 (any_uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>; 254 def : Pat<(f64 (any_uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>; 255 def : Pat<(f128 (any_uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>; 256} 257 258// Convert a floating-point register value to a signed integer value, 259// with the second operand (modifier M3) specifying the rounding mode. 260let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 261 def CFEBR : BinaryRRFe<"cfebr", 0xB398, GR32, FP32>; 262 def CFDBR : BinaryRRFe<"cfdbr", 0xB399, GR32, FP64>; 263 def CFXBR : BinaryRRFe<"cfxbr", 0xB39A, GR32, FP128>; 264 265 def CGEBR : BinaryRRFe<"cgebr", 0xB3A8, GR64, FP32>; 266 def CGDBR : BinaryRRFe<"cgdbr", 0xB3A9, GR64, FP64>; 267 def CGXBR : BinaryRRFe<"cgxbr", 0xB3AA, GR64, FP128>; 268} 269 270// fp_to_sint always rounds towards zero, which is modifier value 5. 271def : Pat<(i32 (any_fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>; 272def : Pat<(i32 (any_fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>; 273def : Pat<(i32 (any_fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>; 274 275def : Pat<(i64 (any_fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>; 276def : Pat<(i64 (any_fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>; 277def : Pat<(i64 (any_fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>; 278 279// The FP extension feature provides versions of the above that allow 280// also specifying the inexact-exception suppression flag. 281let Uses = [FPC], mayRaiseFPException = 1, 282 Predicates = [FeatureFPExtension], Defs = [CC] in { 283 def CFEBRA : TernaryRRFe<"cfebra", 0xB398, GR32, FP32>; 284 def CFDBRA : TernaryRRFe<"cfdbra", 0xB399, GR32, FP64>; 285 def CFXBRA : TernaryRRFe<"cfxbra", 0xB39A, GR32, FP128>; 286 287 def CGEBRA : TernaryRRFe<"cgebra", 0xB3A8, GR64, FP32>; 288 def CGDBRA : TernaryRRFe<"cgdbra", 0xB3A9, GR64, FP64>; 289 def CGXBRA : TernaryRRFe<"cgxbra", 0xB3AA, GR64, FP128>; 290} 291 292// Convert a floating-point register value to an unsigned integer value. 293let Predicates = [FeatureFPExtension] in { 294 let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 295 def CLFEBR : TernaryRRFe<"clfebr", 0xB39C, GR32, FP32>; 296 def CLFDBR : TernaryRRFe<"clfdbr", 0xB39D, GR32, FP64>; 297 def CLFXBR : TernaryRRFe<"clfxbr", 0xB39E, GR32, FP128>; 298 299 def CLGEBR : TernaryRRFe<"clgebr", 0xB3AC, GR64, FP32>; 300 def CLGDBR : TernaryRRFe<"clgdbr", 0xB3AD, GR64, FP64>; 301 def CLGXBR : TernaryRRFe<"clgxbr", 0xB3AE, GR64, FP128>; 302 } 303 304 def : Pat<(i32 (any_fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>; 305 def : Pat<(i32 (any_fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>; 306 def : Pat<(i32 (any_fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>; 307 308 def : Pat<(i64 (any_fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>; 309 def : Pat<(i64 (any_fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>; 310 def : Pat<(i64 (any_fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>; 311} 312 313 314//===----------------------------------------------------------------------===// 315// Unary arithmetic 316//===----------------------------------------------------------------------===// 317 318// We prefer generic instructions during isel, because they do not 319// clobber CC and therefore give the scheduler more freedom. In cases 320// the CC is actually useful, the SystemZElimCompare pass will try to 321// convert generic instructions into opcodes that also set CC. Note 322// that lcdf / lpdf / lndf only affect the sign bit, and can therefore 323// be used with fp32 as well. This could be done for fp128, in which 324// case the operands would have to be tied. 325 326// Negation (Load Complement). 327let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 328 def LCEBR : UnaryRRE<"lcebr", 0xB303, null_frag, FP32, FP32>; 329 def LCDBR : UnaryRRE<"lcdbr", 0xB313, null_frag, FP64, FP64>; 330 def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>; 331} 332// Generic form, which does not set CC. 333def LCDFR : UnaryRRE<"lcdfr", 0xB373, fneg, FP64, FP64>; 334let isCodeGenOnly = 1 in 335 def LCDFR_32 : UnaryRRE<"lcdfr", 0xB373, fneg, FP32, FP32>; 336 337// Absolute value (Load Positive). 338let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 339 def LPEBR : UnaryRRE<"lpebr", 0xB300, null_frag, FP32, FP32>; 340 def LPDBR : UnaryRRE<"lpdbr", 0xB310, null_frag, FP64, FP64>; 341 def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>; 342} 343// Generic form, which does not set CC. 344def LPDFR : UnaryRRE<"lpdfr", 0xB370, fabs, FP64, FP64>; 345let isCodeGenOnly = 1 in 346 def LPDFR_32 : UnaryRRE<"lpdfr", 0xB370, fabs, FP32, FP32>; 347 348// Negative absolute value (Load Negative). 349let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 350 def LNEBR : UnaryRRE<"lnebr", 0xB301, null_frag, FP32, FP32>; 351 def LNDBR : UnaryRRE<"lndbr", 0xB311, null_frag, FP64, FP64>; 352 def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>; 353} 354// Generic form, which does not set CC. 355def LNDFR : UnaryRRE<"lndfr", 0xB371, fnabs, FP64, FP64>; 356let isCodeGenOnly = 1 in 357 def LNDFR_32 : UnaryRRE<"lndfr", 0xB371, fnabs, FP32, FP32>; 358 359// Square root. 360let Uses = [FPC], mayRaiseFPException = 1 in { 361 def SQEBR : UnaryRRE<"sqebr", 0xB314, any_fsqrt, FP32, FP32>; 362 def SQDBR : UnaryRRE<"sqdbr", 0xB315, any_fsqrt, FP64, FP64>; 363 def SQXBR : UnaryRRE<"sqxbr", 0xB316, any_fsqrt, FP128, FP128>; 364 365 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<any_fsqrt>, FP32, 4>; 366 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<any_fsqrt>, FP64, 8>; 367} 368 369// Round to an integer, with the second operand (modifier M3) specifying 370// the rounding mode. These forms always check for inexact conditions. 371let Uses = [FPC], mayRaiseFPException = 1 in { 372 def FIEBR : BinaryRRFe<"fiebr", 0xB357, FP32, FP32>; 373 def FIDBR : BinaryRRFe<"fidbr", 0xB35F, FP64, FP64>; 374 def FIXBR : BinaryRRFe<"fixbr", 0xB347, FP128, FP128>; 375} 376 377// frint rounds according to the current mode (modifier 0) and detects 378// inexact conditions. 379def : Pat<(any_frint FP32:$src), (FIEBR 0, FP32:$src)>; 380def : Pat<(any_frint FP64:$src), (FIDBR 0, FP64:$src)>; 381def : Pat<(any_frint FP128:$src), (FIXBR 0, FP128:$src)>; 382 383let Predicates = [FeatureFPExtension] in { 384 // Extended forms of the FIxBR instructions. M4 can be set to 4 385 // to suppress detection of inexact conditions. 386 let Uses = [FPC], mayRaiseFPException = 1 in { 387 def FIEBRA : TernaryRRFe<"fiebra", 0xB357, FP32, FP32>; 388 def FIDBRA : TernaryRRFe<"fidbra", 0xB35F, FP64, FP64>; 389 def FIXBRA : TernaryRRFe<"fixbra", 0xB347, FP128, FP128>; 390 } 391 392 // fnearbyint is like frint but does not detect inexact conditions. 393 def : Pat<(any_fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>; 394 def : Pat<(any_fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>; 395 def : Pat<(any_fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>; 396 397 // floor is no longer allowed to raise an inexact condition, 398 // so restrict it to the cases where the condition can be suppressed. 399 // Mode 7 is round towards -inf. 400 def : Pat<(any_ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>; 401 def : Pat<(any_ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>; 402 def : Pat<(any_ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>; 403 404 // Same idea for ceil, where mode 6 is round towards +inf. 405 def : Pat<(any_fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>; 406 def : Pat<(any_fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>; 407 def : Pat<(any_fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>; 408 409 // Same idea for trunc, where mode 5 is round towards zero. 410 def : Pat<(any_ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>; 411 def : Pat<(any_ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>; 412 def : Pat<(any_ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>; 413 414 // Same idea for round, where mode 1 is round towards nearest with 415 // ties away from zero. 416 def : Pat<(any_fround FP32:$src), (FIEBRA 1, FP32:$src, 4)>; 417 def : Pat<(any_fround FP64:$src), (FIDBRA 1, FP64:$src, 4)>; 418 def : Pat<(any_fround FP128:$src), (FIXBRA 1, FP128:$src, 4)>; 419} 420 421//===----------------------------------------------------------------------===// 422// Binary arithmetic 423//===----------------------------------------------------------------------===// 424 425// Addition. 426let Uses = [FPC], mayRaiseFPException = 1, 427 Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 428 let isCommutable = 1 in { 429 def AEBR : BinaryRRE<"aebr", 0xB30A, any_fadd, FP32, FP32>; 430 def ADBR : BinaryRRE<"adbr", 0xB31A, any_fadd, FP64, FP64>; 431 def AXBR : BinaryRRE<"axbr", 0xB34A, any_fadd, FP128, FP128>; 432 } 433 defm AEB : BinaryRXEAndPseudo<"aeb", 0xED0A, any_fadd, FP32, load, 4>; 434 defm ADB : BinaryRXEAndPseudo<"adb", 0xED1A, any_fadd, FP64, load, 8>; 435} 436 437// Subtraction. 438let Uses = [FPC], mayRaiseFPException = 1, 439 Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in { 440 def SEBR : BinaryRRE<"sebr", 0xB30B, any_fsub, FP32, FP32>; 441 def SDBR : BinaryRRE<"sdbr", 0xB31B, any_fsub, FP64, FP64>; 442 def SXBR : BinaryRRE<"sxbr", 0xB34B, any_fsub, FP128, FP128>; 443 444 defm SEB : BinaryRXEAndPseudo<"seb", 0xED0B, any_fsub, FP32, load, 4>; 445 defm SDB : BinaryRXEAndPseudo<"sdb", 0xED1B, any_fsub, FP64, load, 8>; 446} 447 448// Multiplication. 449let Uses = [FPC], mayRaiseFPException = 1 in { 450 let isCommutable = 1 in { 451 def MEEBR : BinaryRRE<"meebr", 0xB317, any_fmul, FP32, FP32>; 452 def MDBR : BinaryRRE<"mdbr", 0xB31C, any_fmul, FP64, FP64>; 453 def MXBR : BinaryRRE<"mxbr", 0xB34C, any_fmul, FP128, FP128>; 454 } 455 defm MEEB : BinaryRXEAndPseudo<"meeb", 0xED17, any_fmul, FP32, load, 4>; 456 defm MDB : BinaryRXEAndPseudo<"mdb", 0xED1C, any_fmul, FP64, load, 8>; 457} 458 459// f64 multiplication of two FP32 registers. 460let Uses = [FPC], mayRaiseFPException = 1 in 461 def MDEBR : BinaryRRE<"mdebr", 0xB30C, null_frag, FP64, FP32>; 462def : Pat<(any_fmul (f64 (any_fpextend FP32:$src1)), 463 (f64 (any_fpextend FP32:$src2))), 464 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 465 FP32:$src1, subreg_h32), FP32:$src2)>; 466 467// f64 multiplication of an FP32 register and an f32 memory. 468let Uses = [FPC], mayRaiseFPException = 1 in 469 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>; 470def : Pat<(any_fmul (f64 (any_fpextend FP32:$src1)), 471 (f64 (any_extloadf32 bdxaddr12only:$addr))), 472 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32), 473 bdxaddr12only:$addr)>; 474 475// f128 multiplication of two FP64 registers. 476let Uses = [FPC], mayRaiseFPException = 1 in 477 def MXDBR : BinaryRRE<"mxdbr", 0xB307, null_frag, FP128, FP64>; 478let Predicates = [FeatureNoVectorEnhancements1] in 479 def : Pat<(any_fmul (f128 (any_fpextend FP64:$src1)), 480 (f128 (any_fpextend FP64:$src2))), 481 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)), 482 FP64:$src1, subreg_h64), FP64:$src2)>; 483 484// f128 multiplication of an FP64 register and an f64 memory. 485let Uses = [FPC], mayRaiseFPException = 1 in 486 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>; 487let Predicates = [FeatureNoVectorEnhancements1] in 488 def : Pat<(any_fmul (f128 (any_fpextend FP64:$src1)), 489 (f128 (any_extloadf64 bdxaddr12only:$addr))), 490 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64), 491 bdxaddr12only:$addr)>; 492 493// Fused multiply-add. 494let Uses = [FPC], mayRaiseFPException = 1 in { 495 def MAEBR : TernaryRRD<"maebr", 0xB30E, z_any_fma, FP32, FP32>; 496 def MADBR : TernaryRRD<"madbr", 0xB31E, z_any_fma, FP64, FP64>; 497 498 defm MAEB : TernaryRXFAndPseudo<"maeb", 0xED0E, z_any_fma, FP32, FP32, load, 4>; 499 defm MADB : TernaryRXFAndPseudo<"madb", 0xED1E, z_any_fma, FP64, FP64, load, 8>; 500} 501 502// Fused multiply-subtract. 503let Uses = [FPC], mayRaiseFPException = 1 in { 504 def MSEBR : TernaryRRD<"msebr", 0xB30F, z_any_fms, FP32, FP32>; 505 def MSDBR : TernaryRRD<"msdbr", 0xB31F, z_any_fms, FP64, FP64>; 506 507 defm MSEB : TernaryRXFAndPseudo<"mseb", 0xED0F, z_any_fms, FP32, FP32, load, 4>; 508 defm MSDB : TernaryRXFAndPseudo<"msdb", 0xED1F, z_any_fms, FP64, FP64, load, 8>; 509} 510 511// Division. 512let Uses = [FPC], mayRaiseFPException = 1 in { 513 def DEBR : BinaryRRE<"debr", 0xB30D, any_fdiv, FP32, FP32>; 514 def DDBR : BinaryRRE<"ddbr", 0xB31D, any_fdiv, FP64, FP64>; 515 def DXBR : BinaryRRE<"dxbr", 0xB34D, any_fdiv, FP128, FP128>; 516 517 defm DEB : BinaryRXEAndPseudo<"deb", 0xED0D, any_fdiv, FP32, load, 4>; 518 defm DDB : BinaryRXEAndPseudo<"ddb", 0xED1D, any_fdiv, FP64, load, 8>; 519} 520 521// Divide to integer. 522let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC] in { 523 def DIEBR : TernaryRRFb<"diebr", 0xB353, FP32, FP32, FP32>; 524 def DIDBR : TernaryRRFb<"didbr", 0xB35B, FP64, FP64, FP64>; 525} 526 527//===----------------------------------------------------------------------===// 528// Comparisons 529//===----------------------------------------------------------------------===// 530 531let Uses = [FPC], mayRaiseFPException = 1, Defs = [CC], CCValues = 0xF in { 532 def CEBR : CompareRRE<"cebr", 0xB309, z_any_fcmp, FP32, FP32>; 533 def CDBR : CompareRRE<"cdbr", 0xB319, z_any_fcmp, FP64, FP64>; 534 def CXBR : CompareRRE<"cxbr", 0xB349, z_any_fcmp, FP128, FP128>; 535 536 def CEB : CompareRXE<"ceb", 0xED09, z_any_fcmp, FP32, load, 4>; 537 def CDB : CompareRXE<"cdb", 0xED19, z_any_fcmp, FP64, load, 8>; 538 539 def KEBR : CompareRRE<"kebr", 0xB308, z_strict_fcmps, FP32, FP32>; 540 def KDBR : CompareRRE<"kdbr", 0xB318, z_strict_fcmps, FP64, FP64>; 541 def KXBR : CompareRRE<"kxbr", 0xB348, z_strict_fcmps, FP128, FP128>; 542 543 def KEB : CompareRXE<"keb", 0xED08, z_strict_fcmps, FP32, load, 4>; 544 def KDB : CompareRXE<"kdb", 0xED18, z_strict_fcmps, FP64, load, 8>; 545} 546 547// Test Data Class. 548let Defs = [CC], CCValues = 0xC in { 549 def TCEB : TestRXE<"tceb", 0xED10, z_tdc, FP32>; 550 def TCDB : TestRXE<"tcdb", 0xED11, z_tdc, FP64>; 551 def TCXB : TestRXE<"tcxb", 0xED12, z_tdc, FP128>; 552} 553 554//===----------------------------------------------------------------------===// 555// Floating-point control register instructions 556//===----------------------------------------------------------------------===// 557 558let hasSideEffects = 1 in { 559 let mayLoad = 1, mayStore = 1 in { 560 // TODO: EFPC and SFPC do not touch memory at all 561 let Uses = [FPC] in { 562 def EFPC : InherentRRE<"efpc", 0xB38C, GR32, int_s390_efpc>; 563 def STFPC : StoreInherentS<"stfpc", 0xB29C, storei<int_s390_efpc>, 4>; 564 } 565 566 let Defs = [FPC] in { 567 def SFPC : SideEffectUnaryRRE<"sfpc", 0xB384, GR32, int_s390_sfpc>; 568 def LFPC : SideEffectUnaryS<"lfpc", 0xB29D, loadu<int_s390_sfpc>, 4>; 569 } 570 } 571 572 let Defs = [FPC], mayRaiseFPException = 1 in { 573 def SFASR : SideEffectUnaryRRE<"sfasr", 0xB385, GR32, null_frag>; 574 def LFAS : SideEffectUnaryS<"lfas", 0xB2BD, null_frag, 4>; 575 } 576 577 let Uses = [FPC], Defs = [FPC] in { 578 def SRNMB : SideEffectAddressS<"srnmb", 0xB2B8, null_frag, shift12only>, 579 Requires<[FeatureFPExtension]>; 580 def SRNM : SideEffectAddressS<"srnm", 0xB299, null_frag, shift12only>; 581 def SRNMT : SideEffectAddressS<"srnmt", 0xB2B9, null_frag, shift12only>; 582 } 583} 584 585//===----------------------------------------------------------------------===// 586// Peepholes 587//===----------------------------------------------------------------------===// 588 589def : Pat<(f32 fpimmneg0), (LCDFR_32 (LZER))>; 590def : Pat<(f64 fpimmneg0), (LCDFR (LZDR))>; 591def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>; 592