1 //===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Streams SystemZ assembly language and associated data, in the form of 10 // MCInsts and MCExprs respectively. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SystemZAsmPrinter.h" 15 #include "MCTargetDesc/SystemZInstPrinter.h" 16 #include "SystemZConstantPoolValue.h" 17 #include "SystemZMCInstLower.h" 18 #include "TargetInfo/SystemZTargetInfo.h" 19 #include "llvm/BinaryFormat/ELF.h" 20 #include "llvm/CodeGen/MachineModuleInfoImpls.h" 21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 22 #include "llvm/IR/Mangler.h" 23 #include "llvm/MC/MCExpr.h" 24 #include "llvm/MC/MCInstBuilder.h" 25 #include "llvm/MC/MCSectionELF.h" 26 #include "llvm/MC/MCStreamer.h" 27 #include "llvm/Support/TargetRegistry.h" 28 29 using namespace llvm; 30 31 // Return an RI instruction like MI with opcode Opcode, but with the 32 // GR64 register operands turned into GR32s. 33 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) { 34 if (MI->isCompare()) 35 return MCInstBuilder(Opcode) 36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 37 .addImm(MI->getOperand(1).getImm()); 38 else 39 return MCInstBuilder(Opcode) 40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) 42 .addImm(MI->getOperand(2).getImm()); 43 } 44 45 // Return an RI instruction like MI with opcode Opcode, but with the 46 // GR64 register operands turned into GRH32s. 47 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) { 48 if (MI->isCompare()) 49 return MCInstBuilder(Opcode) 50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 51 .addImm(MI->getOperand(1).getImm()); 52 else 53 return MCInstBuilder(Opcode) 54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) 56 .addImm(MI->getOperand(2).getImm()); 57 } 58 59 // Return an RI instruction like MI with opcode Opcode, but with the 60 // R2 register turned into a GR64. 61 static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) { 62 return MCInstBuilder(Opcode) 63 .addReg(MI->getOperand(0).getReg()) 64 .addReg(MI->getOperand(1).getReg()) 65 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) 66 .addImm(MI->getOperand(3).getImm()) 67 .addImm(MI->getOperand(4).getImm()) 68 .addImm(MI->getOperand(5).getImm()); 69 } 70 71 static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) { 72 StringRef Name = "__tls_get_offset"; 73 return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name), 74 MCSymbolRefExpr::VK_PLT, 75 Context); 76 } 77 78 static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) { 79 StringRef Name = "_GLOBAL_OFFSET_TABLE_"; 80 return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name), 81 MCSymbolRefExpr::VK_None, 82 Context); 83 } 84 85 // MI is an instruction that accepts an optional alignment hint, 86 // and which was already lowered to LoweredMI. If the alignment 87 // of the original memory operand is known, update LoweredMI to 88 // an instruction with the corresponding hint set. 89 static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI, 90 unsigned Opcode) { 91 if (!MI->hasOneMemOperand()) 92 return; 93 const MachineMemOperand *MMO = *MI->memoperands_begin(); 94 unsigned AlignmentHint = 0; 95 if (MMO->getAlignment() >= 16) 96 AlignmentHint = 4; 97 else if (MMO->getAlignment() >= 8) 98 AlignmentHint = 3; 99 if (AlignmentHint == 0) 100 return; 101 102 LoweredMI.setOpcode(Opcode); 103 LoweredMI.addOperand(MCOperand::createImm(AlignmentHint)); 104 } 105 106 // MI loads the high part of a vector from memory. Return an instruction 107 // that uses replicating vector load Opcode to do the same thing. 108 static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) { 109 return MCInstBuilder(Opcode) 110 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 111 .addReg(MI->getOperand(1).getReg()) 112 .addImm(MI->getOperand(2).getImm()) 113 .addReg(MI->getOperand(3).getReg()); 114 } 115 116 // MI stores the high part of a vector to memory. Return an instruction 117 // that uses elemental vector store Opcode to do the same thing. 118 static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) { 119 return MCInstBuilder(Opcode) 120 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 121 .addReg(MI->getOperand(1).getReg()) 122 .addImm(MI->getOperand(2).getImm()) 123 .addReg(MI->getOperand(3).getReg()) 124 .addImm(0); 125 } 126 127 void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) { 128 SystemZMCInstLower Lower(MF->getContext(), *this); 129 MCInst LoweredMI; 130 switch (MI->getOpcode()) { 131 case SystemZ::Return: 132 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D); 133 break; 134 135 case SystemZ::CondReturn: 136 LoweredMI = MCInstBuilder(SystemZ::BCR) 137 .addImm(MI->getOperand(0).getImm()) 138 .addImm(MI->getOperand(1).getImm()) 139 .addReg(SystemZ::R14D); 140 break; 141 142 case SystemZ::CRBReturn: 143 LoweredMI = MCInstBuilder(SystemZ::CRB) 144 .addReg(MI->getOperand(0).getReg()) 145 .addReg(MI->getOperand(1).getReg()) 146 .addImm(MI->getOperand(2).getImm()) 147 .addReg(SystemZ::R14D) 148 .addImm(0); 149 break; 150 151 case SystemZ::CGRBReturn: 152 LoweredMI = MCInstBuilder(SystemZ::CGRB) 153 .addReg(MI->getOperand(0).getReg()) 154 .addReg(MI->getOperand(1).getReg()) 155 .addImm(MI->getOperand(2).getImm()) 156 .addReg(SystemZ::R14D) 157 .addImm(0); 158 break; 159 160 case SystemZ::CIBReturn: 161 LoweredMI = MCInstBuilder(SystemZ::CIB) 162 .addReg(MI->getOperand(0).getReg()) 163 .addImm(MI->getOperand(1).getImm()) 164 .addImm(MI->getOperand(2).getImm()) 165 .addReg(SystemZ::R14D) 166 .addImm(0); 167 break; 168 169 case SystemZ::CGIBReturn: 170 LoweredMI = MCInstBuilder(SystemZ::CGIB) 171 .addReg(MI->getOperand(0).getReg()) 172 .addImm(MI->getOperand(1).getImm()) 173 .addImm(MI->getOperand(2).getImm()) 174 .addReg(SystemZ::R14D) 175 .addImm(0); 176 break; 177 178 case SystemZ::CLRBReturn: 179 LoweredMI = MCInstBuilder(SystemZ::CLRB) 180 .addReg(MI->getOperand(0).getReg()) 181 .addReg(MI->getOperand(1).getReg()) 182 .addImm(MI->getOperand(2).getImm()) 183 .addReg(SystemZ::R14D) 184 .addImm(0); 185 break; 186 187 case SystemZ::CLGRBReturn: 188 LoweredMI = MCInstBuilder(SystemZ::CLGRB) 189 .addReg(MI->getOperand(0).getReg()) 190 .addReg(MI->getOperand(1).getReg()) 191 .addImm(MI->getOperand(2).getImm()) 192 .addReg(SystemZ::R14D) 193 .addImm(0); 194 break; 195 196 case SystemZ::CLIBReturn: 197 LoweredMI = MCInstBuilder(SystemZ::CLIB) 198 .addReg(MI->getOperand(0).getReg()) 199 .addImm(MI->getOperand(1).getImm()) 200 .addImm(MI->getOperand(2).getImm()) 201 .addReg(SystemZ::R14D) 202 .addImm(0); 203 break; 204 205 case SystemZ::CLGIBReturn: 206 LoweredMI = MCInstBuilder(SystemZ::CLGIB) 207 .addReg(MI->getOperand(0).getReg()) 208 .addImm(MI->getOperand(1).getImm()) 209 .addImm(MI->getOperand(2).getImm()) 210 .addReg(SystemZ::R14D) 211 .addImm(0); 212 break; 213 214 case SystemZ::CallBRASL: 215 LoweredMI = MCInstBuilder(SystemZ::BRASL) 216 .addReg(SystemZ::R14D) 217 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT)); 218 break; 219 220 case SystemZ::CallBASR: 221 LoweredMI = MCInstBuilder(SystemZ::BASR) 222 .addReg(SystemZ::R14D) 223 .addReg(MI->getOperand(0).getReg()); 224 break; 225 226 case SystemZ::CallJG: 227 LoweredMI = MCInstBuilder(SystemZ::JG) 228 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT)); 229 break; 230 231 case SystemZ::CallBRCL: 232 LoweredMI = MCInstBuilder(SystemZ::BRCL) 233 .addImm(MI->getOperand(0).getImm()) 234 .addImm(MI->getOperand(1).getImm()) 235 .addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT)); 236 break; 237 238 case SystemZ::CallBR: 239 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D); 240 break; 241 242 case SystemZ::CallBCR: 243 LoweredMI = MCInstBuilder(SystemZ::BCR) 244 .addImm(MI->getOperand(0).getImm()) 245 .addImm(MI->getOperand(1).getImm()) 246 .addReg(SystemZ::R1D); 247 break; 248 249 case SystemZ::CRBCall: 250 LoweredMI = MCInstBuilder(SystemZ::CRB) 251 .addReg(MI->getOperand(0).getReg()) 252 .addReg(MI->getOperand(1).getReg()) 253 .addImm(MI->getOperand(2).getImm()) 254 .addReg(SystemZ::R1D) 255 .addImm(0); 256 break; 257 258 case SystemZ::CGRBCall: 259 LoweredMI = MCInstBuilder(SystemZ::CGRB) 260 .addReg(MI->getOperand(0).getReg()) 261 .addReg(MI->getOperand(1).getReg()) 262 .addImm(MI->getOperand(2).getImm()) 263 .addReg(SystemZ::R1D) 264 .addImm(0); 265 break; 266 267 case SystemZ::CIBCall: 268 LoweredMI = MCInstBuilder(SystemZ::CIB) 269 .addReg(MI->getOperand(0).getReg()) 270 .addImm(MI->getOperand(1).getImm()) 271 .addImm(MI->getOperand(2).getImm()) 272 .addReg(SystemZ::R1D) 273 .addImm(0); 274 break; 275 276 case SystemZ::CGIBCall: 277 LoweredMI = MCInstBuilder(SystemZ::CGIB) 278 .addReg(MI->getOperand(0).getReg()) 279 .addImm(MI->getOperand(1).getImm()) 280 .addImm(MI->getOperand(2).getImm()) 281 .addReg(SystemZ::R1D) 282 .addImm(0); 283 break; 284 285 case SystemZ::CLRBCall: 286 LoweredMI = MCInstBuilder(SystemZ::CLRB) 287 .addReg(MI->getOperand(0).getReg()) 288 .addReg(MI->getOperand(1).getReg()) 289 .addImm(MI->getOperand(2).getImm()) 290 .addReg(SystemZ::R1D) 291 .addImm(0); 292 break; 293 294 case SystemZ::CLGRBCall: 295 LoweredMI = MCInstBuilder(SystemZ::CLGRB) 296 .addReg(MI->getOperand(0).getReg()) 297 .addReg(MI->getOperand(1).getReg()) 298 .addImm(MI->getOperand(2).getImm()) 299 .addReg(SystemZ::R1D) 300 .addImm(0); 301 break; 302 303 case SystemZ::CLIBCall: 304 LoweredMI = MCInstBuilder(SystemZ::CLIB) 305 .addReg(MI->getOperand(0).getReg()) 306 .addImm(MI->getOperand(1).getImm()) 307 .addImm(MI->getOperand(2).getImm()) 308 .addReg(SystemZ::R1D) 309 .addImm(0); 310 break; 311 312 case SystemZ::CLGIBCall: 313 LoweredMI = MCInstBuilder(SystemZ::CLGIB) 314 .addReg(MI->getOperand(0).getReg()) 315 .addImm(MI->getOperand(1).getImm()) 316 .addImm(MI->getOperand(2).getImm()) 317 .addReg(SystemZ::R1D) 318 .addImm(0); 319 break; 320 321 case SystemZ::TLS_GDCALL: 322 LoweredMI = MCInstBuilder(SystemZ::BRASL) 323 .addReg(SystemZ::R14D) 324 .addExpr(getTLSGetOffset(MF->getContext())) 325 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSGD)); 326 break; 327 328 case SystemZ::TLS_LDCALL: 329 LoweredMI = MCInstBuilder(SystemZ::BRASL) 330 .addReg(SystemZ::R14D) 331 .addExpr(getTLSGetOffset(MF->getContext())) 332 .addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSLDM)); 333 break; 334 335 case SystemZ::GOT: 336 LoweredMI = MCInstBuilder(SystemZ::LARL) 337 .addReg(MI->getOperand(0).getReg()) 338 .addExpr(getGlobalOffsetTable(MF->getContext())); 339 break; 340 341 case SystemZ::IILF64: 342 LoweredMI = MCInstBuilder(SystemZ::IILF) 343 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 344 .addImm(MI->getOperand(2).getImm()); 345 break; 346 347 case SystemZ::IIHF64: 348 LoweredMI = MCInstBuilder(SystemZ::IIHF) 349 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 350 .addImm(MI->getOperand(2).getImm()); 351 break; 352 353 case SystemZ::RISBHH: 354 case SystemZ::RISBHL: 355 LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG); 356 break; 357 358 case SystemZ::RISBLH: 359 case SystemZ::RISBLL: 360 LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG); 361 break; 362 363 case SystemZ::VLVGP32: 364 LoweredMI = MCInstBuilder(SystemZ::VLVGP) 365 .addReg(MI->getOperand(0).getReg()) 366 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg())) 367 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())); 368 break; 369 370 case SystemZ::VLR32: 371 case SystemZ::VLR64: 372 LoweredMI = MCInstBuilder(SystemZ::VLR) 373 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 374 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())); 375 break; 376 377 case SystemZ::VL: 378 Lower.lower(MI, LoweredMI); 379 lowerAlignmentHint(MI, LoweredMI, SystemZ::VLAlign); 380 break; 381 382 case SystemZ::VST: 383 Lower.lower(MI, LoweredMI); 384 lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTAlign); 385 break; 386 387 case SystemZ::VLM: 388 Lower.lower(MI, LoweredMI); 389 lowerAlignmentHint(MI, LoweredMI, SystemZ::VLMAlign); 390 break; 391 392 case SystemZ::VSTM: 393 Lower.lower(MI, LoweredMI); 394 lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTMAlign); 395 break; 396 397 case SystemZ::VL32: 398 LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF); 399 break; 400 401 case SystemZ::VL64: 402 LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPG); 403 break; 404 405 case SystemZ::VST32: 406 LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEF); 407 break; 408 409 case SystemZ::VST64: 410 LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEG); 411 break; 412 413 case SystemZ::LFER: 414 LoweredMI = MCInstBuilder(SystemZ::VLGVF) 415 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg())) 416 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())) 417 .addReg(0).addImm(0); 418 break; 419 420 case SystemZ::LEFR: 421 LoweredMI = MCInstBuilder(SystemZ::VLVGF) 422 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 423 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 424 .addReg(MI->getOperand(1).getReg()) 425 .addReg(0).addImm(0); 426 break; 427 428 #define LOWER_LOW(NAME) \ 429 case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break 430 431 LOWER_LOW(IILL); 432 LOWER_LOW(IILH); 433 LOWER_LOW(TMLL); 434 LOWER_LOW(TMLH); 435 LOWER_LOW(NILL); 436 LOWER_LOW(NILH); 437 LOWER_LOW(NILF); 438 LOWER_LOW(OILL); 439 LOWER_LOW(OILH); 440 LOWER_LOW(OILF); 441 LOWER_LOW(XILF); 442 443 #undef LOWER_LOW 444 445 #define LOWER_HIGH(NAME) \ 446 case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break 447 448 LOWER_HIGH(IIHL); 449 LOWER_HIGH(IIHH); 450 LOWER_HIGH(TMHL); 451 LOWER_HIGH(TMHH); 452 LOWER_HIGH(NIHL); 453 LOWER_HIGH(NIHH); 454 LOWER_HIGH(NIHF); 455 LOWER_HIGH(OIHL); 456 LOWER_HIGH(OIHH); 457 LOWER_HIGH(OIHF); 458 LOWER_HIGH(XIHF); 459 460 #undef LOWER_HIGH 461 462 case SystemZ::Serialize: 463 if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization()) 464 LoweredMI = MCInstBuilder(SystemZ::BCRAsm) 465 .addImm(14).addReg(SystemZ::R0D); 466 else 467 LoweredMI = MCInstBuilder(SystemZ::BCRAsm) 468 .addImm(15).addReg(SystemZ::R0D); 469 break; 470 471 // Emit nothing here but a comment if we can. 472 case SystemZ::MemBarrier: 473 OutStreamer->emitRawComment("MEMBARRIER"); 474 return; 475 476 // We want to emit "j .+2" for traps, jumping to the relative immediate field 477 // of the jump instruction, which is an illegal instruction. We cannot emit a 478 // "." symbol, so create and emit a temp label before the instruction and use 479 // that instead. 480 case SystemZ::Trap: { 481 MCSymbol *DotSym = OutContext.createTempSymbol(); 482 OutStreamer->EmitLabel(DotSym); 483 484 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext); 485 const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext); 486 LoweredMI = MCInstBuilder(SystemZ::J) 487 .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext)); 488 } 489 break; 490 491 // Conditional traps will create a branch on condition instruction that jumps 492 // to the relative immediate field of the jump instruction. (eg. "jo .+2") 493 case SystemZ::CondTrap: { 494 MCSymbol *DotSym = OutContext.createTempSymbol(); 495 OutStreamer->EmitLabel(DotSym); 496 497 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext); 498 const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext); 499 LoweredMI = MCInstBuilder(SystemZ::BRC) 500 .addImm(MI->getOperand(0).getImm()) 501 .addImm(MI->getOperand(1).getImm()) 502 .addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext)); 503 } 504 break; 505 506 case TargetOpcode::FENTRY_CALL: 507 LowerFENTRY_CALL(*MI, Lower); 508 return; 509 510 case TargetOpcode::STACKMAP: 511 LowerSTACKMAP(*MI); 512 return; 513 514 case TargetOpcode::PATCHPOINT: 515 LowerPATCHPOINT(*MI, Lower); 516 return; 517 518 default: 519 Lower.lower(MI, LoweredMI); 520 break; 521 } 522 EmitToStreamer(*OutStreamer, LoweredMI); 523 } 524 525 526 // Emit the largest nop instruction smaller than or equal to NumBytes 527 // bytes. Return the size of nop emitted. 528 static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer, 529 unsigned NumBytes, const MCSubtargetInfo &STI) { 530 if (NumBytes < 2) { 531 llvm_unreachable("Zero nops?"); 532 return 0; 533 } 534 else if (NumBytes < 4) { 535 OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCRAsm) 536 .addImm(0).addReg(SystemZ::R0D), STI); 537 return 2; 538 } 539 else if (NumBytes < 6) { 540 OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCAsm) 541 .addImm(0).addReg(0).addImm(0).addReg(0), 542 STI); 543 return 4; 544 } 545 else { 546 MCSymbol *DotSym = OutContext.createTempSymbol(); 547 const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext); 548 OutStreamer.EmitLabel(DotSym); 549 OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BRCLAsm) 550 .addImm(0).addExpr(Dot), STI); 551 return 6; 552 } 553 } 554 555 void SystemZAsmPrinter::LowerFENTRY_CALL(const MachineInstr &MI, 556 SystemZMCInstLower &Lower) { 557 MCContext &Ctx = MF->getContext(); 558 if (MF->getFunction().hasFnAttribute("mrecord-mcount")) { 559 MCSymbol *DotSym = OutContext.createTempSymbol(); 560 OutStreamer->PushSection(); 561 OutStreamer->SwitchSection( 562 Ctx.getELFSection("__mcount_loc", ELF::SHT_PROGBITS, ELF::SHF_ALLOC)); 563 OutStreamer->EmitSymbolValue(DotSym, 8); 564 OutStreamer->PopSection(); 565 OutStreamer->EmitLabel(DotSym); 566 } 567 568 if (MF->getFunction().hasFnAttribute("mnop-mcount")) { 569 EmitNop(Ctx, *OutStreamer, 6, getSubtargetInfo()); 570 return; 571 } 572 573 MCSymbol *fentry = Ctx.getOrCreateSymbol("__fentry__"); 574 const MCSymbolRefExpr *Op = 575 MCSymbolRefExpr::create(fentry, MCSymbolRefExpr::VK_PLT, Ctx); 576 OutStreamer->EmitInstruction(MCInstBuilder(SystemZ::BRASL) 577 .addReg(SystemZ::R0D).addExpr(Op), getSubtargetInfo()); 578 } 579 580 void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) { 581 const SystemZInstrInfo *TII = 582 static_cast<const SystemZInstrInfo *>(MF->getSubtarget().getInstrInfo()); 583 584 unsigned NumNOPBytes = MI.getOperand(1).getImm(); 585 586 auto &Ctx = OutStreamer->getContext(); 587 MCSymbol *MILabel = Ctx.createTempSymbol(); 588 OutStreamer->EmitLabel(MILabel); 589 590 SM.recordStackMap(*MILabel, MI); 591 assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!"); 592 593 // Scan ahead to trim the shadow. 594 unsigned ShadowBytes = 0; 595 const MachineBasicBlock &MBB = *MI.getParent(); 596 MachineBasicBlock::const_iterator MII(MI); 597 ++MII; 598 while (ShadowBytes < NumNOPBytes) { 599 if (MII == MBB.end() || 600 MII->getOpcode() == TargetOpcode::PATCHPOINT || 601 MII->getOpcode() == TargetOpcode::STACKMAP) 602 break; 603 ShadowBytes += TII->getInstSizeInBytes(*MII); 604 if (MII->isCall()) 605 break; 606 ++MII; 607 } 608 609 // Emit nops. 610 while (ShadowBytes < NumNOPBytes) 611 ShadowBytes += EmitNop(OutContext, *OutStreamer, NumNOPBytes - ShadowBytes, 612 getSubtargetInfo()); 613 } 614 615 // Lower a patchpoint of the form: 616 // [<def>], <id>, <numBytes>, <target>, <numArgs> 617 void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI, 618 SystemZMCInstLower &Lower) { 619 auto &Ctx = OutStreamer->getContext(); 620 MCSymbol *MILabel = Ctx.createTempSymbol(); 621 OutStreamer->EmitLabel(MILabel); 622 623 SM.recordPatchPoint(*MILabel, MI); 624 PatchPointOpers Opers(&MI); 625 626 unsigned EncodedBytes = 0; 627 const MachineOperand &CalleeMO = Opers.getCallTarget(); 628 629 if (CalleeMO.isImm()) { 630 uint64_t CallTarget = CalleeMO.getImm(); 631 if (CallTarget) { 632 unsigned ScratchIdx = -1; 633 unsigned ScratchReg = 0; 634 do { 635 ScratchIdx = Opers.getNextScratchIdx(ScratchIdx + 1); 636 ScratchReg = MI.getOperand(ScratchIdx).getReg(); 637 } while (ScratchReg == SystemZ::R0D); 638 639 // Materialize the call target address 640 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::LLILF) 641 .addReg(ScratchReg) 642 .addImm(CallTarget & 0xFFFFFFFF)); 643 EncodedBytes += 6; 644 if (CallTarget >> 32) { 645 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::IIHF) 646 .addReg(ScratchReg) 647 .addImm(CallTarget >> 32)); 648 EncodedBytes += 6; 649 } 650 651 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR) 652 .addReg(SystemZ::R14D) 653 .addReg(ScratchReg)); 654 EncodedBytes += 2; 655 } 656 } else if (CalleeMO.isGlobal()) { 657 const MCExpr *Expr = Lower.getExpr(CalleeMO, MCSymbolRefExpr::VK_PLT); 658 EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BRASL) 659 .addReg(SystemZ::R14D) 660 .addExpr(Expr)); 661 EncodedBytes += 6; 662 } 663 664 // Emit padding. 665 unsigned NumBytes = Opers.getNumPatchBytes(); 666 assert(NumBytes >= EncodedBytes && 667 "Patchpoint can't request size less than the length of a call."); 668 assert((NumBytes - EncodedBytes) % 2 == 0 && 669 "Invalid number of NOP bytes requested!"); 670 while (EncodedBytes < NumBytes) 671 EncodedBytes += EmitNop(OutContext, *OutStreamer, NumBytes - EncodedBytes, 672 getSubtargetInfo()); 673 } 674 675 // Convert a SystemZ-specific constant pool modifier into the associated 676 // MCSymbolRefExpr variant kind. 677 static MCSymbolRefExpr::VariantKind 678 getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier) { 679 switch (Modifier) { 680 case SystemZCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD; 681 case SystemZCP::TLSLDM: return MCSymbolRefExpr::VK_TLSLDM; 682 case SystemZCP::DTPOFF: return MCSymbolRefExpr::VK_DTPOFF; 683 case SystemZCP::NTPOFF: return MCSymbolRefExpr::VK_NTPOFF; 684 } 685 llvm_unreachable("Invalid SystemCPModifier!"); 686 } 687 688 void SystemZAsmPrinter:: 689 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) { 690 auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV); 691 692 const MCExpr *Expr = 693 MCSymbolRefExpr::create(getSymbol(ZCPV->getGlobalValue()), 694 getModifierVariantKind(ZCPV->getModifier()), 695 OutContext); 696 uint64_t Size = getDataLayout().getTypeAllocSize(ZCPV->getType()); 697 698 OutStreamer->EmitValue(Expr, Size); 699 } 700 701 bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 702 const char *ExtraCode, 703 raw_ostream &OS) { 704 if (ExtraCode) 705 return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS); 706 SystemZMCInstLower Lower(MF->getContext(), *this); 707 MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo))); 708 SystemZInstPrinter::printOperand(MO, MAI, OS); 709 return false; 710 } 711 712 bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, 713 unsigned OpNo, 714 const char *ExtraCode, 715 raw_ostream &OS) { 716 SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(), 717 MI->getOperand(OpNo + 1).getImm(), 718 MI->getOperand(OpNo + 2).getReg(), OS); 719 return false; 720 } 721 722 void SystemZAsmPrinter::EmitEndOfAsmFile(Module &M) { 723 emitStackMaps(SM); 724 } 725 726 // Force static initialization. 727 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmPrinter() { 728 RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget()); 729 } 730