1*0b57cec5SDimitry Andric//===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 10*0b57cec5SDimitry Andric// Target-independent interfaces which we are implementing 11*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 16*0b57cec5SDimitry Andric// SystemZ subtarget features 17*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andricinclude "SystemZFeatures.td" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 22*0b57cec5SDimitry Andric// SystemZ subtarget scheduling models 23*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andricinclude "SystemZSchedule.td" 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 28*0b57cec5SDimitry Andric// SystemZ supported processors 29*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 30*0b57cec5SDimitry Andric 31*0b57cec5SDimitry Andricinclude "SystemZProcessors.td" 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 34*0b57cec5SDimitry Andric// Register file description 35*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andricinclude "SystemZRegisterInfo.td" 38*0b57cec5SDimitry Andric 39*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 40*0b57cec5SDimitry Andric// Calling convention description 41*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andricinclude "SystemZCallingConv.td" 44*0b57cec5SDimitry Andric 45*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 46*0b57cec5SDimitry Andric// Instruction descriptions 47*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 48*0b57cec5SDimitry Andric 49*0b57cec5SDimitry Andricinclude "SystemZOperators.td" 50*0b57cec5SDimitry Andricinclude "SystemZOperands.td" 51*0b57cec5SDimitry Andricinclude "SystemZPatterns.td" 52*0b57cec5SDimitry Andricinclude "SystemZInstrFormats.td" 53*0b57cec5SDimitry Andricinclude "SystemZInstrInfo.td" 54*0b57cec5SDimitry Andricinclude "SystemZInstrVector.td" 55*0b57cec5SDimitry Andricinclude "SystemZInstrFP.td" 56*0b57cec5SDimitry Andricinclude "SystemZInstrHFP.td" 57*0b57cec5SDimitry Andricinclude "SystemZInstrDFP.td" 58*0b57cec5SDimitry Andricinclude "SystemZInstrSystem.td" 59*0b57cec5SDimitry Andric 60*0b57cec5SDimitry Andricdef SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; } 61*0b57cec5SDimitry Andric 62*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 63*0b57cec5SDimitry Andric// Assembly parser 64*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 65*0b57cec5SDimitry Andric 66*0b57cec5SDimitry Andricdef SystemZAsmParser : AsmParser { 67*0b57cec5SDimitry Andric let ShouldEmitMatchRegisterName = 0; 68*0b57cec5SDimitry Andric} 69*0b57cec5SDimitry Andric 70*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 71*0b57cec5SDimitry Andric// Top-level target declaration 72*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 73*0b57cec5SDimitry Andric 74*0b57cec5SDimitry Andricdef SystemZ : Target { 75*0b57cec5SDimitry Andric let InstructionSet = SystemZInstrInfo; 76*0b57cec5SDimitry Andric let AssemblyParsers = [SystemZAsmParser]; 77*0b57cec5SDimitry Andric let AllowRegisterRenaming = 1; 78*0b57cec5SDimitry Andric} 79