1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "SystemZMCTargetDesc.h" 10 #include "SystemZInstPrinter.h" 11 #include "SystemZMCAsmInfo.h" 12 #include "SystemZTargetStreamer.h" 13 #include "TargetInfo/SystemZTargetInfo.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCDwarf.h" 16 #include "llvm/MC/MCInst.h" 17 #include "llvm/MC/MCInstrInfo.h" 18 #include "llvm/MC/MCRegisterInfo.h" 19 #include "llvm/MC/MCStreamer.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/TargetRegistry.h" 22 23 using namespace llvm; 24 25 #define GET_INSTRINFO_MC_DESC 26 #define ENABLE_INSTR_PREDICATE_VERIFIER 27 #include "SystemZGenInstrInfo.inc" 28 29 #define GET_SUBTARGETINFO_MC_DESC 30 #include "SystemZGenSubtargetInfo.inc" 31 32 #define GET_REGINFO_MC_DESC 33 #include "SystemZGenRegisterInfo.inc" 34 35 const unsigned SystemZMC::GR32Regs[16] = { 36 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, 37 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, 38 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, 39 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L 40 }; 41 42 const unsigned SystemZMC::GRH32Regs[16] = { 43 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, 44 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, 45 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, 46 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H 47 }; 48 49 const unsigned SystemZMC::GR64Regs[16] = { 50 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 51 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, 52 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, 53 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D 54 }; 55 56 const unsigned SystemZMC::GR128Regs[16] = { 57 SystemZ::R0Q, 0, SystemZ::R2Q, 0, 58 SystemZ::R4Q, 0, SystemZ::R6Q, 0, 59 SystemZ::R8Q, 0, SystemZ::R10Q, 0, 60 SystemZ::R12Q, 0, SystemZ::R14Q, 0 61 }; 62 63 const unsigned SystemZMC::FP32Regs[16] = { 64 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 65 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 66 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 67 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S 68 }; 69 70 const unsigned SystemZMC::FP64Regs[16] = { 71 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 72 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 73 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 74 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D 75 }; 76 77 const unsigned SystemZMC::FP128Regs[16] = { 78 SystemZ::F0Q, SystemZ::F1Q, 0, 0, 79 SystemZ::F4Q, SystemZ::F5Q, 0, 0, 80 SystemZ::F8Q, SystemZ::F9Q, 0, 0, 81 SystemZ::F12Q, SystemZ::F13Q, 0, 0 82 }; 83 84 const unsigned SystemZMC::VR32Regs[32] = { 85 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 86 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 87 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 88 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 89 SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, 90 SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, 91 SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, 92 SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S 93 }; 94 95 const unsigned SystemZMC::VR64Regs[32] = { 96 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 97 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 98 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 99 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 100 SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, 101 SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, 102 SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, 103 SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D 104 }; 105 106 const unsigned SystemZMC::VR128Regs[32] = { 107 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, 108 SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, 109 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, 110 SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 111 SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, 112 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, 113 SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, 114 SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31 115 }; 116 117 const unsigned SystemZMC::AR32Regs[16] = { 118 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, 119 SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, 120 SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, 121 SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15 122 }; 123 124 const unsigned SystemZMC::CR64Regs[16] = { 125 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, 126 SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, 127 SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, 128 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15 129 }; 130 131 unsigned SystemZMC::getFirstReg(unsigned Reg) { 132 static unsigned Map[SystemZ::NUM_TARGET_REGS]; 133 static bool Initialized = false; 134 if (!Initialized) { 135 for (unsigned I = 0; I < 16; ++I) { 136 Map[GR32Regs[I]] = I; 137 Map[GRH32Regs[I]] = I; 138 Map[GR64Regs[I]] = I; 139 Map[GR128Regs[I]] = I; 140 Map[FP128Regs[I]] = I; 141 Map[AR32Regs[I]] = I; 142 } 143 for (unsigned I = 0; I < 32; ++I) { 144 Map[VR32Regs[I]] = I; 145 Map[VR64Regs[I]] = I; 146 Map[VR128Regs[I]] = I; 147 } 148 } 149 assert(Reg < SystemZ::NUM_TARGET_REGS); 150 return Map[Reg]; 151 } 152 153 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, 154 const Triple &TT, 155 const MCTargetOptions &Options) { 156 if (TT.isOSzOS()) 157 return new SystemZMCAsmInfoGOFF(TT); 158 159 MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT); 160 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( 161 nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true), 162 SystemZMC::ELFCFAOffsetFromInitialSP); 163 MAI->addInitialFrameState(Inst); 164 return MAI; 165 } 166 167 static MCInstrInfo *createSystemZMCInstrInfo() { 168 MCInstrInfo *X = new MCInstrInfo(); 169 InitSystemZMCInstrInfo(X); 170 return X; 171 } 172 173 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) { 174 MCRegisterInfo *X = new MCRegisterInfo(); 175 InitSystemZMCRegisterInfo(X, SystemZ::R14D); 176 return X; 177 } 178 179 static MCSubtargetInfo * 180 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 181 return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 182 } 183 184 static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, 185 unsigned SyntaxVariant, 186 const MCAsmInfo &MAI, 187 const MCInstrInfo &MII, 188 const MCRegisterInfo &MRI) { 189 return new SystemZInstPrinter(MAI, MII, MRI); 190 } 191 192 void SystemZTargetStreamer::emitConstantPools() { 193 // Emit EXRL target instructions. 194 if (EXRLTargets2Sym.empty()) 195 return; 196 // Switch to the .text section. 197 const MCObjectFileInfo &OFI = *Streamer.getContext().getObjectFileInfo(); 198 Streamer.switchSection(OFI.getTextSection()); 199 for (auto &I : EXRLTargets2Sym) { 200 Streamer.emitLabel(I.second); 201 const MCInstSTIPair &MCI_STI = I.first; 202 Streamer.emitInstruction(MCI_STI.first, *MCI_STI.second); 203 } 204 EXRLTargets2Sym.clear(); 205 } 206 207 namespace { 208 class SystemZTargetAsmStreamer : public SystemZTargetStreamer { 209 formatted_raw_ostream &OS; 210 211 public: 212 SystemZTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) 213 : SystemZTargetStreamer(S), OS(OS) {} 214 void emitMachine(StringRef CPU) override { 215 OS << "\t.machine " << CPU << "\n"; 216 } 217 }; 218 219 class SystemZTargetELFStreamer : public SystemZTargetStreamer { 220 public: 221 SystemZTargetELFStreamer(MCStreamer &S) : SystemZTargetStreamer(S) {} 222 void emitMachine(StringRef CPU) override {} 223 }; 224 } // end namespace 225 226 static MCTargetStreamer * 227 createAsmTargetStreamer(MCStreamer &S, 228 formatted_raw_ostream &OS, 229 MCInstPrinter *InstPrint, 230 bool isVerboseAsm) { 231 return new SystemZTargetAsmStreamer(S, OS); 232 } 233 234 static MCTargetStreamer * 235 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 236 return new SystemZTargetELFStreamer(S); 237 } 238 239 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTargetMC() { 240 // Register the MCAsmInfo. 241 TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(), 242 createSystemZMCAsmInfo); 243 244 // Register the MCCodeEmitter. 245 TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(), 246 createSystemZMCCodeEmitter); 247 248 // Register the MCInstrInfo. 249 TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(), 250 createSystemZMCInstrInfo); 251 252 // Register the MCRegisterInfo. 253 TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(), 254 createSystemZMCRegisterInfo); 255 256 // Register the MCSubtargetInfo. 257 TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(), 258 createSystemZMCSubtargetInfo); 259 260 // Register the MCAsmBackend. 261 TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(), 262 createSystemZMCAsmBackend); 263 264 // Register the MCInstPrinter. 265 TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(), 266 createSystemZMCInstPrinter); 267 268 // Register the asm streamer. 269 TargetRegistry::RegisterAsmTargetStreamer(getTheSystemZTarget(), 270 createAsmTargetStreamer); 271 272 // Register the obj streamer 273 TargetRegistry::RegisterObjectTargetStreamer(getTheSystemZTarget(), 274 createObjectTargetStreamer); 275 } 276