1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "SystemZMCTargetDesc.h" 10 #include "SystemZInstPrinter.h" 11 #include "SystemZMCAsmInfo.h" 12 #include "SystemZTargetStreamer.h" 13 #include "TargetInfo/SystemZTargetInfo.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCDwarf.h" 16 #include "llvm/MC/MCInstrInfo.h" 17 #include "llvm/MC/MCRegisterInfo.h" 18 #include "llvm/MC/MCStreamer.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/MC/TargetRegistry.h" 21 22 using namespace llvm; 23 24 #define GET_INSTRINFO_MC_DESC 25 #include "SystemZGenInstrInfo.inc" 26 27 #define GET_SUBTARGETINFO_MC_DESC 28 #include "SystemZGenSubtargetInfo.inc" 29 30 #define GET_REGINFO_MC_DESC 31 #include "SystemZGenRegisterInfo.inc" 32 33 const unsigned SystemZMC::GR32Regs[16] = { 34 SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L, 35 SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L, 36 SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L, 37 SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L 38 }; 39 40 const unsigned SystemZMC::GRH32Regs[16] = { 41 SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H, 42 SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H, 43 SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H, 44 SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H 45 }; 46 47 const unsigned SystemZMC::GR64Regs[16] = { 48 SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, 49 SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D, 50 SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D, 51 SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D 52 }; 53 54 const unsigned SystemZMC::GR128Regs[16] = { 55 SystemZ::R0Q, 0, SystemZ::R2Q, 0, 56 SystemZ::R4Q, 0, SystemZ::R6Q, 0, 57 SystemZ::R8Q, 0, SystemZ::R10Q, 0, 58 SystemZ::R12Q, 0, SystemZ::R14Q, 0 59 }; 60 61 const unsigned SystemZMC::FP32Regs[16] = { 62 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 63 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 64 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 65 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S 66 }; 67 68 const unsigned SystemZMC::FP64Regs[16] = { 69 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 70 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 71 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 72 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D 73 }; 74 75 const unsigned SystemZMC::FP128Regs[16] = { 76 SystemZ::F0Q, SystemZ::F1Q, 0, 0, 77 SystemZ::F4Q, SystemZ::F5Q, 0, 0, 78 SystemZ::F8Q, SystemZ::F9Q, 0, 0, 79 SystemZ::F12Q, SystemZ::F13Q, 0, 0 80 }; 81 82 const unsigned SystemZMC::VR32Regs[32] = { 83 SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S, 84 SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S, 85 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, 86 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, 87 SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S, 88 SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, 89 SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, 90 SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S 91 }; 92 93 const unsigned SystemZMC::VR64Regs[32] = { 94 SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D, 95 SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D, 96 SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D, 97 SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D, 98 SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D, 99 SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, 100 SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, 101 SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D 102 }; 103 104 const unsigned SystemZMC::VR128Regs[32] = { 105 SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3, 106 SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7, 107 SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11, 108 SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15, 109 SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19, 110 SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, 111 SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27, 112 SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31 113 }; 114 115 const unsigned SystemZMC::AR32Regs[16] = { 116 SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3, 117 SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7, 118 SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11, 119 SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15 120 }; 121 122 const unsigned SystemZMC::CR64Regs[16] = { 123 SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3, 124 SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7, 125 SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11, 126 SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15 127 }; 128 129 unsigned SystemZMC::getFirstReg(unsigned Reg) { 130 static unsigned Map[SystemZ::NUM_TARGET_REGS]; 131 static bool Initialized = false; 132 if (!Initialized) { 133 for (unsigned I = 0; I < 16; ++I) { 134 Map[GR32Regs[I]] = I; 135 Map[GRH32Regs[I]] = I; 136 Map[GR64Regs[I]] = I; 137 Map[GR128Regs[I]] = I; 138 Map[FP128Regs[I]] = I; 139 Map[AR32Regs[I]] = I; 140 } 141 for (unsigned I = 0; I < 32; ++I) { 142 Map[VR32Regs[I]] = I; 143 Map[VR64Regs[I]] = I; 144 Map[VR128Regs[I]] = I; 145 } 146 } 147 assert(Reg < SystemZ::NUM_TARGET_REGS); 148 return Map[Reg]; 149 } 150 151 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, 152 const Triple &TT, 153 const MCTargetOptions &Options) { 154 if (TT.isOSzOS()) 155 return new SystemZMCAsmInfoGOFF(TT); 156 157 MCAsmInfo *MAI = new SystemZMCAsmInfoELF(TT); 158 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( 159 nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true), 160 SystemZMC::ELFCFAOffsetFromInitialSP); 161 MAI->addInitialFrameState(Inst); 162 return MAI; 163 } 164 165 static MCInstrInfo *createSystemZMCInstrInfo() { 166 MCInstrInfo *X = new MCInstrInfo(); 167 InitSystemZMCInstrInfo(X); 168 return X; 169 } 170 171 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) { 172 MCRegisterInfo *X = new MCRegisterInfo(); 173 InitSystemZMCRegisterInfo(X, SystemZ::R14D); 174 return X; 175 } 176 177 static MCSubtargetInfo * 178 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { 179 return createSystemZMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); 180 } 181 182 static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T, 183 unsigned SyntaxVariant, 184 const MCAsmInfo &MAI, 185 const MCInstrInfo &MII, 186 const MCRegisterInfo &MRI) { 187 return new SystemZInstPrinter(MAI, MII, MRI); 188 } 189 190 void SystemZTargetStreamer::emitConstantPools() { 191 // Emit EXRL target instructions. 192 if (EXRLTargets2Sym.empty()) 193 return; 194 // Switch to the .text section. 195 const MCObjectFileInfo &OFI = *Streamer.getContext().getObjectFileInfo(); 196 Streamer.SwitchSection(OFI.getTextSection()); 197 for (auto &I : EXRLTargets2Sym) { 198 Streamer.emitLabel(I.second); 199 const MCInstSTIPair &MCI_STI = I.first; 200 Streamer.emitInstruction(MCI_STI.first, *MCI_STI.second); 201 } 202 EXRLTargets2Sym.clear(); 203 } 204 205 namespace { 206 class SystemZTargetAsmStreamer : public SystemZTargetStreamer { 207 formatted_raw_ostream &OS; 208 209 public: 210 SystemZTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS) 211 : SystemZTargetStreamer(S), OS(OS) {} 212 void emitMachine(StringRef CPU) override { 213 OS << "\t.machine " << CPU << "\n"; 214 } 215 }; 216 217 class SystemZTargetELFStreamer : public SystemZTargetStreamer { 218 public: 219 SystemZTargetELFStreamer(MCStreamer &S) : SystemZTargetStreamer(S) {} 220 void emitMachine(StringRef CPU) override {} 221 }; 222 } // end namespace 223 224 static MCTargetStreamer * 225 createAsmTargetStreamer(MCStreamer &S, 226 formatted_raw_ostream &OS, 227 MCInstPrinter *InstPrint, 228 bool isVerboseAsm) { 229 return new SystemZTargetAsmStreamer(S, OS); 230 } 231 232 static MCTargetStreamer * 233 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { 234 return new SystemZTargetELFStreamer(S); 235 } 236 237 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTargetMC() { 238 // Register the MCAsmInfo. 239 TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(), 240 createSystemZMCAsmInfo); 241 242 // Register the MCCodeEmitter. 243 TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(), 244 createSystemZMCCodeEmitter); 245 246 // Register the MCInstrInfo. 247 TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(), 248 createSystemZMCInstrInfo); 249 250 // Register the MCRegisterInfo. 251 TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(), 252 createSystemZMCRegisterInfo); 253 254 // Register the MCSubtargetInfo. 255 TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(), 256 createSystemZMCSubtargetInfo); 257 258 // Register the MCAsmBackend. 259 TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(), 260 createSystemZMCAsmBackend); 261 262 // Register the MCInstPrinter. 263 TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(), 264 createSystemZMCInstPrinter); 265 266 // Register the asm streamer. 267 TargetRegistry::RegisterAsmTargetStreamer(getTheSystemZTarget(), 268 createAsmTargetStreamer); 269 270 // Register the obj streamer 271 TargetRegistry::RegisterObjectTargetStreamer(getTheSystemZTarget(), 272 createObjectTargetStreamer); 273 } 274