1 //===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the SystemZMCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/SystemZMCFixups.h" 14 #include "MCTargetDesc/SystemZMCTargetDesc.h" 15 #include "SystemZInstrInfo.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/MC/MCCodeEmitter.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCFixup.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrInfo.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Support/ErrorHandling.h" 26 #include "llvm/Support/raw_ostream.h" 27 #include <cassert> 28 #include <cstdint> 29 30 using namespace llvm; 31 32 #define DEBUG_TYPE "mccodeemitter" 33 34 namespace { 35 36 class SystemZMCCodeEmitter : public MCCodeEmitter { 37 const MCInstrInfo &MCII; 38 MCContext &Ctx; 39 40 mutable unsigned MemOpsEmitted; 41 42 public: 43 SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 44 : MCII(mcii), Ctx(ctx) { 45 } 46 47 ~SystemZMCCodeEmitter() override = default; 48 49 // OVerride MCCodeEmitter. 50 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 51 SmallVectorImpl<MCFixup> &Fixups, 52 const MCSubtargetInfo &STI) const override; 53 54 private: 55 // Automatically generated by TableGen. 56 uint64_t getBinaryCodeForInstr(const MCInst &MI, 57 SmallVectorImpl<MCFixup> &Fixups, 58 const MCSubtargetInfo &STI) const; 59 60 // Called by the TableGen code to get the binary encoding of operand 61 // MO in MI. Fixups is the list of fixups against MI. 62 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 63 SmallVectorImpl<MCFixup> &Fixups, 64 const MCSubtargetInfo &STI) const; 65 66 // Return the displacement value for the OpNum operand. If it is a symbol, 67 // add a fixup for it and return 0. 68 uint64_t getDispOpValue(const MCInst &MI, unsigned OpNum, 69 SmallVectorImpl<MCFixup> &Fixups, 70 SystemZ::FixupKind Kind) const; 71 72 // Called by the TableGen code to get the binary encoding of an address. 73 // The index or length, if any, is encoded first, followed by the base, 74 // followed by the displacement. In a 20-bit displacement, 75 // the low 12 bits are encoded before the high 8 bits. 76 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 77 SmallVectorImpl<MCFixup> &Fixups, 78 const MCSubtargetInfo &STI) const; 79 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 80 SmallVectorImpl<MCFixup> &Fixups, 81 const MCSubtargetInfo &STI) const; 82 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 83 SmallVectorImpl<MCFixup> &Fixups, 84 const MCSubtargetInfo &STI) const; 85 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 86 SmallVectorImpl<MCFixup> &Fixups, 87 const MCSubtargetInfo &STI) const; 88 uint64_t getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum, 89 SmallVectorImpl<MCFixup> &Fixups, 90 const MCSubtargetInfo &STI) const; 91 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 92 SmallVectorImpl<MCFixup> &Fixups, 93 const MCSubtargetInfo &STI) const; 94 uint64_t getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum, 95 SmallVectorImpl<MCFixup> &Fixups, 96 const MCSubtargetInfo &STI) const; 97 uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum, 98 SmallVectorImpl<MCFixup> &Fixups, 99 const MCSubtargetInfo &STI) const; 100 101 // Operand OpNum of MI needs a PC-relative fixup of kind Kind at 102 // Offset bytes from the start of MI. Add the fixup to Fixups 103 // and return the in-place addend, which since we're a RELA target 104 // is always 0. If AllowTLS is true and optional operand OpNum + 1 105 // is present, also emit a TLS call fixup for it. 106 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum, 107 SmallVectorImpl<MCFixup> &Fixups, 108 unsigned Kind, int64_t Offset, 109 bool AllowTLS) const; 110 111 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, 112 SmallVectorImpl<MCFixup> &Fixups, 113 const MCSubtargetInfo &STI) const { 114 return getPCRelEncoding(MI, OpNum, Fixups, 115 SystemZ::FK_390_PC16DBL, 2, false); 116 } 117 uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, 118 SmallVectorImpl<MCFixup> &Fixups, 119 const MCSubtargetInfo &STI) const { 120 return getPCRelEncoding(MI, OpNum, Fixups, 121 SystemZ::FK_390_PC32DBL, 2, false); 122 } 123 uint64_t getPC16DBLTLSEncoding(const MCInst &MI, unsigned OpNum, 124 SmallVectorImpl<MCFixup> &Fixups, 125 const MCSubtargetInfo &STI) const { 126 return getPCRelEncoding(MI, OpNum, Fixups, 127 SystemZ::FK_390_PC16DBL, 2, true); 128 } 129 uint64_t getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum, 130 SmallVectorImpl<MCFixup> &Fixups, 131 const MCSubtargetInfo &STI) const { 132 return getPCRelEncoding(MI, OpNum, Fixups, 133 SystemZ::FK_390_PC32DBL, 2, true); 134 } 135 uint64_t getPC12DBLBPPEncoding(const MCInst &MI, unsigned OpNum, 136 SmallVectorImpl<MCFixup> &Fixups, 137 const MCSubtargetInfo &STI) const { 138 return getPCRelEncoding(MI, OpNum, Fixups, 139 SystemZ::FK_390_PC12DBL, 1, false); 140 } 141 uint64_t getPC16DBLBPPEncoding(const MCInst &MI, unsigned OpNum, 142 SmallVectorImpl<MCFixup> &Fixups, 143 const MCSubtargetInfo &STI) const { 144 return getPCRelEncoding(MI, OpNum, Fixups, 145 SystemZ::FK_390_PC16DBL, 4, false); 146 } 147 uint64_t getPC24DBLBPPEncoding(const MCInst &MI, unsigned OpNum, 148 SmallVectorImpl<MCFixup> &Fixups, 149 const MCSubtargetInfo &STI) const { 150 return getPCRelEncoding(MI, OpNum, Fixups, 151 SystemZ::FK_390_PC24DBL, 3, false); 152 } 153 154 private: 155 FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; 156 void 157 verifyInstructionPredicates(const MCInst &MI, 158 const FeatureBitset &AvailableFeatures) const; 159 }; 160 161 } // end anonymous namespace 162 163 void SystemZMCCodeEmitter:: 164 encodeInstruction(const MCInst &MI, raw_ostream &OS, 165 SmallVectorImpl<MCFixup> &Fixups, 166 const MCSubtargetInfo &STI) const { 167 verifyInstructionPredicates(MI, 168 computeAvailableFeatures(STI.getFeatureBits())); 169 170 MemOpsEmitted = 0; 171 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 172 unsigned Size = MCII.get(MI.getOpcode()).getSize(); 173 // Big-endian insertion of Size bytes. 174 unsigned ShiftValue = (Size * 8) - 8; 175 for (unsigned I = 0; I != Size; ++I) { 176 OS << uint8_t(Bits >> ShiftValue); 177 ShiftValue -= 8; 178 } 179 } 180 181 uint64_t SystemZMCCodeEmitter:: 182 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 183 SmallVectorImpl<MCFixup> &Fixups, 184 const MCSubtargetInfo &STI) const { 185 if (MO.isReg()) 186 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 187 if (MO.isImm()) 188 return static_cast<uint64_t>(MO.getImm()); 189 llvm_unreachable("Unexpected operand type!"); 190 } 191 192 uint64_t SystemZMCCodeEmitter:: 193 getDispOpValue(const MCInst &MI, unsigned OpNum, 194 SmallVectorImpl<MCFixup> &Fixups, 195 SystemZ::FixupKind Kind) const { 196 const MCOperand &MO = MI.getOperand(OpNum); 197 if (MO.isImm()) { 198 ++MemOpsEmitted; 199 return static_cast<uint64_t>(MO.getImm()); 200 } 201 if (MO.isExpr()) { 202 // All instructions follow the pattern where the first displacement has a 203 // 2 bytes offset, and the second one 4 bytes. 204 unsigned ByteOffs = MemOpsEmitted++ == 0 ? 2 : 4; 205 Fixups.push_back(MCFixup::create(ByteOffs, MO.getExpr(), (MCFixupKind)Kind, 206 MI.getLoc())); 207 assert(Fixups.size() <= 2 && "More than two memory operands in MI?"); 208 return 0; 209 } 210 llvm_unreachable("Unexpected operand type!"); 211 } 212 213 uint64_t SystemZMCCodeEmitter:: 214 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 215 SmallVectorImpl<MCFixup> &Fixups, 216 const MCSubtargetInfo &STI) const { 217 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 218 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12); 219 assert(isUInt<4>(Base) && isUInt<12>(Disp)); 220 return (Base << 12) | Disp; 221 } 222 223 uint64_t SystemZMCCodeEmitter:: 224 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 225 SmallVectorImpl<MCFixup> &Fixups, 226 const MCSubtargetInfo &STI) const { 227 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 228 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_20); 229 assert(isUInt<4>(Base) && isInt<20>(Disp)); 230 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); 231 } 232 233 uint64_t SystemZMCCodeEmitter:: 234 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 235 SmallVectorImpl<MCFixup> &Fixups, 236 const MCSubtargetInfo &STI) const { 237 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 238 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12); 239 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 240 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); 241 return (Index << 16) | (Base << 12) | Disp; 242 } 243 244 uint64_t SystemZMCCodeEmitter:: 245 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 246 SmallVectorImpl<MCFixup> &Fixups, 247 const MCSubtargetInfo &STI) const { 248 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 249 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_20); 250 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 251 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); 252 return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8) 253 | ((Disp & 0xff000) >> 12); 254 } 255 256 uint64_t SystemZMCCodeEmitter:: 257 getBDLAddr12Len4Encoding(const MCInst &MI, unsigned OpNum, 258 SmallVectorImpl<MCFixup> &Fixups, 259 const MCSubtargetInfo &STI) const { 260 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 261 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12); 262 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1; 263 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len)); 264 return (Len << 16) | (Base << 12) | Disp; 265 } 266 267 uint64_t SystemZMCCodeEmitter:: 268 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 269 SmallVectorImpl<MCFixup> &Fixups, 270 const MCSubtargetInfo &STI) const { 271 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 272 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12); 273 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1; 274 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); 275 return (Len << 16) | (Base << 12) | Disp; 276 } 277 278 uint64_t SystemZMCCodeEmitter:: 279 getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum, 280 SmallVectorImpl<MCFixup> &Fixups, 281 const MCSubtargetInfo &STI) const { 282 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 283 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12); 284 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 285 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len)); 286 return (Len << 16) | (Base << 12) | Disp; 287 } 288 289 uint64_t SystemZMCCodeEmitter:: 290 getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum, 291 SmallVectorImpl<MCFixup> &Fixups, 292 const MCSubtargetInfo &STI) const { 293 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 294 uint64_t Disp = getDispOpValue(MI, OpNum + 1, Fixups, SystemZ::FK_390_12); 295 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 296 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index)); 297 return (Index << 16) | (Base << 12) | Disp; 298 } 299 300 uint64_t 301 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum, 302 SmallVectorImpl<MCFixup> &Fixups, 303 unsigned Kind, int64_t Offset, 304 bool AllowTLS) const { 305 SMLoc Loc = MI.getLoc(); 306 const MCOperand &MO = MI.getOperand(OpNum); 307 const MCExpr *Expr; 308 if (MO.isImm()) 309 Expr = MCConstantExpr::create(MO.getImm() + Offset, Ctx); 310 else { 311 Expr = MO.getExpr(); 312 if (Offset) { 313 // The operand value is relative to the start of MI, but the fixup 314 // is relative to the operand field itself, which is Offset bytes 315 // into MI. Add Offset to the relocation value to cancel out 316 // this difference. 317 const MCExpr *OffsetExpr = MCConstantExpr::create(Offset, Ctx); 318 Expr = MCBinaryExpr::createAdd(Expr, OffsetExpr, Ctx); 319 } 320 } 321 Fixups.push_back(MCFixup::create(Offset, Expr, (MCFixupKind)Kind, Loc)); 322 323 // Output the fixup for the TLS marker if present. 324 if (AllowTLS && OpNum + 1 < MI.getNumOperands()) { 325 const MCOperand &MOTLS = MI.getOperand(OpNum + 1); 326 Fixups.push_back(MCFixup::create( 327 0, MOTLS.getExpr(), (MCFixupKind)SystemZ::FK_390_TLS_CALL, Loc)); 328 } 329 return 0; 330 } 331 332 #define ENABLE_INSTR_PREDICATE_VERIFIER 333 #include "SystemZGenMCCodeEmitter.inc" 334 335 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, 336 const MCRegisterInfo &MRI, 337 MCContext &Ctx) { 338 return new SystemZMCCodeEmitter(MCII, Ctx); 339 } 340