1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "SparcTargetMachine.h" 13 #include "LeonPasses.h" 14 #include "Sparc.h" 15 #include "SparcTargetObjectFile.h" 16 #include "TargetInfo/SparcTargetInfo.h" 17 #include "llvm/CodeGen/Passes.h" 18 #include "llvm/CodeGen/TargetPassConfig.h" 19 #include "llvm/IR/LegacyPassManager.h" 20 #include "llvm/Support/TargetRegistry.h" 21 using namespace llvm; 22 23 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { 24 // Register the target. 25 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget()); 26 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target()); 27 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget()); 28 } 29 30 static std::string computeDataLayout(const Triple &T, bool is64Bit) { 31 // Sparc is typically big endian, but some are little. 32 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E"; 33 Ret += "-m:e"; 34 35 // Some ABIs have 32bit pointers. 36 if (!is64Bit) 37 Ret += "-p:32:32"; 38 39 // Alignments for 64 bit integers. 40 Ret += "-i64:64"; 41 42 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. 43 // On SparcV9 registers can hold 64 or 32 bits, on others only 32. 44 if (is64Bit) 45 Ret += "-n32:64"; 46 else 47 Ret += "-f128:64-n32"; 48 49 if (is64Bit) 50 Ret += "-S128"; 51 else 52 Ret += "-S64"; 53 54 return Ret; 55 } 56 57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 58 if (!RM.hasValue()) 59 return Reloc::Static; 60 return *RM; 61 } 62 63 // Code models. Some only make sense for 64-bit code. 64 // 65 // SunCC Reloc CodeModel Constraints 66 // abs32 Static Small text+data+bss linked below 2^32 bytes 67 // abs44 Static Medium text+data+bss linked below 2^44 bytes 68 // abs64 Static Large text smaller than 2^31 bytes 69 // pic13 PIC_ Small GOT < 2^13 bytes 70 // pic32 PIC_ Medium GOT < 2^32 bytes 71 // 72 // All code models require that the text segment is smaller than 2GB. 73 static CodeModel::Model 74 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM, 75 bool Is64Bit, bool JIT) { 76 if (CM) { 77 if (*CM == CodeModel::Tiny) 78 report_fatal_error("Target does not support the tiny CodeModel", false); 79 if (*CM == CodeModel::Kernel) 80 report_fatal_error("Target does not support the kernel CodeModel", false); 81 return *CM; 82 } 83 if (Is64Bit) { 84 if (JIT) 85 return CodeModel::Large; 86 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 87 } 88 return CodeModel::Small; 89 } 90 91 /// Create an ILP32 architecture model 92 SparcTargetMachine::SparcTargetMachine( 93 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 94 const TargetOptions &Options, Optional<Reloc::Model> RM, 95 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) 96 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, 97 getEffectiveRelocModel(RM), 98 getEffectiveSparcCodeModel( 99 CM, getEffectiveRelocModel(RM), is64bit, JIT), 100 OL), 101 TLOF(std::make_unique<SparcELFTargetObjectFile>()), 102 Subtarget(TT, std::string(CPU), std::string(FS), *this, is64bit), 103 is64Bit(is64bit) { 104 initAsmInfo(); 105 } 106 107 SparcTargetMachine::~SparcTargetMachine() {} 108 109 const SparcSubtarget * 110 SparcTargetMachine::getSubtargetImpl(const Function &F) const { 111 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 112 Attribute FSAttr = F.getFnAttribute("target-features"); 113 114 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 115 ? CPUAttr.getValueAsString().str() 116 : TargetCPU; 117 std::string FS = !FSAttr.hasAttribute(Attribute::None) 118 ? FSAttr.getValueAsString().str() 119 : TargetFS; 120 121 // FIXME: This is related to the code below to reset the target options, 122 // we need to know whether or not the soft float flag is set on the 123 // function, so we can enable it as a subtarget feature. 124 bool softFloat = 125 F.hasFnAttribute("use-soft-float") && 126 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 127 128 if (softFloat) 129 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 130 131 auto &I = SubtargetMap[CPU + FS]; 132 if (!I) { 133 // This needs to be done before we create a new subtarget since any 134 // creation will depend on the TM and the code generation flags on the 135 // function that reside in TargetOptions. 136 resetTargetOptions(F); 137 I = std::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this, 138 this->is64Bit); 139 } 140 return I.get(); 141 } 142 143 namespace { 144 /// Sparc Code Generator Pass Configuration Options. 145 class SparcPassConfig : public TargetPassConfig { 146 public: 147 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM) 148 : TargetPassConfig(TM, PM) {} 149 150 SparcTargetMachine &getSparcTargetMachine() const { 151 return getTM<SparcTargetMachine>(); 152 } 153 154 void addIRPasses() override; 155 bool addInstSelector() override; 156 void addPreEmitPass() override; 157 }; 158 } // namespace 159 160 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 161 return new SparcPassConfig(*this, PM); 162 } 163 164 void SparcPassConfig::addIRPasses() { 165 addPass(createAtomicExpandPass()); 166 167 TargetPassConfig::addIRPasses(); 168 } 169 170 bool SparcPassConfig::addInstSelector() { 171 addPass(createSparcISelDag(getSparcTargetMachine())); 172 return false; 173 } 174 175 void SparcPassConfig::addPreEmitPass(){ 176 addPass(createSparcDelaySlotFillerPass()); 177 178 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad()) 179 { 180 addPass(new InsertNOPLoad()); 181 } 182 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) { 183 addPass(new DetectRoundChange()); 184 } 185 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT()) 186 { 187 addPass(new FixAllFDIVSQRT()); 188 } 189 } 190 191 void SparcV8TargetMachine::anchor() { } 192 193 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, 194 StringRef CPU, StringRef FS, 195 const TargetOptions &Options, 196 Optional<Reloc::Model> RM, 197 Optional<CodeModel::Model> CM, 198 CodeGenOpt::Level OL, bool JIT) 199 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 200 201 void SparcV9TargetMachine::anchor() { } 202 203 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, 204 StringRef CPU, StringRef FS, 205 const TargetOptions &Options, 206 Optional<Reloc::Model> RM, 207 Optional<CodeModel::Model> CM, 208 CodeGenOpt::Level OL, bool JIT) 209 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 210 211 void SparcelTargetMachine::anchor() {} 212 213 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, 214 StringRef CPU, StringRef FS, 215 const TargetOptions &Options, 216 Optional<Reloc::Model> RM, 217 Optional<CodeModel::Model> CM, 218 CodeGenOpt::Level OL, bool JIT) 219 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 220