1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // 10 //===----------------------------------------------------------------------===// 11 12 #include "SparcTargetMachine.h" 13 #include "LeonPasses.h" 14 #include "Sparc.h" 15 #include "SparcTargetObjectFile.h" 16 #include "TargetInfo/SparcTargetInfo.h" 17 #include "llvm/CodeGen/Passes.h" 18 #include "llvm/CodeGen/TargetPassConfig.h" 19 #include "llvm/IR/LegacyPassManager.h" 20 #include "llvm/MC/TargetRegistry.h" 21 using namespace llvm; 22 23 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcTarget() { 24 // Register the target. 25 RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget()); 26 RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target()); 27 RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget()); 28 } 29 30 static std::string computeDataLayout(const Triple &T, bool is64Bit) { 31 // Sparc is typically big endian, but some are little. 32 std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E"; 33 Ret += "-m:e"; 34 35 // Some ABIs have 32bit pointers. 36 if (!is64Bit) 37 Ret += "-p:32:32"; 38 39 // Alignments for 64 bit integers. 40 Ret += "-i64:64"; 41 42 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64. 43 // On SparcV9 registers can hold 64 or 32 bits, on others only 32. 44 if (is64Bit) 45 Ret += "-n32:64"; 46 else 47 Ret += "-f128:64-n32"; 48 49 if (is64Bit) 50 Ret += "-S128"; 51 else 52 Ret += "-S64"; 53 54 return Ret; 55 } 56 57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 58 return RM.value_or(Reloc::Static); 59 } 60 61 // Code models. Some only make sense for 64-bit code. 62 // 63 // SunCC Reloc CodeModel Constraints 64 // abs32 Static Small text+data+bss linked below 2^32 bytes 65 // abs44 Static Medium text+data+bss linked below 2^44 bytes 66 // abs64 Static Large text smaller than 2^31 bytes 67 // pic13 PIC_ Small GOT < 2^13 bytes 68 // pic32 PIC_ Medium GOT < 2^32 bytes 69 // 70 // All code models require that the text segment is smaller than 2GB. 71 static CodeModel::Model 72 getEffectiveSparcCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM, 73 bool Is64Bit, bool JIT) { 74 if (CM) { 75 if (*CM == CodeModel::Tiny) 76 report_fatal_error("Target does not support the tiny CodeModel", false); 77 if (*CM == CodeModel::Kernel) 78 report_fatal_error("Target does not support the kernel CodeModel", false); 79 return *CM; 80 } 81 if (Is64Bit) { 82 if (JIT) 83 return CodeModel::Large; 84 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 85 } 86 return CodeModel::Small; 87 } 88 89 /// Create an ILP32 architecture model 90 SparcTargetMachine::SparcTargetMachine( 91 const Target &T, const Triple &TT, StringRef CPU, StringRef FS, 92 const TargetOptions &Options, Optional<Reloc::Model> RM, 93 Optional<CodeModel::Model> CM, CodeGenOpt::Level OL, bool JIT, bool is64bit) 94 : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, 95 getEffectiveRelocModel(RM), 96 getEffectiveSparcCodeModel( 97 CM, getEffectiveRelocModel(RM), is64bit, JIT), 98 OL), 99 TLOF(std::make_unique<SparcELFTargetObjectFile>()), 100 Subtarget(TT, std::string(CPU), std::string(FS), *this, is64bit), 101 is64Bit(is64bit) { 102 initAsmInfo(); 103 } 104 105 SparcTargetMachine::~SparcTargetMachine() = default; 106 107 const SparcSubtarget * 108 SparcTargetMachine::getSubtargetImpl(const Function &F) const { 109 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 110 Attribute FSAttr = F.getFnAttribute("target-features"); 111 112 std::string CPU = 113 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 114 std::string FS = 115 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 116 117 // FIXME: This is related to the code below to reset the target options, 118 // we need to know whether or not the soft float flag is set on the 119 // function, so we can enable it as a subtarget feature. 120 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 121 122 if (softFloat) 123 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 124 125 auto &I = SubtargetMap[CPU + FS]; 126 if (!I) { 127 // This needs to be done before we create a new subtarget since any 128 // creation will depend on the TM and the code generation flags on the 129 // function that reside in TargetOptions. 130 resetTargetOptions(F); 131 I = std::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this, 132 this->is64Bit); 133 } 134 return I.get(); 135 } 136 137 namespace { 138 /// Sparc Code Generator Pass Configuration Options. 139 class SparcPassConfig : public TargetPassConfig { 140 public: 141 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM) 142 : TargetPassConfig(TM, PM) {} 143 144 SparcTargetMachine &getSparcTargetMachine() const { 145 return getTM<SparcTargetMachine>(); 146 } 147 148 void addIRPasses() override; 149 bool addInstSelector() override; 150 void addPreEmitPass() override; 151 }; 152 } // namespace 153 154 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { 155 return new SparcPassConfig(*this, PM); 156 } 157 158 void SparcPassConfig::addIRPasses() { 159 addPass(createAtomicExpandPass()); 160 161 TargetPassConfig::addIRPasses(); 162 } 163 164 bool SparcPassConfig::addInstSelector() { 165 addPass(createSparcISelDag(getSparcTargetMachine())); 166 return false; 167 } 168 169 void SparcPassConfig::addPreEmitPass(){ 170 addPass(createSparcDelaySlotFillerPass()); 171 172 if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad()) 173 { 174 addPass(new InsertNOPLoad()); 175 } 176 if (this->getSparcTargetMachine().getSubtargetImpl()->detectRoundChange()) { 177 addPass(new DetectRoundChange()); 178 } 179 if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT()) 180 { 181 addPass(new FixAllFDIVSQRT()); 182 } 183 } 184 185 void SparcV8TargetMachine::anchor() { } 186 187 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, 188 StringRef CPU, StringRef FS, 189 const TargetOptions &Options, 190 Optional<Reloc::Model> RM, 191 Optional<CodeModel::Model> CM, 192 CodeGenOpt::Level OL, bool JIT) 193 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 194 195 void SparcV9TargetMachine::anchor() { } 196 197 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, 198 StringRef CPU, StringRef FS, 199 const TargetOptions &Options, 200 Optional<Reloc::Model> RM, 201 Optional<CodeModel::Model> CM, 202 CodeGenOpt::Level OL, bool JIT) 203 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 204 205 void SparcelTargetMachine::anchor() {} 206 207 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, 208 StringRef CPU, StringRef FS, 209 const TargetOptions &Options, 210 Optional<Reloc::Model> RM, 211 Optional<CodeModel::Model> CM, 212 CodeGenOpt::Level OL, bool JIT) 213 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 214