1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Sparc instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Instruction format superclass 15//===----------------------------------------------------------------------===// 16 17include "SparcInstrFormats.td" 18 19//===----------------------------------------------------------------------===// 20// Feature predicates. 21//===----------------------------------------------------------------------===// 22 23// True when generating 32-bit code. 24def Is32Bit : Predicate<"!Subtarget->is64Bit()">; 25 26// True when generating 64-bit code. This also implies HasV9. 27def Is64Bit : Predicate<"Subtarget->is64Bit()">; 28 29def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">, 30 AssemblerPredicate<(all_of FeatureSoftMulDiv)>; 31 32// HasV9 - This predicate is true when the target processor supports V9 33// instructions. Note that the machine may be running in 32-bit mode. 34def HasV9 : Predicate<"Subtarget->isV9()">, 35 AssemblerPredicate<(all_of FeatureV9)>; 36 37// HasNoV9 - This predicate is true when the target doesn't have V9 38// instructions. Use of this is just a hack for the isel not having proper 39// costs for V8 instructions that are more expensive than their V9 ones. 40def HasNoV9 : Predicate<"!Subtarget->isV9()">; 41 42// HasVIS - This is true when the target processor has VIS extensions. 43def HasVIS : Predicate<"Subtarget->isVIS()">, 44 AssemblerPredicate<(all_of FeatureVIS)>; 45def HasVIS2 : Predicate<"Subtarget->isVIS2()">, 46 AssemblerPredicate<(all_of FeatureVIS2)>; 47def HasVIS3 : Predicate<"Subtarget->isVIS3()">, 48 AssemblerPredicate<(all_of FeatureVIS3)>; 49 50// HasHardQuad - This is true when the target processor supports quad floating 51// point instructions. 52def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; 53 54// HasLeonCASA - This is true when the target processor supports the CASA 55// instruction 56def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">; 57 58// HasPWRPSR - This is true when the target processor supports partial 59// writes to the PSR register that only affects the ET field. 60def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">, 61 AssemblerPredicate<(all_of FeaturePWRPSR)>; 62 63// HasUMAC_SMAC - This is true when the target processor supports the 64// UMAC and SMAC instructions 65def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">; 66 67def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">; 68def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">; 69def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">; 70 71// UseDeprecatedInsts - This predicate is true when the target processor is a 72// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 73// to use when appropriate. In either of these cases, the instruction selector 74// will pick deprecated instructions. 75def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">; 76 77//===----------------------------------------------------------------------===// 78// Instruction Pattern Stuff 79//===----------------------------------------------------------------------===// 80 81def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 82 83def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 84 85def LO10 : SDNodeXForm<imm, [{ 86 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N), 87 MVT::i32); 88}]>; 89 90def HI22 : SDNodeXForm<imm, [{ 91 // Transformation function: shift the immediate value down into the low bits. 92 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N), 93 MVT::i32); 94}]>; 95 96// Return the complement of a HI22 immediate value. 97def HI22_not : SDNodeXForm<imm, [{ 98 return CurDAG->getTargetConstant(~(unsigned)N->getZExtValue() >> 10, SDLoc(N), 99 MVT::i32); 100}]>; 101 102def SETHIimm : PatLeaf<(imm), [{ 103 return isShiftedUInt<22, 10>(N->getZExtValue()); 104}], HI22>; 105 106// The N->hasOneUse() prevents the immediate from being instantiated in both 107// normal and complement form. 108def SETHIimm_not : PatLeaf<(i32 imm), [{ 109 return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue()); 110}], HI22_not>; 111 112// Addressing modes. 113def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 114def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 115 116// Constrained operands for the shift operations. 117class ShiftAmtImmAsmOperand<int Bits> : AsmOperandClass { 118 let Name = "ShiftAmtImm" # Bits; 119 let ParserMethod = "parseShiftAmtImm<" # Bits # ">"; 120} 121def shift_imm5 : Operand<i32> { 122 let ParserMatchClass = ShiftAmtImmAsmOperand<5>; 123} 124def shift_imm6 : Operand<i32> { 125 let ParserMatchClass = ShiftAmtImmAsmOperand<6>; 126} 127 128// Address operands 129def SparcMEMrrAsmOperand : AsmOperandClass { 130 let Name = "MEMrr"; 131 let ParserMethod = "parseMEMOperand"; 132} 133 134def SparcMEMriAsmOperand : AsmOperandClass { 135 let Name = "MEMri"; 136 let ParserMethod = "parseMEMOperand"; 137} 138 139def MEMrr : Operand<iPTR> { 140 let PrintMethod = "printMemOperand"; 141 let MIOperandInfo = (ops ptr_rc, ptr_rc); 142 let ParserMatchClass = SparcMEMrrAsmOperand; 143} 144def MEMri : Operand<iPTR> { 145 let PrintMethod = "printMemOperand"; 146 let MIOperandInfo = (ops ptr_rc, i32imm); 147 let ParserMatchClass = SparcMEMriAsmOperand; 148} 149 150def TLSSym : Operand<iPTR>; 151 152def SparcMembarTagAsmOperand : AsmOperandClass { 153 let Name = "MembarTag"; 154 let ParserMethod = "parseMembarTag"; 155} 156 157def MembarTag : Operand<i32> { 158 let PrintMethod = "printMembarTag"; 159 let ParserMatchClass = SparcMembarTagAsmOperand; 160} 161 162// Branch targets have OtherVT type. 163def brtarget : Operand<OtherVT> { 164 let EncoderMethod = "getBranchTargetOpValue"; 165} 166 167def bprtarget : Operand<OtherVT> { 168 let EncoderMethod = "getBranchPredTargetOpValue"; 169} 170 171def bprtarget16 : Operand<OtherVT> { 172 let EncoderMethod = "getBranchOnRegTargetOpValue"; 173} 174 175def SparcCallTargetAsmOperand : AsmOperandClass { 176 let Name = "CallTarget"; 177 let ParserMethod = "parseCallTarget"; 178} 179 180def calltarget : Operand<i32> { 181 let EncoderMethod = "getCallTargetOpValue"; 182 let DecoderMethod = "DecodeCall"; 183 let ParserMatchClass = SparcCallTargetAsmOperand; 184} 185 186def simm13Op : Operand<i32> { 187 let DecoderMethod = "DecodeSIMM13"; 188 let EncoderMethod = "getSImm13OpValue"; 189} 190 191// Operand for printing out a condition code. 192let PrintMethod = "printCCOperand" in 193 def CCOp : Operand<i32>; 194 195def SDTSPcmpicc : 196SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 197def SDTSPcmpfcc : 198SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 199def SDTSPbrcc : 200SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 201def SDTSPselectcc : 202SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 203def SDTSPFTOI : 204SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 205def SDTSPITOF : 206SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 207def SDTSPFTOX : 208SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>; 209def SDTSPXTOF : 210SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>; 211 212def SDTSPtlsadd : 213SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 214def SDTSPtlsld : 215SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 216 217def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 218def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 219def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 220def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 221def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 222 223def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 224def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 225 226def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 227def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 228def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>; 229def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>; 230 231def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 232def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 233def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 234 235// These are target-independent nodes, but have target-specific formats. 236def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 237 SDTCisVT<1, i32> ]>; 238def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 239 SDTCisVT<1, i32> ]>; 240 241def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 242 [SDNPHasChain, SDNPOutGlue]>; 243def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 244 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 245 246def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 247def call : SDNode<"SPISD::CALL", SDT_SPCall, 248 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 249 SDNPVariadic]>; 250 251def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 252def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 253 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 254 255def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 256 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 257 258def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>; 259def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>; 260def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall, 261 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 262 SDNPVariadic]>; 263 264def getPCX : Operand<iPTR> { 265 let PrintMethod = "printGetPCX"; 266} 267 268//===----------------------------------------------------------------------===// 269// SPARC Flag Conditions 270//===----------------------------------------------------------------------===// 271 272// Note that these values must be kept in sync with the CCOp::CondCode enum 273// values. 274class ICC_VAL<int N> : PatLeaf<(i32 N)>; 275def ICC_NE : ICC_VAL< 9>; // Not Equal 276def ICC_E : ICC_VAL< 1>; // Equal 277def ICC_G : ICC_VAL<10>; // Greater 278def ICC_LE : ICC_VAL< 2>; // Less or Equal 279def ICC_GE : ICC_VAL<11>; // Greater or Equal 280def ICC_L : ICC_VAL< 3>; // Less 281def ICC_GU : ICC_VAL<12>; // Greater Unsigned 282def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 283def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 284def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 285def ICC_POS : ICC_VAL<14>; // Positive 286def ICC_NEG : ICC_VAL< 6>; // Negative 287def ICC_VC : ICC_VAL<15>; // Overflow Clear 288def ICC_VS : ICC_VAL< 7>; // Overflow Set 289 290class FCC_VAL<int N> : PatLeaf<(i32 N)>; 291def FCC_U : FCC_VAL<23>; // Unordered 292def FCC_G : FCC_VAL<22>; // Greater 293def FCC_UG : FCC_VAL<21>; // Unordered or Greater 294def FCC_L : FCC_VAL<20>; // Less 295def FCC_UL : FCC_VAL<19>; // Unordered or Less 296def FCC_LG : FCC_VAL<18>; // Less or Greater 297def FCC_NE : FCC_VAL<17>; // Not Equal 298def FCC_E : FCC_VAL<25>; // Equal 299def FCC_UE : FCC_VAL<26>; // Unordered or Equal 300def FCC_GE : FCC_VAL<27>; // Greater or Equal 301def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal 302def FCC_LE : FCC_VAL<29>; // Less or Equal 303def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal 304def FCC_O : FCC_VAL<31>; // Ordered 305 306class CPCC_VAL<int N> : PatLeaf<(i32 N)>; 307def CPCC_3 : CPCC_VAL<39>; // 3 308def CPCC_2 : CPCC_VAL<38>; // 2 309def CPCC_23 : CPCC_VAL<37>; // 2 or 3 310def CPCC_1 : CPCC_VAL<36>; // 1 311def CPCC_13 : CPCC_VAL<35>; // 1 or 3 312def CPCC_12 : CPCC_VAL<34>; // 1 or 2 313def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3 314def CPCC_0 : CPCC_VAL<41>; // 0 315def CPCC_03 : CPCC_VAL<42>; // 0 or 3 316def CPCC_02 : CPCC_VAL<43>; // 0 or 2 317def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3 318def CPCC_01 : CPCC_VAL<45>; // 0 or 1 319def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3 320def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2 321 322//===----------------------------------------------------------------------===// 323// Instruction Class Templates 324//===----------------------------------------------------------------------===// 325 326/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 327multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode, 328 RegisterClass RC, ValueType Ty, Operand immOp, 329 InstrItinClass itin = IIC_iu_instr> { 330 def rr : F3_1<2, Op3Val, 331 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 332 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 333 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))], 334 itin>; 335 def ri : F3_2<2, Op3Val, 336 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 337 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 338 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))], 339 itin>; 340} 341 342/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 343/// pattern. 344multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> { 345 def rr : F3_1<2, Op3Val, 346 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 347 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], 348 itin>; 349 def ri : F3_2<2, Op3Val, 350 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 351 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], 352 itin>; 353} 354 355// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 356multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 357 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> { 358 def rr : F3_1<3, Op3Val, 359 (outs RC:$dst), (ins MEMrr:$addr), 360 !strconcat(OpcStr, " [$addr], $dst"), 361 [(set Ty:$dst, (OpNode ADDRrr:$addr))], 362 itin>; 363 def ri : F3_2<3, Op3Val, 364 (outs RC:$dst), (ins MEMri:$addr), 365 !strconcat(OpcStr, " [$addr], $dst"), 366 [(set Ty:$dst, (OpNode ADDRri:$addr))], 367 itin>; 368} 369 370// TODO: Instructions of the LoadASI class are currently asm only; hooking up 371// CodeGen's address spaces to use these is a future task. 372class LoadASI<string OpcStr, bits<6> Op3Val, RegisterClass RC> : 373 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), 374 !strconcat(OpcStr, "a [$addr] $asi, $dst"), 375 []>; 376 377// LoadA multiclass - As above, but also define alternate address space variant 378multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val, 379 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, 380 InstrItinClass itin = NoItinerary> : 381 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> { 382 def Arr : LoadASI<OpcStr, LoadAOp3Val, RC>; 383} 384 385// The LDSTUB instruction is supported for asm only. 386// It is unlikely that general-purpose code could make use of it. 387// CAS is preferred for sparc v9. 388def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr), 389 "ldstub [$addr], $dst", []>; 390def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr), 391 "ldstub [$addr], $dst", []>; 392def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst), 393 (ins MEMrr:$addr, i8imm:$asi), 394 "ldstuba [$addr] $asi, $dst", []>; 395 396// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 397multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 398 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> { 399 def rr : F3_1<3, Op3Val, 400 (outs), (ins MEMrr:$addr, RC:$rd), 401 !strconcat(OpcStr, " $rd, [$addr]"), 402 [(OpNode Ty:$rd, ADDRrr:$addr)], 403 itin>; 404 def ri : F3_2<3, Op3Val, 405 (outs), (ins MEMri:$addr, RC:$rd), 406 !strconcat(OpcStr, " $rd, [$addr]"), 407 [(OpNode Ty:$rd, ADDRri:$addr)], 408 itin>; 409} 410 411// TODO: Instructions of the StoreASI class are currently asm only; hooking up 412// CodeGen's address spaces to use these is a future task. 413class StoreASI<string OpcStr, bits<6> Op3Val, RegisterClass RC, 414 InstrItinClass itin = IIC_st> : 415 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), 416 !strconcat(OpcStr, "a $rd, [$addr] $asi"), 417 [], 418 itin>; 419 420multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val, 421 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> : 422 Store<OpcStr, Op3Val, OpNode, RC, Ty> { 423 def Arr : StoreASI<OpcStr, StoreAOp3Val, RC>; 424} 425 426//===----------------------------------------------------------------------===// 427// Instructions 428//===----------------------------------------------------------------------===// 429 430// Pseudo instructions. 431class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 432 : InstSP<outs, ins, asmstr, pattern> { 433 let isCodeGenOnly = 1; 434 let isPseudo = 1; 435} 436 437// GETPCX for PIC 438let Defs = [O7] in { 439 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 440} 441 442let Defs = [O6], Uses = [O6] in { 443def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 444 "!ADJCALLSTACKDOWN $amt1, $amt2", 445 [(callseq_start timm:$amt1, timm:$amt2)]>; 446def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 447 "!ADJCALLSTACKUP $amt1", 448 [(callseq_end timm:$amt1, timm:$amt2)]>; 449} 450 451let hasSideEffects = 1, mayStore = 1 in { 452 let rd = 0, rs1 = 0, rs2 = 0 in 453 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 454 "flushw", 455 [(flushw)]>, Requires<[HasV9]>; 456 let rd = 8, rs1 = 0, simm13 = 3 in 457 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 458 "ta 3", 459 [(flushw)]>; 460} 461 462// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 463// instruction selection into a branch sequence. This has to handle all 464// permutations of selection between i32/f32/f64 on ICC and FCC. 465// Expanded after instruction selection. 466let Uses = [ICC], usesCustomInserter = 1 in { 467 def SELECT_CC_Int_ICC 468 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 469 "; SELECT_CC_Int_ICC PSEUDO!", 470 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 471 def SELECT_CC_FP_ICC 472 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 473 "; SELECT_CC_FP_ICC PSEUDO!", 474 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 475 476 def SELECT_CC_DFP_ICC 477 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 478 "; SELECT_CC_DFP_ICC PSEUDO!", 479 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 480 481 def SELECT_CC_QFP_ICC 482 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 483 "; SELECT_CC_QFP_ICC PSEUDO!", 484 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>; 485} 486 487let usesCustomInserter = 1, Uses = [FCC0] in { 488 489 def SELECT_CC_Int_FCC 490 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 491 "; SELECT_CC_Int_FCC PSEUDO!", 492 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 493 494 def SELECT_CC_FP_FCC 495 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 496 "; SELECT_CC_FP_FCC PSEUDO!", 497 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 498 def SELECT_CC_DFP_FCC 499 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 500 "; SELECT_CC_DFP_FCC PSEUDO!", 501 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 502 def SELECT_CC_QFP_FCC 503 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 504 "; SELECT_CC_QFP_FCC PSEUDO!", 505 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 506} 507 508// Section B.1 - Load Integer Instructions, p. 90 509let DecoderMethod = "DecodeLoadInt" in { 510 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>; 511 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>; 512 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>; 513 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>; 514 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>; 515} 516 517let DecoderMethod = "DecodeLoadIntPair" in 518 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>; 519 520// Section B.2 - Load Floating-point Instructions, p. 92 521let DecoderMethod = "DecodeLoadFP" in { 522 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>; 523 def LDFArr : LoadASI<"ld", 0b110000, FPRegs>, 524 Requires<[HasV9]>; 525} 526let DecoderMethod = "DecodeLoadDFP" in { 527 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>; 528 def LDDFArr : LoadASI<"ldd", 0b110011, DFPRegs>, 529 Requires<[HasV9]>; 530} 531let DecoderMethod = "DecodeLoadQFP" in 532 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>, 533 Requires<[HasV9, HasHardQuad]>; 534 535let DecoderMethod = "DecodeLoadCP" in 536 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>; 537let DecoderMethod = "DecodeLoadCPPair" in 538 defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>; 539 540let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in { 541 let rd = 0 in { 542 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr), 543 "ld [$addr], %csr", []>; 544 def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr), 545 "ld [$addr], %csr", []>; 546 } 547} 548 549let DecoderMethod = "DecodeLoadFP" in 550 let Defs = [FSR] in { 551 let rd = 0 in { 552 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), 553 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; 554 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), 555 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; 556 } 557 let rd = 1 in { 558 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), 559 "ldx [$addr], %fsr", []>, Requires<[HasV9]>; 560 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), 561 "ldx [$addr], %fsr", []>, Requires<[HasV9]>; 562 } 563 } 564 565// Section B.4 - Store Integer Instructions, p. 95 566let DecoderMethod = "DecodeStoreInt" in { 567 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>; 568 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>; 569 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>; 570} 571 572let DecoderMethod = "DecodeStoreIntPair" in 573 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>; 574 575// Section B.5 - Store Floating-point Instructions, p. 97 576let DecoderMethod = "DecodeStoreFP" in { 577 defm STF : Store<"st", 0b100100, store, FPRegs, f32>; 578 def STFArr : StoreASI<"st", 0b110100, FPRegs>, 579 Requires<[HasV9]>; 580} 581let DecoderMethod = "DecodeStoreDFP" in { 582 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>; 583 def STDFArr : StoreASI<"std", 0b110111, DFPRegs>, 584 Requires<[HasV9]>; 585} 586let DecoderMethod = "DecodeStoreQFP" in 587 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>, 588 Requires<[HasV9, HasHardQuad]>; 589 590let DecoderMethod = "DecodeStoreCP" in 591 defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; 592 593let DecoderMethod = "DecodeStoreCPPair" in 594 defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>; 595 596let DecoderMethod = "DecodeStoreCP", rd = 0 in { 597 let Defs = [CPSR] in { 598 def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins), 599 "st %csr, [$addr]", [], IIC_st>; 600 def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins), 601 "st %csr, [$addr]", [], IIC_st>; 602 } 603 let Defs = [CPQ] in { 604 def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins), 605 "std %cq, [$addr]", [], IIC_std>; 606 def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins), 607 "std %cq, [$addr]", [], IIC_std>; 608 } 609} 610 611let DecoderMethod = "DecodeStoreFP" in { 612 let rd = 0 in { 613 let Defs = [FSR] in { 614 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), 615 "st %fsr, [$addr]", [], IIC_st>; 616 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), 617 "st %fsr, [$addr]", [], IIC_st>; 618 } 619 let Defs = [FQ] in { 620 def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins), 621 "std %fq, [$addr]", [], IIC_std>; 622 def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins), 623 "std %fq, [$addr]", [], IIC_std>; 624 } 625 } 626 let rd = 1, Defs = [FSR] in { 627 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), 628 "stx %fsr, [$addr]", []>, Requires<[HasV9]>; 629 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), 630 "stx %fsr, [$addr]", []>, Requires<[HasV9]>; 631 } 632} 633 634// Section B.8 - SWAP Register with Memory Instruction 635// (Atomic swap) 636let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in { 637 def SWAPrr : F3_1<3, 0b001111, 638 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val), 639 "swap [$addr], $dst", 640 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>; 641 def SWAPri : F3_2<3, 0b001111, 642 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val), 643 "swap [$addr], $dst", 644 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>; 645 def SWAPArr : F3_1_asi<3, 0b011111, 646 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val), 647 "swapa [$addr] $asi, $dst", 648 [/*FIXME: pattern?*/]>; 649} 650 651 652// Section B.9 - SETHI Instruction, p. 104 653def SETHIi: F2_1<0b100, 654 (outs IntRegs:$rd), (ins i32imm:$imm22), 655 "sethi $imm22, $rd", 656 [(set i32:$rd, SETHIimm:$imm22)], 657 IIC_iu_instr>; 658 659// Section B.10 - NOP Instruction, p. 105 660// (It's a special case of SETHI) 661let rd = 0, imm22 = 0 in 662 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 663 664// Section B.11 - Logical Instructions, p. 106 665defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>; 666 667def ANDNrr : F3_1<2, 0b000101, 668 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 669 "andn $rs1, $rs2, $rd", 670 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>; 671def ANDNri : F3_2<2, 0b000101, 672 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 673 "andn $rs1, $simm13, $rd", []>; 674 675defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>; 676 677def ORNrr : F3_1<2, 0b000110, 678 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 679 "orn $rs1, $rs2, $rd", 680 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>; 681def ORNri : F3_2<2, 0b000110, 682 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 683 "orn $rs1, $simm13, $rd", []>; 684defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>; 685 686def XNORrr : F3_1<2, 0b000111, 687 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 688 "xnor $rs1, $rs2, $rd", 689 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>; 690def XNORri : F3_2<2, 0b000111, 691 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 692 "xnor $rs1, $simm13, $rd", []>; 693 694def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2), 695 (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>; 696 697def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2), 698 (ORNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>; 699 700let Defs = [ICC] in { 701 defm ANDCC : F3_12np<"andcc", 0b010001>; 702 defm ANDNCC : F3_12np<"andncc", 0b010101>; 703 defm ORCC : F3_12np<"orcc", 0b010010>; 704 defm ORNCC : F3_12np<"orncc", 0b010110>; 705 defm XORCC : F3_12np<"xorcc", 0b010011>; 706 defm XNORCC : F3_12np<"xnorcc", 0b010111>; 707} 708 709// Section B.12 - Shift Instructions, p. 107 710defm SLL : F3_S<"sll", 0b100101, 0, shl, i32, shift_imm5, IntRegs>; 711defm SRL : F3_S<"srl", 0b100110, 0, srl, i32, shift_imm5, IntRegs>; 712defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>; 713 714// Section B.13 - Add Instructions, p. 108 715defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>; 716 717// "LEA" forms of add (patterns to make tblgen happy) 718let Predicates = [Is32Bit], isCodeGenOnly = 1 in 719 def LEA_ADDri : F3_2<2, 0b000000, 720 (outs IntRegs:$dst), (ins MEMri:$addr), 721 "add ${addr:arith}, $dst", 722 [(set iPTR:$dst, ADDRri:$addr)]>; 723 724let Defs = [ICC] in 725 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>; 726 727let Uses = [ICC] in 728 defm ADDC : F3_12np<"addx", 0b001000>; 729 730let Uses = [ICC], Defs = [ICC] in 731 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>; 732 733// Section B.15 - Subtract Instructions, p. 110 734defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>; 735let Uses = [ICC], Defs = [ICC] in 736 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>; 737 738let Defs = [ICC] in 739 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>; 740 741let Uses = [ICC] in 742 defm SUBC : F3_12np <"subx", 0b001100>; 743 744// cmp (from Section A.3) is a specialized alias for subcc 745let Defs = [ICC], rd = 0 in { 746 def CMPrr : F3_1<2, 0b010100, 747 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 748 "cmp $rs1, $rs2", 749 [(SPcmpicc i32:$rs1, i32:$rs2)]>; 750 def CMPri : F3_2<2, 0b010100, 751 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 752 "cmp $rs1, $simm13", 753 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>; 754} 755 756// Section B.18 - Multiply Instructions, p. 113 757let Defs = [Y] in { 758 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>; 759 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>; 760} 761 762let Defs = [Y, ICC] in { 763 defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>; 764 defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>; 765} 766 767let Defs = [Y, ICC], Uses = [Y, ICC] in { 768 defm MULSCC : F3_12np<"mulscc", 0b100100>; 769} 770 771// Section B.19 - Divide Instructions, p. 115 772let Uses = [Y], Defs = [Y] in { 773 defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>; 774 defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>; 775} 776 777let Uses = [Y], Defs = [Y, ICC] in { 778 defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>; 779 defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>; 780} 781 782// Section B.20 - SAVE and RESTORE, p. 117 783defm SAVE : F3_12np<"save" , 0b111100>; 784defm RESTORE : F3_12np<"restore", 0b111101>; 785 786// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 787 788// unconditional branch class. 789class BranchAlways<dag ins, string asmstr, list<dag> pattern> 790 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> { 791 let isBranch = 1; 792 let isTerminator = 1; 793 let hasDelaySlot = 1; 794 let isBarrier = 1; 795} 796 797let cond = 8 in 798 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>; 799 800 801let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 802 803// conditional branch class: 804class BranchSP<dag ins, string asmstr, list<dag> pattern> 805 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>; 806 807// conditional branch with annul class: 808class BranchSPA<dag ins, string asmstr, list<dag> pattern> 809 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>; 810 811// Conditional branch class on %icc|%xcc with predication: 812multiclass IPredBranch<string regstr, list<dag> CCPattern> { 813 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), 814 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")), 815 CCPattern, 816 IIC_iu_instr>; 817 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), 818 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")), 819 [], 820 IIC_iu_instr>; 821 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), 822 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")), 823 [], 824 IIC_iu_instr>; 825 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), 826 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")), 827 [], 828 IIC_iu_instr>; 829} 830 831} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 832 833 834// Indirect branch instructions. 835let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1, 836 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in { 837 def BINDrr : F3_1<2, 0b111000, 838 (outs), (ins MEMrr:$ptr), 839 "jmp $ptr", 840 [(brind ADDRrr:$ptr)]>; 841 def BINDri : F3_2<2, 0b111000, 842 (outs), (ins MEMri:$ptr), 843 "jmp $ptr", 844 [(brind ADDRri:$ptr)]>; 845} 846 847let Uses = [ICC] in { 848 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond), 849 "b$cond $imm22", 850 [(SPbricc bb:$imm22, imm:$cond)]>; 851 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond), 852 "b$cond,a $imm22", []>; 853 854 let Predicates = [HasV9], cc = 0b00 in 855 defm BPI : IPredBranch<"%icc", []>; 856} 857 858// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 859 860let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 861 862// floating-point conditional branch class: 863class FPBranchSP<dag ins, string asmstr, list<dag> pattern> 864 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; 865 866// floating-point conditional branch with annul class: 867class FPBranchSPA<dag ins, string asmstr, list<dag> pattern> 868 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; 869 870// Conditional branch class on %fcc0-%fcc3 with predication: 871multiclass FPredBranch { 872 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, 873 FCCRegs:$cc), 874 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>; 875 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, 876 FCCRegs:$cc), 877 "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>; 878 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, 879 FCCRegs:$cc), 880 "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>; 881 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, 882 FCCRegs:$cc), 883 "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>; 884} 885} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 886 887let Uses = [FCC0] in { 888 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 889 "fb$cond $imm22", 890 [(SPbrfcc bb:$imm22, imm:$cond)]>; 891 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), 892 "fb$cond,a $imm22", []>; 893} 894 895let Predicates = [HasV9] in 896 defm BPF : FPredBranch; 897 898// Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123 899let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 900 901// co-processor conditional branch class: 902class CPBranchSP<dag ins, string asmstr, list<dag> pattern> 903 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>; 904 905// co-processor conditional branch with annul class: 906class CPBranchSPA<dag ins, string asmstr, list<dag> pattern> 907 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>; 908 909} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 910 911def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 912 "cb$cond $imm22", 913 [(SPbrfcc bb:$imm22, imm:$cond)]>; 914def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), 915 "cb$cond,a $imm22", []>; 916 917// Section B.24 - Call and Link Instruction, p. 125 918// This is the only Format 1 instruction 919let Uses = [O6], 920 hasDelaySlot = 1, isCall = 1 in { 921 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops), 922 "call $disp", 923 [], 924 IIC_jmp_or_call> { 925 bits<30> disp; 926 let op = 1; 927 let Inst{29-0} = disp; 928 } 929 930 // indirect calls: special cases of JMPL. 931 let isCodeGenOnly = 1, rd = 15 in { 932 def CALLrr : F3_1<2, 0b111000, 933 (outs), (ins MEMrr:$ptr, variable_ops), 934 "call $ptr", 935 [(call ADDRrr:$ptr)], 936 IIC_jmp_or_call>; 937 def CALLri : F3_2<2, 0b111000, 938 (outs), (ins MEMri:$ptr, variable_ops), 939 "call $ptr", 940 [(call ADDRri:$ptr)], 941 IIC_jmp_or_call>; 942 } 943} 944 945// Section B.25 - Jump and Link Instruction 946 947// JMPL Instruction. 948let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 949 DecoderMethod = "DecodeJMPL" in { 950 def JMPLrr: F3_1<2, 0b111000, 951 (outs IntRegs:$dst), (ins MEMrr:$addr), 952 "jmpl $addr, $dst", 953 [], 954 IIC_jmp_or_call>; 955 def JMPLri: F3_2<2, 0b111000, 956 (outs IntRegs:$dst), (ins MEMri:$addr), 957 "jmpl $addr, $dst", 958 [], 959 IIC_jmp_or_call>; 960} 961 962// Section A.3 - Synthetic Instructions, p. 85 963// special cases of JMPL: 964let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 965 isCodeGenOnly = 1 in { 966 let rd = 0, rs1 = 15 in 967 def RETL: F3_2<2, 0b111000, 968 (outs), (ins i32imm:$val), 969 "jmp %o7+$val", 970 [(retflag simm13:$val)], 971 IIC_jmp_or_call>; 972 973 let rd = 0, rs1 = 31 in 974 def RET: F3_2<2, 0b111000, 975 (outs), (ins i32imm:$val), 976 "jmp %i7+$val", 977 [], 978 IIC_jmp_or_call>; 979} 980 981// Section B.26 - Return from Trap Instruction 982let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, 983 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in { 984 def RETTrr : F3_1<2, 0b111001, 985 (outs), (ins MEMrr:$addr), 986 "rett $addr", 987 [], 988 IIC_jmp_or_call>; 989 def RETTri : F3_2<2, 0b111001, 990 (outs), (ins MEMri:$addr), 991 "rett $addr", 992 [], 993 IIC_jmp_or_call>; 994} 995 996 997// Section B.27 - Trap on Integer Condition Codes Instruction 998// conditional branch class: 999let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in 1000{ 1001 def TRAPrr : TRAPSPrr<0b111010, 1002 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), 1003 "t$cond $rs1 + $rs2", 1004 []>; 1005 def TRAPri : TRAPSPri<0b111010, 1006 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), 1007 "t$cond $rs1 + $imm", 1008 []>; 1009} 1010 1011multiclass TRAP<string regStr> { 1012 def rr : TRAPSPrr<0b111010, 1013 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), 1014 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), 1015 []>; 1016 def ri : TRAPSPri<0b111010, 1017 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), 1018 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), 1019 []>; 1020} 1021 1022let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in 1023 defm TICC : TRAP<"%icc">; 1024 1025 1026let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in 1027 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; 1028 1029let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in 1030 def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>; 1031 1032// Section B.28 - Read State Register Instructions 1033let rs2 = 0 in 1034 def RDASR : F3_1<2, 0b101000, 1035 (outs IntRegs:$rd), (ins ASRRegs:$rs1), 1036 "rd $rs1, $rd", []>; 1037 1038// PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 1039let Predicates = [HasNoV9] in { 1040 let rs2 = 0, rs1 = 0, Uses=[PSR] in 1041 def RDPSR : F3_1<2, 0b101001, 1042 (outs IntRegs:$rd), (ins), 1043 "rd %psr, $rd", []>; 1044 1045 let rs2 = 0, rs1 = 0, Uses=[WIM] in 1046 def RDWIM : F3_1<2, 0b101010, 1047 (outs IntRegs:$rd), (ins), 1048 "rd %wim, $rd", []>; 1049 1050 let rs2 = 0, rs1 = 0, Uses=[TBR] in 1051 def RDTBR : F3_1<2, 0b101011, 1052 (outs IntRegs:$rd), (ins), 1053 "rd %tbr, $rd", []>; 1054} 1055 1056// PC don't exist on the SparcV8, only the V9. 1057let Predicates = [HasV9] in { 1058 let rs2 = 0, rs1 = 5 in 1059 def RDPC : F3_1<2, 0b101000, 1060 (outs IntRegs:$rd), (ins), 1061 "rd %pc, $rd", []>; 1062} 1063 1064// Section B.29 - Write State Register Instructions 1065def WRASRrr : F3_1<2, 0b110000, 1066 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 1067 "wr $rs1, $rs2, $rd", []>; 1068def WRASRri : F3_2<2, 0b110000, 1069 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 1070 "wr $rs1, $simm13, $rd", []>; 1071 1072// PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 1073let Predicates = [HasNoV9] in { 1074 let Defs = [PSR], rd=0 in { 1075 def WRPSRrr : F3_1<2, 0b110001, 1076 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1077 "wr $rs1, $rs2, %psr", []>; 1078 def WRPSRri : F3_2<2, 0b110001, 1079 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1080 "wr $rs1, $simm13, %psr", []>; 1081 } 1082 1083 let Defs = [WIM], rd=0 in { 1084 def WRWIMrr : F3_1<2, 0b110010, 1085 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1086 "wr $rs1, $rs2, %wim", []>; 1087 def WRWIMri : F3_2<2, 0b110010, 1088 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1089 "wr $rs1, $simm13, %wim", []>; 1090 } 1091 1092 let Defs = [TBR], rd=0 in { 1093 def WRTBRrr : F3_1<2, 0b110011, 1094 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1095 "wr $rs1, $rs2, %tbr", []>; 1096 def WRTBRri : F3_2<2, 0b110011, 1097 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1098 "wr $rs1, $simm13, %tbr", []>; 1099 } 1100} 1101 1102// Section B.30 - STBAR Instruction 1103let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in 1104 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>; 1105 1106 1107// Section B.31 - Unimplemented Instruction 1108let rd = 0 in 1109 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22), 1110 "unimp $imm22", []>; 1111 1112// Section B.32 - Flush Instruction Memory 1113let rd = 0 in { 1114 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr), 1115 "flush $addr", []>; 1116 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr), 1117 "flush $addr", []>; 1118 1119 // The no-arg FLUSH is only here for the benefit of the InstAlias 1120 // "flush", which cannot seem to use FLUSHrr, due to the inability 1121 // to construct a MEMrr with fixed G0 registers. 1122 let rs1 = 0, rs2 = 0 in 1123 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>; 1124} 1125 1126// Section B.33 - Floating-point Operate (FPop) Instructions 1127 1128// Convert Integer to Floating-point Instructions, p. 141 1129def FITOS : F3_3u<2, 0b110100, 0b011000100, 1130 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1131 "fitos $rs2, $rd", 1132 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))], 1133 IIC_fpu_fast_instr>; 1134def FITOD : F3_3u<2, 0b110100, 0b011001000, 1135 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 1136 "fitod $rs2, $rd", 1137 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))], 1138 IIC_fpu_fast_instr>; 1139def FITOQ : F3_3u<2, 0b110100, 0b011001100, 1140 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 1141 "fitoq $rs2, $rd", 1142 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>, 1143 Requires<[HasHardQuad]>; 1144 1145// Convert Floating-point to Integer Instructions, p. 142 1146def FSTOI : F3_3u<2, 0b110100, 0b011010001, 1147 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1148 "fstoi $rs2, $rd", 1149 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))], 1150 IIC_fpu_fast_instr>; 1151def FDTOI : F3_3u<2, 0b110100, 0b011010010, 1152 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 1153 "fdtoi $rs2, $rd", 1154 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))], 1155 IIC_fpu_fast_instr>; 1156def FQTOI : F3_3u<2, 0b110100, 0b011010011, 1157 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 1158 "fqtoi $rs2, $rd", 1159 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>, 1160 Requires<[HasHardQuad]>; 1161 1162// Convert between Floating-point Formats Instructions, p. 143 1163def FSTOD : F3_3u<2, 0b110100, 0b011001001, 1164 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 1165 "fstod $rs2, $rd", 1166 [(set f64:$rd, (fpextend f32:$rs2))], 1167 IIC_fpu_stod>; 1168def FSTOQ : F3_3u<2, 0b110100, 0b011001101, 1169 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 1170 "fstoq $rs2, $rd", 1171 [(set f128:$rd, (fpextend f32:$rs2))]>, 1172 Requires<[HasHardQuad]>; 1173def FDTOS : F3_3u<2, 0b110100, 0b011000110, 1174 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 1175 "fdtos $rs2, $rd", 1176 [(set f32:$rd, (fpround f64:$rs2))], 1177 IIC_fpu_fast_instr>; 1178def FDTOQ : F3_3u<2, 0b110100, 0b011001110, 1179 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 1180 "fdtoq $rs2, $rd", 1181 [(set f128:$rd, (fpextend f64:$rs2))]>, 1182 Requires<[HasHardQuad]>; 1183def FQTOS : F3_3u<2, 0b110100, 0b011000111, 1184 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 1185 "fqtos $rs2, $rd", 1186 [(set f32:$rd, (fpround f128:$rs2))]>, 1187 Requires<[HasHardQuad]>; 1188def FQTOD : F3_3u<2, 0b110100, 0b011001011, 1189 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 1190 "fqtod $rs2, $rd", 1191 [(set f64:$rd, (fpround f128:$rs2))]>, 1192 Requires<[HasHardQuad]>; 1193 1194// Floating-point Move Instructions, p. 144 1195def FMOVS : F3_3u<2, 0b110100, 0b000000001, 1196 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1197 "fmovs $rs2, $rd", []>; 1198def FNEGS : F3_3u<2, 0b110100, 0b000000101, 1199 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1200 "fnegs $rs2, $rd", 1201 [(set f32:$rd, (fneg f32:$rs2))], 1202 IIC_fpu_negs>; 1203def FABSS : F3_3u<2, 0b110100, 0b000001001, 1204 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1205 "fabss $rs2, $rd", 1206 [(set f32:$rd, (fabs f32:$rs2))], 1207 IIC_fpu_abs>; 1208 1209 1210// Floating-point Square Root Instructions, p.145 1211// FSQRTS generates an erratum on LEON processors, so by disabling this instruction 1212// this will be promoted to use FSQRTD with doubles instead. 1213let Predicates = [HasNoFdivSqrtFix] in 1214def FSQRTS : F3_3u<2, 0b110100, 0b000101001, 1215 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1216 "fsqrts $rs2, $rd", 1217 [(set f32:$rd, (fsqrt f32:$rs2))], 1218 IIC_fpu_sqrts>; 1219def FSQRTD : F3_3u<2, 0b110100, 0b000101010, 1220 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1221 "fsqrtd $rs2, $rd", 1222 [(set f64:$rd, (fsqrt f64:$rs2))], 1223 IIC_fpu_sqrtd>; 1224def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, 1225 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1226 "fsqrtq $rs2, $rd", 1227 [(set f128:$rd, (fsqrt f128:$rs2))]>, 1228 Requires<[HasHardQuad]>; 1229 1230 1231 1232// Floating-point Add and Subtract Instructions, p. 146 1233def FADDS : F3_3<2, 0b110100, 0b001000001, 1234 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1235 "fadds $rs1, $rs2, $rd", 1236 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))], 1237 IIC_fpu_fast_instr>; 1238def FADDD : F3_3<2, 0b110100, 0b001000010, 1239 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1240 "faddd $rs1, $rs2, $rd", 1241 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))], 1242 IIC_fpu_fast_instr>; 1243def FADDQ : F3_3<2, 0b110100, 0b001000011, 1244 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1245 "faddq $rs1, $rs2, $rd", 1246 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>, 1247 Requires<[HasHardQuad]>; 1248 1249def FSUBS : F3_3<2, 0b110100, 0b001000101, 1250 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1251 "fsubs $rs1, $rs2, $rd", 1252 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))], 1253 IIC_fpu_fast_instr>; 1254def FSUBD : F3_3<2, 0b110100, 0b001000110, 1255 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1256 "fsubd $rs1, $rs2, $rd", 1257 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))], 1258 IIC_fpu_fast_instr>; 1259def FSUBQ : F3_3<2, 0b110100, 0b001000111, 1260 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1261 "fsubq $rs1, $rs2, $rd", 1262 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>, 1263 Requires<[HasHardQuad]>; 1264 1265 1266// Floating-point Multiply and Divide Instructions, p. 147 1267def FMULS : F3_3<2, 0b110100, 0b001001001, 1268 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1269 "fmuls $rs1, $rs2, $rd", 1270 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))], 1271 IIC_fpu_muls>, 1272 Requires<[HasFMULS]>; 1273def FMULD : F3_3<2, 0b110100, 0b001001010, 1274 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1275 "fmuld $rs1, $rs2, $rd", 1276 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))], 1277 IIC_fpu_muld>; 1278def FMULQ : F3_3<2, 0b110100, 0b001001011, 1279 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1280 "fmulq $rs1, $rs2, $rd", 1281 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>, 1282 Requires<[HasHardQuad]>; 1283 1284def FSMULD : F3_3<2, 0b110100, 0b001101001, 1285 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1286 "fsmuld $rs1, $rs2, $rd", 1287 [(set f64:$rd, (fmul (fpextend f32:$rs1), 1288 (fpextend f32:$rs2)))], 1289 IIC_fpu_muld>, 1290 Requires<[HasFSMULD]>; 1291def FDMULQ : F3_3<2, 0b110100, 0b001101110, 1292 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1293 "fdmulq $rs1, $rs2, $rd", 1294 [(set f128:$rd, (fmul (fpextend f64:$rs1), 1295 (fpextend f64:$rs2)))]>, 1296 Requires<[HasHardQuad]>; 1297 1298// FDIVS generates an erratum on LEON processors, so by disabling this instruction 1299// this will be promoted to use FDIVD with doubles instead. 1300def FDIVS : F3_3<2, 0b110100, 0b001001101, 1301 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1302 "fdivs $rs1, $rs2, $rd", 1303 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))], 1304 IIC_fpu_divs>; 1305def FDIVD : F3_3<2, 0b110100, 0b001001110, 1306 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1307 "fdivd $rs1, $rs2, $rd", 1308 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))], 1309 IIC_fpu_divd>; 1310def FDIVQ : F3_3<2, 0b110100, 0b001001111, 1311 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1312 "fdivq $rs1, $rs2, $rd", 1313 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>, 1314 Requires<[HasHardQuad]>; 1315 1316// Floating-point Compare Instructions, p. 148 1317// Note: the 2nd template arg is different for these guys. 1318// Note 2: the result of a FCMP is not available until the 2nd cycle 1319// after the instr is retired, but there is no interlock in Sparc V8. 1320// This behavior is modeled with a forced noop after the instruction in 1321// DelaySlotFiller. 1322 1323let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in { 1324 def FCMPS : F3_3c<2, 0b110101, 0b001010001, 1325 (outs), (ins FPRegs:$rs1, FPRegs:$rs2), 1326 "fcmps $rs1, $rs2", 1327 [(SPcmpfcc f32:$rs1, f32:$rs2)], 1328 IIC_fpu_fast_instr>; 1329 def FCMPD : F3_3c<2, 0b110101, 0b001010010, 1330 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1331 "fcmpd $rs1, $rs2", 1332 [(SPcmpfcc f64:$rs1, f64:$rs2)], 1333 IIC_fpu_fast_instr>; 1334 def FCMPQ : F3_3c<2, 0b110101, 0b001010011, 1335 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1336 "fcmpq $rs1, $rs2", 1337 [(SPcmpfcc f128:$rs1, f128:$rs2)]>, 1338 Requires<[HasHardQuad]>; 1339} 1340 1341//===----------------------------------------------------------------------===// 1342// Instructions for Thread Local Storage(TLS). 1343//===----------------------------------------------------------------------===// 1344let isAsmParserOnly = 1 in { 1345def TLS_ADDrr : F3_1<2, 0b000000, 1346 (outs IntRegs:$rd), 1347 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 1348 "add $rs1, $rs2, $rd, $sym", 1349 [(set i32:$rd, 1350 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>; 1351 1352let mayLoad = 1 in 1353 def TLS_LDrr : F3_1<3, 0b000000, 1354 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 1355 "ld [$addr], $dst, $sym", 1356 [(set i32:$dst, 1357 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 1358 1359let Uses = [O6], isCall = 1, hasDelaySlot = 1 in 1360 def TLS_CALL : InstSP<(outs), 1361 (ins calltarget:$disp, TLSSym:$sym, variable_ops), 1362 "call $disp, $sym", 1363 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)], 1364 IIC_jmp_or_call> { 1365 bits<30> disp; 1366 let op = 1; 1367 let Inst{29-0} = disp; 1368} 1369} 1370 1371//===----------------------------------------------------------------------===// 1372// V9 Instructions 1373//===----------------------------------------------------------------------===// 1374 1375// V9 Conditional Moves. 1376let Predicates = [HasV9], Constraints = "$f = $rd" in { 1377 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 1378 let Uses = [ICC], intcc = 1, cc = 0b00 in { 1379 def MOVICCrr 1380 : F4_1<0b101100, (outs IntRegs:$rd), 1381 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1382 "mov$cond %icc, $rs2, $rd", 1383 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>; 1384 1385 def MOVICCri 1386 : F4_2<0b101100, (outs IntRegs:$rd), 1387 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1388 "mov$cond %icc, $simm11, $rd", 1389 [(set i32:$rd, 1390 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>; 1391 } 1392 1393 let Uses = [FCC0], intcc = 0, cc = 0b00 in { 1394 def MOVFCCrr 1395 : F4_1<0b101100, (outs IntRegs:$rd), 1396 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1397 "mov$cond %fcc0, $rs2, $rd", 1398 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>; 1399 def MOVFCCri 1400 : F4_2<0b101100, (outs IntRegs:$rd), 1401 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1402 "mov$cond %fcc0, $simm11, $rd", 1403 [(set i32:$rd, 1404 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>; 1405 } 1406 1407 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in { 1408 def FMOVS_ICC 1409 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1410 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1411 "fmovs$cond %icc, $rs2, $rd", 1412 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>; 1413 def FMOVD_ICC 1414 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1415 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1416 "fmovd$cond %icc, $rs2, $rd", 1417 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>; 1418 def FMOVQ_ICC 1419 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1420 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1421 "fmovq$cond %icc, $rs2, $rd", 1422 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>, 1423 Requires<[HasHardQuad]>; 1424 } 1425 1426 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in { 1427 def FMOVS_FCC 1428 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1429 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1430 "fmovs$cond %fcc0, $rs2, $rd", 1431 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>; 1432 def FMOVD_FCC 1433 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1434 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1435 "fmovd$cond %fcc0, $rs2, $rd", 1436 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>; 1437 def FMOVQ_FCC 1438 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1439 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1440 "fmovq$cond %fcc0, $rs2, $rd", 1441 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>, 1442 Requires<[HasHardQuad]>; 1443 } 1444 1445} 1446 1447// Floating-Point Move Instructions, p. 164 of the V9 manual. 1448let Predicates = [HasV9] in { 1449 def FMOVD : F3_3u<2, 0b110100, 0b000000010, 1450 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1451 "fmovd $rs2, $rd", []>; 1452 def FMOVQ : F3_3u<2, 0b110100, 0b000000011, 1453 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1454 "fmovq $rs2, $rd", []>, 1455 Requires<[HasHardQuad]>; 1456 def FNEGD : F3_3u<2, 0b110100, 0b000000110, 1457 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1458 "fnegd $rs2, $rd", 1459 [(set f64:$rd, (fneg f64:$rs2))]>; 1460 def FNEGQ : F3_3u<2, 0b110100, 0b000000111, 1461 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1462 "fnegq $rs2, $rd", 1463 [(set f128:$rd, (fneg f128:$rs2))]>, 1464 Requires<[HasHardQuad]>; 1465 def FABSD : F3_3u<2, 0b110100, 0b000001010, 1466 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1467 "fabsd $rs2, $rd", 1468 [(set f64:$rd, (fabs f64:$rs2))]>; 1469 def FABSQ : F3_3u<2, 0b110100, 0b000001011, 1470 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1471 "fabsq $rs2, $rd", 1472 [(set f128:$rd, (fabs f128:$rs2))]>, 1473 Requires<[HasHardQuad]>; 1474} 1475 1476// Floating-point compare instruction with %fcc0-%fcc3. 1477def V9FCMPS : F3_3c<2, 0b110101, 0b001010001, 1478 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1479 "fcmps $rd, $rs1, $rs2", []>; 1480def V9FCMPD : F3_3c<2, 0b110101, 0b001010010, 1481 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1482 "fcmpd $rd, $rs1, $rs2", []>; 1483def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011, 1484 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1485 "fcmpq $rd, $rs1, $rs2", []>, 1486 Requires<[HasHardQuad]>; 1487 1488let hasSideEffects = 1 in { 1489 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101, 1490 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1491 "fcmpes $rd, $rs1, $rs2", []>; 1492 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110, 1493 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1494 "fcmped $rd, $rs1, $rs2", []>; 1495 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111, 1496 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1497 "fcmpeq $rd, $rs1, $rs2", []>, 1498 Requires<[HasHardQuad]>; 1499} 1500 1501// Floating point conditional move instrucitons with %fcc0-%fcc3. 1502let Predicates = [HasV9] in { 1503 let Constraints = "$f = $rd", intcc = 0 in { 1504 def V9MOVFCCrr 1505 : F4_1<0b101100, (outs IntRegs:$rd), 1506 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1507 "mov$cond $cc, $rs2, $rd", []>; 1508 def V9MOVFCCri 1509 : F4_2<0b101100, (outs IntRegs:$rd), 1510 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1511 "mov$cond $cc, $simm11, $rd", []>; 1512 def V9FMOVS_FCC 1513 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1514 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1515 "fmovs$cond $opf_cc, $rs2, $rd", []>; 1516 def V9FMOVD_FCC 1517 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1518 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1519 "fmovd$cond $opf_cc, $rs2, $rd", []>; 1520 def V9FMOVQ_FCC 1521 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1522 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1523 "fmovq$cond $opf_cc, $rs2, $rd", []>, 1524 Requires<[HasHardQuad]>; 1525 } // Constraints = "$f = $rd", ... 1526} // let Predicates = [hasV9] 1527 1528 1529// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 1530// the top 32-bits before using it. To do this clearing, we use a SRLri X,0. 1531let rs1 = 0 in 1532 def POPCrr : F3_1<2, 0b101110, 1533 (outs IntRegs:$rd), (ins IntRegs:$rs2), 1534 "popc $rs2, $rd", []>, Requires<[HasV9]>; 1535def : Pat<(i32 (ctpop i32:$src)), 1536 (POPCrr (SRLri $src, 0))>; 1537 1538let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in 1539 def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13), 1540 "membar $simm13", []>; 1541 1542let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in 1543 def SIR: F3_2<2, 0b110000, (outs), 1544 (ins simm13Op:$simm13), 1545 "sir $simm13", []>; 1546 1547// The CAS instruction, unlike other instructions, only comes in a 1548// form which requires an ASI be provided. The ASI value hardcoded 1549// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9. 1550let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in 1551 def CASrr: F3_1_asi<3, 0b111100, 1552 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1553 IntRegs:$swap), 1554 "cas [$rs1], $rs2, $rd", 1555 [(set i32:$rd, 1556 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; 1557 1558 1559// CASA is supported as an instruction on some LEON3 and all LEON4 processors. 1560// This version can be automatically lowered from C code, selecting ASI 10 1561let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in 1562 def CASAasi10: F3_1_asi<3, 0b111100, 1563 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1564 IntRegs:$swap), 1565 "casa [$rs1] 10, $rs2, $rd", 1566 [(set i32:$rd, 1567 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; 1568 1569// CASA supported on some LEON3 and all LEON4 processors. Same pattern as 1570// CASrr, above, but with a different ASI. This version is supported for 1571// inline assembly lowering only. 1572let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in 1573 def CASArr: F3_1_asi<3, 0b111100, 1574 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1575 IntRegs:$swap, i8imm:$asi), 1576 "casa [$rs1] $asi, $rs2, $rd", []>; 1577 1578// TODO: Add DAG sequence to lower these instructions. Currently, only provided 1579// as inline assembler-supported instructions. 1580let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { 1581 def SMACrr : F3_1<2, 0b111111, 1582 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), 1583 "smac $rs1, $rs2, $rd", 1584 [], IIC_smac_umac>; 1585 1586 def SMACri : F3_2<2, 0b111111, 1587 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), 1588 "smac $rs1, $simm13, $rd", 1589 [], IIC_smac_umac>; 1590 1591 def UMACrr : F3_1<2, 0b111110, 1592 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), 1593 "umac $rs1, $rs2, $rd", 1594 [], IIC_smac_umac>; 1595 1596 def UMACri : F3_2<2, 0b111110, 1597 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), 1598 "umac $rs1, $simm13, $rd", 1599 [], IIC_smac_umac>; 1600} 1601 1602// The partial write WRPSR instruction has a non-zero destination 1603// register value to separate it from the standard instruction. 1604let Predicates = [HasPWRPSR], Defs = [PSR], rd=1 in { 1605 def PWRPSRrr : F3_1<2, 0b110001, 1606 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1607 "pwr $rs1, $rs2, %psr", []>; 1608 def PWRPSRri : F3_2<2, 0b110001, 1609 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1610 "pwr $rs1, $simm13, %psr", []>; 1611} 1612 1613let Defs = [ICC] in { 1614defm TADDCC : F3_12np<"taddcc", 0b100000>; 1615defm TSUBCC : F3_12np<"tsubcc", 0b100001>; 1616 1617let hasSideEffects = 1 in { 1618 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>; 1619 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>; 1620} 1621} 1622 1623// Section A.42 - Prefetch Data 1624let Predicates = [HasV9] in { 1625 def PREFETCHr : F3_1<3, 0b101101, 1626 (outs), (ins MEMrr:$addr, shift_imm5:$rd), 1627 "prefetch [$addr], $rd", []>; 1628 def PREFETCHi : F3_2<3, 0b101101, 1629 (outs), (ins MEMri:$addr, shift_imm5:$rd), 1630 "prefetch [$addr], $rd", []>; 1631} 1632 1633 1634 1635// Section A.43 - Read Privileged Register Instructions 1636let Predicates = [HasV9] in { 1637let rs2 = 0 in 1638 def RDPR : F3_1<2, 0b101010, 1639 (outs IntRegs:$rd), (ins PRRegs:$rs1), 1640 "rdpr $rs1, $rd", []>; 1641} 1642 1643// Section A.62 - Write Privileged Register Instructions 1644let Predicates = [HasV9] in { 1645 def WRPRrr : F3_1<2, 0b110010, 1646 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 1647 "wrpr $rs1, $rs2, $rd", []>; 1648 def WRPRri : F3_2<2, 0b110010, 1649 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 1650 "wrpr $rs1, $simm13, $rd", []>; 1651} 1652 1653//===----------------------------------------------------------------------===// 1654// Non-Instruction Patterns 1655//===----------------------------------------------------------------------===// 1656 1657// Zero immediate. 1658def : Pat<(i32 0), 1659 (ORrr (i32 G0), (i32 G0))>; 1660// Small immediates. 1661def : Pat<(i32 simm13:$val), 1662 (ORri (i32 G0), imm:$val)>; 1663// Arbitrary immediates. 1664def : Pat<(i32 imm:$val), 1665 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 1666 1667 1668// Global addresses, constant pool entries 1669let Predicates = [Is32Bit] in { 1670 1671def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 1672def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 1673def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 1674def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 1675 1676// GlobalTLS addresses 1677def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 1678def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>; 1679def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 1680 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1681def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 1682 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1683 1684// Blockaddress 1685def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 1686def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 1687 1688// Add reg, lo. This is used when taking the addr of a global/constpool entry. 1689def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 1690def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 1691def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 1692 (ADDri $r, tblockaddress:$in)>; 1693} 1694 1695// Calls: 1696def : Pat<(call tglobaladdr:$dst), 1697 (CALL tglobaladdr:$dst)>; 1698def : Pat<(call texternalsym:$dst), 1699 (CALL texternalsym:$dst)>; 1700 1701// Map integer extload's to zextloads. 1702def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1703def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1704def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1705def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1706def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1707def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1708 1709// zextload bool -> zextload byte 1710def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1711def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1712 1713// store 0, addr -> store %g0, addr 1714def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 1715def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 1716 1717// store bar for all atomic_fence in V8. 1718let Predicates = [HasNoV9] in 1719 def : Pat<(atomic_fence timm, timm), (STBAR)>; 1720 1721let Predicates = [HasV9] in 1722 def : Pat<(atomic_fence timm, timm), (MEMBARi 0xf)>; 1723 1724// atomic_load addr -> load addr 1725def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1726def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1727def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1728def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1729def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>; 1730def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>; 1731 1732// atomic_store val, addr -> store val, addr 1733def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>; 1734def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>; 1735def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>; 1736def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>; 1737def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>; 1738def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>; 1739 1740// extract_vector 1741def : Pat<(extractelt (v2i32 IntPair:$Rn), 0), 1742 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>; 1743def : Pat<(extractelt (v2i32 IntPair:$Rn), 1), 1744 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>; 1745 1746// build_vector 1747def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)), 1748 (INSERT_SUBREG 1749 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even), 1750 (i32 IntRegs:$a2), sub_odd)>; 1751 1752 1753include "SparcInstr64Bit.td" 1754include "SparcInstrVIS.td" 1755include "SparcInstrAliases.td" 1756