1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the Sparc instructions in TableGen format. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Instruction format superclass 15//===----------------------------------------------------------------------===// 16 17include "SparcInstrFormats.td" 18 19//===----------------------------------------------------------------------===// 20// Feature predicates. 21//===----------------------------------------------------------------------===// 22 23// True when generating 32-bit code. 24def Is32Bit : Predicate<"!Subtarget->is64Bit()">; 25 26// True when generating 64-bit code. This also implies HasV9. 27def Is64Bit : Predicate<"Subtarget->is64Bit()">; 28 29def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">, 30 AssemblerPredicate<(all_of FeatureSoftMulDiv)>; 31 32// HasV9 - This predicate is true when the target processor supports V9 33// instructions. Note that the machine may be running in 32-bit mode. 34def HasV9 : Predicate<"Subtarget->isV9()">, 35 AssemblerPredicate<(all_of FeatureV9)>; 36 37// HasNoV9 - This predicate is true when the target doesn't have V9 38// instructions. Use of this is just a hack for the isel not having proper 39// costs for V8 instructions that are more expensive than their V9 ones. 40def HasNoV9 : Predicate<"!Subtarget->isV9()">; 41 42// HasVIS - This is true when the target processor has VIS extensions. 43def HasVIS : Predicate<"Subtarget->isVIS()">, 44 AssemblerPredicate<(all_of FeatureVIS)>; 45def HasVIS2 : Predicate<"Subtarget->isVIS2()">, 46 AssemblerPredicate<(all_of FeatureVIS2)>; 47def HasVIS3 : Predicate<"Subtarget->isVIS3()">, 48 AssemblerPredicate<(all_of FeatureVIS3)>; 49 50// HasHardQuad - This is true when the target processor supports quad floating 51// point instructions. 52def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">; 53 54// HasLeonCASA - This is true when the target processor supports the CASA 55// instruction 56def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">; 57 58// HasPWRPSR - This is true when the target processor supports partial 59// writes to the PSR register that only affects the ET field. 60def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">, 61 AssemblerPredicate<(all_of FeaturePWRPSR)>; 62 63// HasUMAC_SMAC - This is true when the target processor supports the 64// UMAC and SMAC instructions 65def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">; 66 67def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">; 68def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">; 69def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">; 70 71// UseDeprecatedInsts - This predicate is true when the target processor is a 72// V8, or when it is V9 but the V8 deprecated instructions are efficient enough 73// to use when appropriate. In either of these cases, the instruction selector 74// will pick deprecated instructions. 75def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">; 76 77//===----------------------------------------------------------------------===// 78// Instruction Pattern Stuff 79//===----------------------------------------------------------------------===// 80 81def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 82 83def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 84 85def LO10 : SDNodeXForm<imm, [{ 86 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N), 87 MVT::i32); 88}]>; 89 90def HI22 : SDNodeXForm<imm, [{ 91 // Transformation function: shift the immediate value down into the low bits. 92 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N), 93 MVT::i32); 94}]>; 95 96// Return the complement of a HI22 immediate value. 97def HI22_not : SDNodeXForm<imm, [{ 98 return CurDAG->getTargetConstant(~(unsigned)N->getZExtValue() >> 10, SDLoc(N), 99 MVT::i32); 100}]>; 101 102def SETHIimm : PatLeaf<(imm), [{ 103 return isShiftedUInt<22, 10>(N->getZExtValue()); 104}], HI22>; 105 106// The N->hasOneUse() prevents the immediate from being instantiated in both 107// normal and complement form. 108def SETHIimm_not : PatLeaf<(i32 imm), [{ 109 return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue()); 110}], HI22_not>; 111 112// Addressing modes. 113def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>; 114def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>; 115 116// Constrained operands for the shift operations. 117class ShiftAmtImmAsmOperand<int Bits> : AsmOperandClass { 118 let Name = "ShiftAmtImm" # Bits; 119 let ParserMethod = "parseShiftAmtImm<" # Bits # ">"; 120} 121def shift_imm5 : Operand<i32> { 122 let ParserMatchClass = ShiftAmtImmAsmOperand<5>; 123} 124def shift_imm6 : Operand<i32> { 125 let ParserMatchClass = ShiftAmtImmAsmOperand<6>; 126} 127 128// Address operands 129def SparcMEMrrAsmOperand : AsmOperandClass { 130 let Name = "MEMrr"; 131 let ParserMethod = "parseMEMOperand"; 132} 133 134def SparcMEMriAsmOperand : AsmOperandClass { 135 let Name = "MEMri"; 136 let ParserMethod = "parseMEMOperand"; 137} 138 139def MEMrr : Operand<iPTR> { 140 let PrintMethod = "printMemOperand"; 141 let MIOperandInfo = (ops ptr_rc, ptr_rc); 142 let ParserMatchClass = SparcMEMrrAsmOperand; 143} 144def MEMri : Operand<iPTR> { 145 let PrintMethod = "printMemOperand"; 146 let MIOperandInfo = (ops ptr_rc, i32imm); 147 let ParserMatchClass = SparcMEMriAsmOperand; 148} 149 150def TLSSym : Operand<iPTR>; 151 152def SparcMembarTagAsmOperand : AsmOperandClass { 153 let Name = "MembarTag"; 154 let ParserMethod = "parseMembarTag"; 155} 156 157def MembarTag : Operand<i32> { 158 let PrintMethod = "printMembarTag"; 159 let ParserMatchClass = SparcMembarTagAsmOperand; 160} 161 162// Branch targets have OtherVT type. 163def brtarget : Operand<OtherVT> { 164 let EncoderMethod = "getBranchTargetOpValue"; 165} 166 167def bprtarget : Operand<OtherVT> { 168 let EncoderMethod = "getBranchPredTargetOpValue"; 169} 170 171def bprtarget16 : Operand<OtherVT> { 172 let EncoderMethod = "getBranchOnRegTargetOpValue"; 173} 174 175def SparcCallTargetAsmOperand : AsmOperandClass { 176 let Name = "CallTarget"; 177 let ParserMethod = "parseCallTarget"; 178} 179 180def calltarget : Operand<i32> { 181 let EncoderMethod = "getCallTargetOpValue"; 182 let DecoderMethod = "DecodeCall"; 183 let ParserMatchClass = SparcCallTargetAsmOperand; 184} 185 186def simm13Op : Operand<i32> { 187 let DecoderMethod = "DecodeSIMM13"; 188 let EncoderMethod = "getSImm13OpValue"; 189} 190 191// Operand for printing out a condition code. 192let PrintMethod = "printCCOperand" in 193 def CCOp : Operand<i32>; 194 195def SDTSPcmpicc : 196SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 197def SDTSPcmpfcc : 198SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 199def SDTSPbrcc : 200SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 201def SDTSPselectcc : 202SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 203def SDTSPFTOI : 204SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 205def SDTSPITOF : 206SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 207def SDTSPFTOX : 208SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>; 209def SDTSPXTOF : 210SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>; 211 212def SDTSPtlsadd : 213SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 214def SDTSPtlsld : 215SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>; 216 217def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>; 218def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 219def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 220def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 221def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 222 223def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 224def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 225 226def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 227def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 228def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>; 229def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>; 230 231def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 232def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>; 233def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 234 235// These are target-independent nodes, but have target-specific formats. 236def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>, 237 SDTCisVT<1, i32> ]>; 238def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 239 SDTCisVT<1, i32> ]>; 240 241def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 242 [SDNPHasChain, SDNPOutGlue]>; 243def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 244 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 245 246def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 247def call : SDNode<"SPISD::CALL", SDT_SPCall, 248 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 249 SDNPVariadic]>; 250 251def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 252def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 253 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 254 255def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 256 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>; 257 258def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>; 259def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>; 260def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall, 261 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 262 SDNPVariadic]>; 263 264def getPCX : Operand<iPTR> { 265 let PrintMethod = "printGetPCX"; 266} 267 268//===----------------------------------------------------------------------===// 269// SPARC Flag Conditions 270//===----------------------------------------------------------------------===// 271 272// Note that these values must be kept in sync with the CCOp::CondCode enum 273// values. 274class ICC_VAL<int N> : PatLeaf<(i32 N)>; 275def ICC_NE : ICC_VAL< 9>; // Not Equal 276def ICC_E : ICC_VAL< 1>; // Equal 277def ICC_G : ICC_VAL<10>; // Greater 278def ICC_LE : ICC_VAL< 2>; // Less or Equal 279def ICC_GE : ICC_VAL<11>; // Greater or Equal 280def ICC_L : ICC_VAL< 3>; // Less 281def ICC_GU : ICC_VAL<12>; // Greater Unsigned 282def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 283def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 284def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 285def ICC_POS : ICC_VAL<14>; // Positive 286def ICC_NEG : ICC_VAL< 6>; // Negative 287def ICC_VC : ICC_VAL<15>; // Overflow Clear 288def ICC_VS : ICC_VAL< 7>; // Overflow Set 289 290class FCC_VAL<int N> : PatLeaf<(i32 N)>; 291def FCC_U : FCC_VAL<23>; // Unordered 292def FCC_G : FCC_VAL<22>; // Greater 293def FCC_UG : FCC_VAL<21>; // Unordered or Greater 294def FCC_L : FCC_VAL<20>; // Less 295def FCC_UL : FCC_VAL<19>; // Unordered or Less 296def FCC_LG : FCC_VAL<18>; // Less or Greater 297def FCC_NE : FCC_VAL<17>; // Not Equal 298def FCC_E : FCC_VAL<25>; // Equal 299def FCC_UE : FCC_VAL<26>; // Unordered or Equal 300def FCC_GE : FCC_VAL<27>; // Greater or Equal 301def FCC_UGE : FCC_VAL<28>; // Unordered or Greater or Equal 302def FCC_LE : FCC_VAL<29>; // Less or Equal 303def FCC_ULE : FCC_VAL<30>; // Unordered or Less or Equal 304def FCC_O : FCC_VAL<31>; // Ordered 305 306class CPCC_VAL<int N> : PatLeaf<(i32 N)>; 307def CPCC_3 : CPCC_VAL<39>; // 3 308def CPCC_2 : CPCC_VAL<38>; // 2 309def CPCC_23 : CPCC_VAL<37>; // 2 or 3 310def CPCC_1 : CPCC_VAL<36>; // 1 311def CPCC_13 : CPCC_VAL<35>; // 1 or 3 312def CPCC_12 : CPCC_VAL<34>; // 1 or 2 313def CPCC_123 : CPCC_VAL<33>; // 1 or 2 or 3 314def CPCC_0 : CPCC_VAL<41>; // 0 315def CPCC_03 : CPCC_VAL<42>; // 0 or 3 316def CPCC_02 : CPCC_VAL<43>; // 0 or 2 317def CPCC_023 : CPCC_VAL<44>; // 0 or 2 or 3 318def CPCC_01 : CPCC_VAL<45>; // 0 or 1 319def CPCC_013 : CPCC_VAL<46>; // 0 or 1 or 3 320def CPCC_012 : CPCC_VAL<47>; // 0 or 1 or 2 321 322//===----------------------------------------------------------------------===// 323// Instruction Class Templates 324//===----------------------------------------------------------------------===// 325 326/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 327multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode, 328 RegisterClass RC, ValueType Ty, Operand immOp, 329 InstrItinClass itin = IIC_iu_instr> { 330 def rr : F3_1<2, Op3Val, 331 (outs RC:$rd), (ins RC:$rs1, RC:$rs2), 332 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 333 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))], 334 itin>; 335 def ri : F3_2<2, Op3Val, 336 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13), 337 !strconcat(OpcStr, " $rs1, $simm13, $rd"), 338 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))], 339 itin>; 340} 341 342/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 343/// pattern. 344multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> { 345 def rr : F3_1<2, Op3Val, 346 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 347 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [], 348 itin>; 349 def ri : F3_2<2, Op3Val, 350 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 351 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [], 352 itin>; 353} 354 355// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 356multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 357 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> { 358 def rr : F3_1<3, Op3Val, 359 (outs RC:$dst), (ins MEMrr:$addr), 360 !strconcat(OpcStr, " [$addr], $dst"), 361 [(set Ty:$dst, (OpNode ADDRrr:$addr))], 362 itin>; 363 def ri : F3_2<3, Op3Val, 364 (outs RC:$dst), (ins MEMri:$addr), 365 !strconcat(OpcStr, " [$addr], $dst"), 366 [(set Ty:$dst, (OpNode ADDRri:$addr))], 367 itin>; 368} 369 370// TODO: Instructions of the LoadASI class are currently asm only; hooking up 371// CodeGen's address spaces to use these is a future task. 372class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 373 RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> : 374 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi), 375 !strconcat(OpcStr, "a [$addr] $asi, $dst"), 376 []>; 377 378// LoadA multiclass - As above, but also define alternate address space variant 379multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val, 380 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, 381 InstrItinClass itin = NoItinerary> : 382 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> { 383 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>; 384} 385 386// The LDSTUB instruction is supported for asm only. 387// It is unlikely that general-purpose code could make use of it. 388// CAS is preferred for sparc v9. 389def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr), 390 "ldstub [$addr], $dst", []>; 391def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr), 392 "ldstub [$addr], $dst", []>; 393def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst), 394 (ins MEMrr:$addr, i8imm:$asi), 395 "ldstuba [$addr] $asi, $dst", []>; 396 397// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. 398multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, 399 RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> { 400 def rr : F3_1<3, Op3Val, 401 (outs), (ins MEMrr:$addr, RC:$rd), 402 !strconcat(OpcStr, " $rd, [$addr]"), 403 [(OpNode Ty:$rd, ADDRrr:$addr)], 404 itin>; 405 def ri : F3_2<3, Op3Val, 406 (outs), (ins MEMri:$addr, RC:$rd), 407 !strconcat(OpcStr, " $rd, [$addr]"), 408 [(OpNode Ty:$rd, ADDRri:$addr)], 409 itin>; 410} 411 412// TODO: Instructions of the StoreASI class are currently asm only; hooking up 413// CodeGen's address spaces to use these is a future task. 414class StoreASI<string OpcStr, bits<6> Op3Val, 415 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, 416 InstrItinClass itin = IIC_st> : 417 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi), 418 !strconcat(OpcStr, "a $rd, [$addr] $asi"), 419 [], 420 itin>; 421 422multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val, 423 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty, 424 InstrItinClass itin = IIC_st> : 425 Store<OpcStr, Op3Val, OpNode, RC, Ty> { 426 def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>; 427} 428 429//===----------------------------------------------------------------------===// 430// Instructions 431//===----------------------------------------------------------------------===// 432 433// Pseudo instructions. 434class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 435 : InstSP<outs, ins, asmstr, pattern> { 436 let isCodeGenOnly = 1; 437 let isPseudo = 1; 438} 439 440// GETPCX for PIC 441let Defs = [O7] in { 442 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 443} 444 445let Defs = [O6], Uses = [O6] in { 446def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 447 "!ADJCALLSTACKDOWN $amt1, $amt2", 448 [(callseq_start timm:$amt1, timm:$amt2)]>; 449def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 450 "!ADJCALLSTACKUP $amt1", 451 [(callseq_end timm:$amt1, timm:$amt2)]>; 452} 453 454let hasSideEffects = 1, mayStore = 1 in { 455 let rd = 0, rs1 = 0, rs2 = 0 in 456 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 457 "flushw", 458 [(flushw)]>, Requires<[HasV9]>; 459 let rd = 8, rs1 = 0, simm13 = 3 in 460 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 461 "ta 3", 462 [(flushw)]>; 463} 464 465// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 466// instruction selection into a branch sequence. This has to handle all 467// permutations of selection between i32/f32/f64 on ICC and FCC. 468// Expanded after instruction selection. 469let Uses = [ICC], usesCustomInserter = 1 in { 470 def SELECT_CC_Int_ICC 471 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 472 "; SELECT_CC_Int_ICC PSEUDO!", 473 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>; 474 def SELECT_CC_FP_ICC 475 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 476 "; SELECT_CC_FP_ICC PSEUDO!", 477 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>; 478 479 def SELECT_CC_DFP_ICC 480 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 481 "; SELECT_CC_DFP_ICC PSEUDO!", 482 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>; 483 484 def SELECT_CC_QFP_ICC 485 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 486 "; SELECT_CC_QFP_ICC PSEUDO!", 487 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>; 488} 489 490let usesCustomInserter = 1, Uses = [FCC0] in { 491 492 def SELECT_CC_Int_FCC 493 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 494 "; SELECT_CC_Int_FCC PSEUDO!", 495 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>; 496 497 def SELECT_CC_FP_FCC 498 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 499 "; SELECT_CC_FP_FCC PSEUDO!", 500 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>; 501 def SELECT_CC_DFP_FCC 502 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 503 "; SELECT_CC_DFP_FCC PSEUDO!", 504 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>; 505 def SELECT_CC_QFP_FCC 506 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond), 507 "; SELECT_CC_QFP_FCC PSEUDO!", 508 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>; 509} 510 511// Section B.1 - Load Integer Instructions, p. 90 512let DecoderMethod = "DecodeLoadInt" in { 513 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>; 514 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>; 515 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>; 516 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>; 517 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>; 518} 519 520let DecoderMethod = "DecodeLoadIntPair" in 521 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>; 522 523// Section B.2 - Load Floating-point Instructions, p. 92 524let DecoderMethod = "DecodeLoadFP" in { 525 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32, IIC_iu_or_fpu_instr>; 526 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32, IIC_iu_or_fpu_instr>, 527 Requires<[HasV9]>; 528} 529let DecoderMethod = "DecodeLoadDFP" in { 530 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64, IIC_ldd>; 531 def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>, 532 Requires<[HasV9]>; 533} 534let DecoderMethod = "DecodeLoadQFP" in 535 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>, 536 Requires<[HasV9, HasHardQuad]>; 537 538let DecoderMethod = "DecodeLoadCP" in 539 defm LDC : Load<"ld", 0b110000, load, CoprocRegs, i32>; 540let DecoderMethod = "DecodeLoadCPPair" in 541 defm LDDC : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>; 542 543let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in { 544 let rd = 0 in { 545 def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr), 546 "ld [$addr], %csr", []>; 547 def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr), 548 "ld [$addr], %csr", []>; 549 } 550} 551 552let DecoderMethod = "DecodeLoadFP" in 553 let Defs = [FSR] in { 554 let rd = 0 in { 555 def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), 556 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; 557 def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), 558 "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>; 559 } 560 let rd = 1 in { 561 def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr), 562 "ldx [$addr], %fsr", []>, Requires<[HasV9]>; 563 def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr), 564 "ldx [$addr], %fsr", []>, Requires<[HasV9]>; 565 } 566 } 567 568// Section B.4 - Store Integer Instructions, p. 95 569let DecoderMethod = "DecodeStoreInt" in { 570 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>; 571 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>; 572 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>; 573} 574 575let DecoderMethod = "DecodeStoreIntPair" in 576 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>; 577 578// Section B.5 - Store Floating-point Instructions, p. 97 579let DecoderMethod = "DecodeStoreFP" in { 580 defm STF : Store<"st", 0b100100, store, FPRegs, f32>; 581 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>, 582 Requires<[HasV9]>; 583} 584let DecoderMethod = "DecodeStoreDFP" in { 585 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64, IIC_std>; 586 def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>, 587 Requires<[HasV9]>; 588} 589let DecoderMethod = "DecodeStoreQFP" in 590 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>, 591 Requires<[HasV9, HasHardQuad]>; 592 593let DecoderMethod = "DecodeStoreCP" in 594 defm STC : Store<"st", 0b110100, store, CoprocRegs, i32>; 595 596let DecoderMethod = "DecodeStoreCPPair" in 597 defm STDC : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>; 598 599let DecoderMethod = "DecodeStoreCP", rd = 0 in { 600 let Defs = [CPSR] in { 601 def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins), 602 "st %csr, [$addr]", [], IIC_st>; 603 def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins), 604 "st %csr, [$addr]", [], IIC_st>; 605 } 606 let Defs = [CPQ] in { 607 def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins), 608 "std %cq, [$addr]", [], IIC_std>; 609 def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins), 610 "std %cq, [$addr]", [], IIC_std>; 611 } 612} 613 614let DecoderMethod = "DecodeStoreFP" in { 615 let rd = 0 in { 616 let Defs = [FSR] in { 617 def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), 618 "st %fsr, [$addr]", [], IIC_st>; 619 def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), 620 "st %fsr, [$addr]", [], IIC_st>; 621 } 622 let Defs = [FQ] in { 623 def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins), 624 "std %fq, [$addr]", [], IIC_std>; 625 def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins), 626 "std %fq, [$addr]", [], IIC_std>; 627 } 628 } 629 let rd = 1, Defs = [FSR] in { 630 def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins), 631 "stx %fsr, [$addr]", []>, Requires<[HasV9]>; 632 def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins), 633 "stx %fsr, [$addr]", []>, Requires<[HasV9]>; 634 } 635} 636 637// Section B.8 - SWAP Register with Memory Instruction 638// (Atomic swap) 639let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in { 640 def SWAPrr : F3_1<3, 0b001111, 641 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val), 642 "swap [$addr], $dst", 643 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>; 644 def SWAPri : F3_2<3, 0b001111, 645 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val), 646 "swap [$addr], $dst", 647 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>; 648 def SWAPArr : F3_1_asi<3, 0b011111, 649 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val), 650 "swapa [$addr] $asi, $dst", 651 [/*FIXME: pattern?*/]>; 652} 653 654 655// Section B.9 - SETHI Instruction, p. 104 656def SETHIi: F2_1<0b100, 657 (outs IntRegs:$rd), (ins i32imm:$imm22), 658 "sethi $imm22, $rd", 659 [(set i32:$rd, SETHIimm:$imm22)], 660 IIC_iu_instr>; 661 662// Section B.10 - NOP Instruction, p. 105 663// (It's a special case of SETHI) 664let rd = 0, imm22 = 0 in 665 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 666 667// Section B.11 - Logical Instructions, p. 106 668defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>; 669 670def ANDNrr : F3_1<2, 0b000101, 671 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 672 "andn $rs1, $rs2, $rd", 673 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>; 674def ANDNri : F3_2<2, 0b000101, 675 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 676 "andn $rs1, $simm13, $rd", []>; 677 678defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>; 679 680def ORNrr : F3_1<2, 0b000110, 681 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 682 "orn $rs1, $rs2, $rd", 683 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>; 684def ORNri : F3_2<2, 0b000110, 685 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 686 "orn $rs1, $simm13, $rd", []>; 687defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>; 688 689def XNORrr : F3_1<2, 0b000111, 690 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 691 "xnor $rs1, $rs2, $rd", 692 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>; 693def XNORri : F3_2<2, 0b000111, 694 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 695 "xnor $rs1, $simm13, $rd", []>; 696 697def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2), 698 (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>; 699 700def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2), 701 (ORNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>; 702 703let Defs = [ICC] in { 704 defm ANDCC : F3_12np<"andcc", 0b010001>; 705 defm ANDNCC : F3_12np<"andncc", 0b010101>; 706 defm ORCC : F3_12np<"orcc", 0b010010>; 707 defm ORNCC : F3_12np<"orncc", 0b010110>; 708 defm XORCC : F3_12np<"xorcc", 0b010011>; 709 defm XNORCC : F3_12np<"xnorcc", 0b010111>; 710} 711 712// Section B.12 - Shift Instructions, p. 107 713defm SLL : F3_S<"sll", 0b100101, 0, shl, i32, shift_imm5, IntRegs>; 714defm SRL : F3_S<"srl", 0b100110, 0, srl, i32, shift_imm5, IntRegs>; 715defm SRA : F3_S<"sra", 0b100111, 0, sra, i32, shift_imm5, IntRegs>; 716 717// Section B.13 - Add Instructions, p. 108 718defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>; 719 720// "LEA" forms of add (patterns to make tblgen happy) 721let Predicates = [Is32Bit], isCodeGenOnly = 1 in 722 def LEA_ADDri : F3_2<2, 0b000000, 723 (outs IntRegs:$dst), (ins MEMri:$addr), 724 "add ${addr:arith}, $dst", 725 [(set iPTR:$dst, ADDRri:$addr)]>; 726 727let Defs = [ICC] in 728 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>; 729 730let Uses = [ICC] in 731 defm ADDC : F3_12np<"addx", 0b001000>; 732 733let Uses = [ICC], Defs = [ICC] in 734 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>; 735 736// Section B.15 - Subtract Instructions, p. 110 737defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>; 738let Uses = [ICC], Defs = [ICC] in 739 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>; 740 741let Defs = [ICC] in 742 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>; 743 744let Uses = [ICC] in 745 defm SUBC : F3_12np <"subx", 0b001100>; 746 747// cmp (from Section A.3) is a specialized alias for subcc 748let Defs = [ICC], rd = 0 in { 749 def CMPrr : F3_1<2, 0b010100, 750 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 751 "cmp $rs1, $rs2", 752 [(SPcmpicc i32:$rs1, i32:$rs2)]>; 753 def CMPri : F3_2<2, 0b010100, 754 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 755 "cmp $rs1, $simm13", 756 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>; 757} 758 759// Section B.18 - Multiply Instructions, p. 113 760let Defs = [Y] in { 761 defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>; 762 defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>; 763} 764 765let Defs = [Y, ICC] in { 766 defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>; 767 defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>; 768} 769 770let Defs = [Y, ICC], Uses = [Y, ICC] in { 771 defm MULSCC : F3_12np<"mulscc", 0b100100>; 772} 773 774// Section B.19 - Divide Instructions, p. 115 775let Uses = [Y], Defs = [Y] in { 776 defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>; 777 defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>; 778} 779 780let Uses = [Y], Defs = [Y, ICC] in { 781 defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>; 782 defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>; 783} 784 785// Section B.20 - SAVE and RESTORE, p. 117 786defm SAVE : F3_12np<"save" , 0b111100>; 787defm RESTORE : F3_12np<"restore", 0b111101>; 788 789// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 790 791// unconditional branch class. 792class BranchAlways<dag ins, string asmstr, list<dag> pattern> 793 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> { 794 let isBranch = 1; 795 let isTerminator = 1; 796 let hasDelaySlot = 1; 797 let isBarrier = 1; 798} 799 800let cond = 8 in 801 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>; 802 803 804let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 805 806// conditional branch class: 807class BranchSP<dag ins, string asmstr, list<dag> pattern> 808 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>; 809 810// conditional branch with annul class: 811class BranchSPA<dag ins, string asmstr, list<dag> pattern> 812 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>; 813 814// Conditional branch class on %icc|%xcc with predication: 815multiclass IPredBranch<string regstr, list<dag> CCPattern> { 816 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), 817 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")), 818 CCPattern, 819 IIC_iu_instr>; 820 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond), 821 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")), 822 [], 823 IIC_iu_instr>; 824 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), 825 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")), 826 [], 827 IIC_iu_instr>; 828 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond), 829 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")), 830 [], 831 IIC_iu_instr>; 832} 833 834} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 835 836 837// Indirect branch instructions. 838let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1, 839 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in { 840 def BINDrr : F3_1<2, 0b111000, 841 (outs), (ins MEMrr:$ptr), 842 "jmp $ptr", 843 [(brind ADDRrr:$ptr)]>; 844 def BINDri : F3_2<2, 0b111000, 845 (outs), (ins MEMri:$ptr), 846 "jmp $ptr", 847 [(brind ADDRri:$ptr)]>; 848} 849 850let Uses = [ICC] in { 851 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond), 852 "b$cond $imm22", 853 [(SPbricc bb:$imm22, imm:$cond)]>; 854 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond), 855 "b$cond,a $imm22", []>; 856 857 let Predicates = [HasV9], cc = 0b00 in 858 defm BPI : IPredBranch<"%icc", []>; 859} 860 861// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 862 863let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 864 865// floating-point conditional branch class: 866class FPBranchSP<dag ins, string asmstr, list<dag> pattern> 867 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; 868 869// floating-point conditional branch with annul class: 870class FPBranchSPA<dag ins, string asmstr, list<dag> pattern> 871 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>; 872 873// Conditional branch class on %fcc0-%fcc3 with predication: 874multiclass FPredBranch { 875 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, 876 FCCRegs:$cc), 877 "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>; 878 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond, 879 FCCRegs:$cc), 880 "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>; 881 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, 882 FCCRegs:$cc), 883 "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>; 884 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond, 885 FCCRegs:$cc), 886 "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>; 887} 888} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 889 890let Uses = [FCC0] in { 891 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 892 "fb$cond $imm22", 893 [(SPbrfcc bb:$imm22, imm:$cond)]>; 894 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), 895 "fb$cond,a $imm22", []>; 896} 897 898let Predicates = [HasV9] in 899 defm BPF : FPredBranch; 900 901// Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123 902let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in { 903 904// co-processor conditional branch class: 905class CPBranchSP<dag ins, string asmstr, list<dag> pattern> 906 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>; 907 908// co-processor conditional branch with annul class: 909class CPBranchSPA<dag ins, string asmstr, list<dag> pattern> 910 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>; 911 912} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 913 914def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond), 915 "cb$cond $imm22", 916 [(SPbrfcc bb:$imm22, imm:$cond)]>; 917def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond), 918 "cb$cond,a $imm22", []>; 919 920// Section B.24 - Call and Link Instruction, p. 125 921// This is the only Format 1 instruction 922let Uses = [O6], 923 hasDelaySlot = 1, isCall = 1 in { 924 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops), 925 "call $disp", 926 [], 927 IIC_jmp_or_call> { 928 bits<30> disp; 929 let op = 1; 930 let Inst{29-0} = disp; 931 } 932 933 // indirect calls: special cases of JMPL. 934 let isCodeGenOnly = 1, rd = 15 in { 935 def CALLrr : F3_1<2, 0b111000, 936 (outs), (ins MEMrr:$ptr, variable_ops), 937 "call $ptr", 938 [(call ADDRrr:$ptr)], 939 IIC_jmp_or_call>; 940 def CALLri : F3_2<2, 0b111000, 941 (outs), (ins MEMri:$ptr, variable_ops), 942 "call $ptr", 943 [(call ADDRri:$ptr)], 944 IIC_jmp_or_call>; 945 } 946} 947 948// Section B.25 - Jump and Link Instruction 949 950// JMPL Instruction. 951let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 952 DecoderMethod = "DecodeJMPL" in { 953 def JMPLrr: F3_1<2, 0b111000, 954 (outs IntRegs:$dst), (ins MEMrr:$addr), 955 "jmpl $addr, $dst", 956 [], 957 IIC_jmp_or_call>; 958 def JMPLri: F3_2<2, 0b111000, 959 (outs IntRegs:$dst), (ins MEMri:$addr), 960 "jmpl $addr, $dst", 961 [], 962 IIC_jmp_or_call>; 963} 964 965// Section A.3 - Synthetic Instructions, p. 85 966// special cases of JMPL: 967let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1, 968 isCodeGenOnly = 1 in { 969 let rd = 0, rs1 = 15 in 970 def RETL: F3_2<2, 0b111000, 971 (outs), (ins i32imm:$val), 972 "jmp %o7+$val", 973 [(retflag simm13:$val)], 974 IIC_jmp_or_call>; 975 976 let rd = 0, rs1 = 31 in 977 def RET: F3_2<2, 0b111000, 978 (outs), (ins i32imm:$val), 979 "jmp %i7+$val", 980 [], 981 IIC_jmp_or_call>; 982} 983 984// Section B.26 - Return from Trap Instruction 985let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, 986 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in { 987 def RETTrr : F3_1<2, 0b111001, 988 (outs), (ins MEMrr:$addr), 989 "rett $addr", 990 [], 991 IIC_jmp_or_call>; 992 def RETTri : F3_2<2, 0b111001, 993 (outs), (ins MEMri:$addr), 994 "rett $addr", 995 [], 996 IIC_jmp_or_call>; 997} 998 999 1000// Section B.27 - Trap on Integer Condition Codes Instruction 1001// conditional branch class: 1002let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in 1003{ 1004 def TRAPrr : TRAPSPrr<0b111010, 1005 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), 1006 "t$cond $rs1 + $rs2", 1007 []>; 1008 def TRAPri : TRAPSPri<0b111010, 1009 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), 1010 "t$cond $rs1 + $imm", 1011 []>; 1012} 1013 1014multiclass TRAP<string regStr> { 1015 def rr : TRAPSPrr<0b111010, 1016 (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond), 1017 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), 1018 []>; 1019 def ri : TRAPSPri<0b111010, 1020 (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond), 1021 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), 1022 []>; 1023} 1024 1025let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in 1026 defm TICC : TRAP<"%icc">; 1027 1028 1029let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in 1030 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; 1031 1032let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in 1033 def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>; 1034 1035// Section B.28 - Read State Register Instructions 1036let rs2 = 0 in 1037 def RDASR : F3_1<2, 0b101000, 1038 (outs IntRegs:$rd), (ins ASRRegs:$rs1), 1039 "rd $rs1, $rd", []>; 1040 1041// PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 1042let Predicates = [HasNoV9] in { 1043 let rs2 = 0, rs1 = 0, Uses=[PSR] in 1044 def RDPSR : F3_1<2, 0b101001, 1045 (outs IntRegs:$rd), (ins), 1046 "rd %psr, $rd", []>; 1047 1048 let rs2 = 0, rs1 = 0, Uses=[WIM] in 1049 def RDWIM : F3_1<2, 0b101010, 1050 (outs IntRegs:$rd), (ins), 1051 "rd %wim, $rd", []>; 1052 1053 let rs2 = 0, rs1 = 0, Uses=[TBR] in 1054 def RDTBR : F3_1<2, 0b101011, 1055 (outs IntRegs:$rd), (ins), 1056 "rd %tbr, $rd", []>; 1057} 1058 1059// PC don't exist on the SparcV8, only the V9. 1060let Predicates = [HasV9] in { 1061 let rs2 = 0, rs1 = 5 in 1062 def RDPC : F3_1<2, 0b101000, 1063 (outs IntRegs:$rd), (ins), 1064 "rd %pc, $rd", []>; 1065} 1066 1067// Section B.29 - Write State Register Instructions 1068def WRASRrr : F3_1<2, 0b110000, 1069 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 1070 "wr $rs1, $rs2, $rd", []>; 1071def WRASRri : F3_2<2, 0b110000, 1072 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 1073 "wr $rs1, $simm13, $rd", []>; 1074 1075// PSR, WIM, and TBR don't exist on the SparcV9, only the V8. 1076let Predicates = [HasNoV9] in { 1077 let Defs = [PSR], rd=0 in { 1078 def WRPSRrr : F3_1<2, 0b110001, 1079 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1080 "wr $rs1, $rs2, %psr", []>; 1081 def WRPSRri : F3_2<2, 0b110001, 1082 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1083 "wr $rs1, $simm13, %psr", []>; 1084 } 1085 1086 let Defs = [WIM], rd=0 in { 1087 def WRWIMrr : F3_1<2, 0b110010, 1088 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1089 "wr $rs1, $rs2, %wim", []>; 1090 def WRWIMri : F3_2<2, 0b110010, 1091 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1092 "wr $rs1, $simm13, %wim", []>; 1093 } 1094 1095 let Defs = [TBR], rd=0 in { 1096 def WRTBRrr : F3_1<2, 0b110011, 1097 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1098 "wr $rs1, $rs2, %tbr", []>; 1099 def WRTBRri : F3_2<2, 0b110011, 1100 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1101 "wr $rs1, $simm13, %tbr", []>; 1102 } 1103} 1104 1105// Section B.30 - STBAR Instruction 1106let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in 1107 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>; 1108 1109 1110// Section B.31 - Unimplemented Instruction 1111let rd = 0 in 1112 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22), 1113 "unimp $imm22", []>; 1114 1115// Section B.32 - Flush Instruction Memory 1116let rd = 0 in { 1117 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr), 1118 "flush $addr", []>; 1119 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr), 1120 "flush $addr", []>; 1121 1122 // The no-arg FLUSH is only here for the benefit of the InstAlias 1123 // "flush", which cannot seem to use FLUSHrr, due to the inability 1124 // to construct a MEMrr with fixed G0 registers. 1125 let rs1 = 0, rs2 = 0 in 1126 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>; 1127} 1128 1129// Section B.33 - Floating-point Operate (FPop) Instructions 1130 1131// Convert Integer to Floating-point Instructions, p. 141 1132def FITOS : F3_3u<2, 0b110100, 0b011000100, 1133 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1134 "fitos $rs2, $rd", 1135 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))], 1136 IIC_fpu_fast_instr>; 1137def FITOD : F3_3u<2, 0b110100, 0b011001000, 1138 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 1139 "fitod $rs2, $rd", 1140 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))], 1141 IIC_fpu_fast_instr>; 1142def FITOQ : F3_3u<2, 0b110100, 0b011001100, 1143 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 1144 "fitoq $rs2, $rd", 1145 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>, 1146 Requires<[HasHardQuad]>; 1147 1148// Convert Floating-point to Integer Instructions, p. 142 1149def FSTOI : F3_3u<2, 0b110100, 0b011010001, 1150 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1151 "fstoi $rs2, $rd", 1152 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))], 1153 IIC_fpu_fast_instr>; 1154def FDTOI : F3_3u<2, 0b110100, 0b011010010, 1155 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 1156 "fdtoi $rs2, $rd", 1157 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))], 1158 IIC_fpu_fast_instr>; 1159def FQTOI : F3_3u<2, 0b110100, 0b011010011, 1160 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 1161 "fqtoi $rs2, $rd", 1162 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>, 1163 Requires<[HasHardQuad]>; 1164 1165// Convert between Floating-point Formats Instructions, p. 143 1166def FSTOD : F3_3u<2, 0b110100, 0b011001001, 1167 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 1168 "fstod $rs2, $rd", 1169 [(set f64:$rd, (fpextend f32:$rs2))], 1170 IIC_fpu_stod>; 1171def FSTOQ : F3_3u<2, 0b110100, 0b011001101, 1172 (outs QFPRegs:$rd), (ins FPRegs:$rs2), 1173 "fstoq $rs2, $rd", 1174 [(set f128:$rd, (fpextend f32:$rs2))]>, 1175 Requires<[HasHardQuad]>; 1176def FDTOS : F3_3u<2, 0b110100, 0b011000110, 1177 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 1178 "fdtos $rs2, $rd", 1179 [(set f32:$rd, (fpround f64:$rs2))], 1180 IIC_fpu_fast_instr>; 1181def FDTOQ : F3_3u<2, 0b110100, 0b011001110, 1182 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 1183 "fdtoq $rs2, $rd", 1184 [(set f128:$rd, (fpextend f64:$rs2))]>, 1185 Requires<[HasHardQuad]>; 1186def FQTOS : F3_3u<2, 0b110100, 0b011000111, 1187 (outs FPRegs:$rd), (ins QFPRegs:$rs2), 1188 "fqtos $rs2, $rd", 1189 [(set f32:$rd, (fpround f128:$rs2))]>, 1190 Requires<[HasHardQuad]>; 1191def FQTOD : F3_3u<2, 0b110100, 0b011001011, 1192 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 1193 "fqtod $rs2, $rd", 1194 [(set f64:$rd, (fpround f128:$rs2))]>, 1195 Requires<[HasHardQuad]>; 1196 1197// Floating-point Move Instructions, p. 144 1198def FMOVS : F3_3u<2, 0b110100, 0b000000001, 1199 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1200 "fmovs $rs2, $rd", []>; 1201def FNEGS : F3_3u<2, 0b110100, 0b000000101, 1202 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1203 "fnegs $rs2, $rd", 1204 [(set f32:$rd, (fneg f32:$rs2))], 1205 IIC_fpu_negs>; 1206def FABSS : F3_3u<2, 0b110100, 0b000001001, 1207 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1208 "fabss $rs2, $rd", 1209 [(set f32:$rd, (fabs f32:$rs2))], 1210 IIC_fpu_abs>; 1211 1212 1213// Floating-point Square Root Instructions, p.145 1214// FSQRTS generates an erratum on LEON processors, so by disabling this instruction 1215// this will be promoted to use FSQRTD with doubles instead. 1216let Predicates = [HasNoFdivSqrtFix] in 1217def FSQRTS : F3_3u<2, 0b110100, 0b000101001, 1218 (outs FPRegs:$rd), (ins FPRegs:$rs2), 1219 "fsqrts $rs2, $rd", 1220 [(set f32:$rd, (fsqrt f32:$rs2))], 1221 IIC_fpu_sqrts>; 1222def FSQRTD : F3_3u<2, 0b110100, 0b000101010, 1223 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1224 "fsqrtd $rs2, $rd", 1225 [(set f64:$rd, (fsqrt f64:$rs2))], 1226 IIC_fpu_sqrtd>; 1227def FSQRTQ : F3_3u<2, 0b110100, 0b000101011, 1228 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1229 "fsqrtq $rs2, $rd", 1230 [(set f128:$rd, (fsqrt f128:$rs2))]>, 1231 Requires<[HasHardQuad]>; 1232 1233 1234 1235// Floating-point Add and Subtract Instructions, p. 146 1236def FADDS : F3_3<2, 0b110100, 0b001000001, 1237 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1238 "fadds $rs1, $rs2, $rd", 1239 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))], 1240 IIC_fpu_fast_instr>; 1241def FADDD : F3_3<2, 0b110100, 0b001000010, 1242 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1243 "faddd $rs1, $rs2, $rd", 1244 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))], 1245 IIC_fpu_fast_instr>; 1246def FADDQ : F3_3<2, 0b110100, 0b001000011, 1247 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1248 "faddq $rs1, $rs2, $rd", 1249 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>, 1250 Requires<[HasHardQuad]>; 1251 1252def FSUBS : F3_3<2, 0b110100, 0b001000101, 1253 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1254 "fsubs $rs1, $rs2, $rd", 1255 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))], 1256 IIC_fpu_fast_instr>; 1257def FSUBD : F3_3<2, 0b110100, 0b001000110, 1258 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1259 "fsubd $rs1, $rs2, $rd", 1260 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))], 1261 IIC_fpu_fast_instr>; 1262def FSUBQ : F3_3<2, 0b110100, 0b001000111, 1263 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1264 "fsubq $rs1, $rs2, $rd", 1265 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>, 1266 Requires<[HasHardQuad]>; 1267 1268 1269// Floating-point Multiply and Divide Instructions, p. 147 1270def FMULS : F3_3<2, 0b110100, 0b001001001, 1271 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1272 "fmuls $rs1, $rs2, $rd", 1273 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))], 1274 IIC_fpu_muls>, 1275 Requires<[HasFMULS]>; 1276def FMULD : F3_3<2, 0b110100, 0b001001010, 1277 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1278 "fmuld $rs1, $rs2, $rd", 1279 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))], 1280 IIC_fpu_muld>; 1281def FMULQ : F3_3<2, 0b110100, 0b001001011, 1282 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1283 "fmulq $rs1, $rs2, $rd", 1284 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>, 1285 Requires<[HasHardQuad]>; 1286 1287def FSMULD : F3_3<2, 0b110100, 0b001101001, 1288 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1289 "fsmuld $rs1, $rs2, $rd", 1290 [(set f64:$rd, (fmul (fpextend f32:$rs1), 1291 (fpextend f32:$rs2)))], 1292 IIC_fpu_muld>, 1293 Requires<[HasFSMULD]>; 1294def FDMULQ : F3_3<2, 0b110100, 0b001101110, 1295 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1296 "fdmulq $rs1, $rs2, $rd", 1297 [(set f128:$rd, (fmul (fpextend f64:$rs1), 1298 (fpextend f64:$rs2)))]>, 1299 Requires<[HasHardQuad]>; 1300 1301// FDIVS generates an erratum on LEON processors, so by disabling this instruction 1302// this will be promoted to use FDIVD with doubles instead. 1303def FDIVS : F3_3<2, 0b110100, 0b001001101, 1304 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1305 "fdivs $rs1, $rs2, $rd", 1306 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))], 1307 IIC_fpu_divs>; 1308def FDIVD : F3_3<2, 0b110100, 0b001001110, 1309 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1310 "fdivd $rs1, $rs2, $rd", 1311 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))], 1312 IIC_fpu_divd>; 1313def FDIVQ : F3_3<2, 0b110100, 0b001001111, 1314 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1315 "fdivq $rs1, $rs2, $rd", 1316 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>, 1317 Requires<[HasHardQuad]>; 1318 1319// Floating-point Compare Instructions, p. 148 1320// Note: the 2nd template arg is different for these guys. 1321// Note 2: the result of a FCMP is not available until the 2nd cycle 1322// after the instr is retired, but there is no interlock in Sparc V8. 1323// This behavior is modeled with a forced noop after the instruction in 1324// DelaySlotFiller. 1325 1326let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in { 1327 def FCMPS : F3_3c<2, 0b110101, 0b001010001, 1328 (outs), (ins FPRegs:$rs1, FPRegs:$rs2), 1329 "fcmps $rs1, $rs2", 1330 [(SPcmpfcc f32:$rs1, f32:$rs2)], 1331 IIC_fpu_fast_instr>; 1332 def FCMPD : F3_3c<2, 0b110101, 0b001010010, 1333 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1334 "fcmpd $rs1, $rs2", 1335 [(SPcmpfcc f64:$rs1, f64:$rs2)], 1336 IIC_fpu_fast_instr>; 1337 def FCMPQ : F3_3c<2, 0b110101, 0b001010011, 1338 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1339 "fcmpq $rs1, $rs2", 1340 [(SPcmpfcc f128:$rs1, f128:$rs2)]>, 1341 Requires<[HasHardQuad]>; 1342} 1343 1344//===----------------------------------------------------------------------===// 1345// Instructions for Thread Local Storage(TLS). 1346//===----------------------------------------------------------------------===// 1347let isAsmParserOnly = 1 in { 1348def TLS_ADDrr : F3_1<2, 0b000000, 1349 (outs IntRegs:$rd), 1350 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym), 1351 "add $rs1, $rs2, $rd, $sym", 1352 [(set i32:$rd, 1353 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>; 1354 1355let mayLoad = 1 in 1356 def TLS_LDrr : F3_1<3, 0b000000, 1357 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym), 1358 "ld [$addr], $dst, $sym", 1359 [(set i32:$dst, 1360 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 1361 1362let Uses = [O6], isCall = 1, hasDelaySlot = 1 in 1363 def TLS_CALL : InstSP<(outs), 1364 (ins calltarget:$disp, TLSSym:$sym, variable_ops), 1365 "call $disp, $sym", 1366 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)], 1367 IIC_jmp_or_call> { 1368 bits<30> disp; 1369 let op = 1; 1370 let Inst{29-0} = disp; 1371} 1372} 1373 1374//===----------------------------------------------------------------------===// 1375// V9 Instructions 1376//===----------------------------------------------------------------------===// 1377 1378// V9 Conditional Moves. 1379let Predicates = [HasV9], Constraints = "$f = $rd" in { 1380 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 1381 let Uses = [ICC], intcc = 1, cc = 0b00 in { 1382 def MOVICCrr 1383 : F4_1<0b101100, (outs IntRegs:$rd), 1384 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1385 "mov$cond %icc, $rs2, $rd", 1386 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>; 1387 1388 def MOVICCri 1389 : F4_2<0b101100, (outs IntRegs:$rd), 1390 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1391 "mov$cond %icc, $simm11, $rd", 1392 [(set i32:$rd, 1393 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>; 1394 } 1395 1396 let Uses = [FCC0], intcc = 0, cc = 0b00 in { 1397 def MOVFCCrr 1398 : F4_1<0b101100, (outs IntRegs:$rd), 1399 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1400 "mov$cond %fcc0, $rs2, $rd", 1401 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>; 1402 def MOVFCCri 1403 : F4_2<0b101100, (outs IntRegs:$rd), 1404 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1405 "mov$cond %fcc0, $simm11, $rd", 1406 [(set i32:$rd, 1407 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>; 1408 } 1409 1410 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in { 1411 def FMOVS_ICC 1412 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1413 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1414 "fmovs$cond %icc, $rs2, $rd", 1415 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>; 1416 def FMOVD_ICC 1417 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1418 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1419 "fmovd$cond %icc, $rs2, $rd", 1420 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>; 1421 def FMOVQ_ICC 1422 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1423 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1424 "fmovq$cond %icc, $rs2, $rd", 1425 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>, 1426 Requires<[HasHardQuad]>; 1427 } 1428 1429 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in { 1430 def FMOVS_FCC 1431 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1432 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1433 "fmovs$cond %fcc0, $rs2, $rd", 1434 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>; 1435 def FMOVD_FCC 1436 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1437 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1438 "fmovd$cond %fcc0, $rs2, $rd", 1439 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>; 1440 def FMOVQ_FCC 1441 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1442 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1443 "fmovq$cond %fcc0, $rs2, $rd", 1444 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>, 1445 Requires<[HasHardQuad]>; 1446 } 1447 1448} 1449 1450// Floating-Point Move Instructions, p. 164 of the V9 manual. 1451let Predicates = [HasV9] in { 1452 def FMOVD : F3_3u<2, 0b110100, 0b000000010, 1453 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1454 "fmovd $rs2, $rd", []>; 1455 def FMOVQ : F3_3u<2, 0b110100, 0b000000011, 1456 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1457 "fmovq $rs2, $rd", []>, 1458 Requires<[HasHardQuad]>; 1459 def FNEGD : F3_3u<2, 0b110100, 0b000000110, 1460 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1461 "fnegd $rs2, $rd", 1462 [(set f64:$rd, (fneg f64:$rs2))]>; 1463 def FNEGQ : F3_3u<2, 0b110100, 0b000000111, 1464 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1465 "fnegq $rs2, $rd", 1466 [(set f128:$rd, (fneg f128:$rs2))]>, 1467 Requires<[HasHardQuad]>; 1468 def FABSD : F3_3u<2, 0b110100, 0b000001010, 1469 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 1470 "fabsd $rs2, $rd", 1471 [(set f64:$rd, (fabs f64:$rs2))]>; 1472 def FABSQ : F3_3u<2, 0b110100, 0b000001011, 1473 (outs QFPRegs:$rd), (ins QFPRegs:$rs2), 1474 "fabsq $rs2, $rd", 1475 [(set f128:$rd, (fabs f128:$rs2))]>, 1476 Requires<[HasHardQuad]>; 1477} 1478 1479// Floating-point compare instruction with %fcc0-%fcc3. 1480def V9FCMPS : F3_3c<2, 0b110101, 0b001010001, 1481 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1482 "fcmps $rd, $rs1, $rs2", []>; 1483def V9FCMPD : F3_3c<2, 0b110101, 0b001010010, 1484 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1485 "fcmpd $rd, $rs1, $rs2", []>; 1486def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011, 1487 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1488 "fcmpq $rd, $rs1, $rs2", []>, 1489 Requires<[HasHardQuad]>; 1490 1491let hasSideEffects = 1 in { 1492 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101, 1493 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), 1494 "fcmpes $rd, $rs1, $rs2", []>; 1495 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110, 1496 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), 1497 "fcmped $rd, $rs1, $rs2", []>; 1498 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111, 1499 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2), 1500 "fcmpeq $rd, $rs1, $rs2", []>, 1501 Requires<[HasHardQuad]>; 1502} 1503 1504// Floating point conditional move instrucitons with %fcc0-%fcc3. 1505let Predicates = [HasV9] in { 1506 let Constraints = "$f = $rd", intcc = 0 in { 1507 def V9MOVFCCrr 1508 : F4_1<0b101100, (outs IntRegs:$rd), 1509 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 1510 "mov$cond $cc, $rs2, $rd", []>; 1511 def V9MOVFCCri 1512 : F4_2<0b101100, (outs IntRegs:$rd), 1513 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond), 1514 "mov$cond $cc, $simm11, $rd", []>; 1515 def V9FMOVS_FCC 1516 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 1517 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 1518 "fmovs$cond $opf_cc, $rs2, $rd", []>; 1519 def V9FMOVD_FCC 1520 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 1521 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 1522 "fmovd$cond $opf_cc, $rs2, $rd", []>; 1523 def V9FMOVQ_FCC 1524 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 1525 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 1526 "fmovq$cond $opf_cc, $rs2, $rd", []>, 1527 Requires<[HasHardQuad]>; 1528 } // Constraints = "$f = $rd", ... 1529} // let Predicates = [hasV9] 1530 1531 1532// POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 1533// the top 32-bits before using it. To do this clearing, we use a SRLri X,0. 1534let rs1 = 0 in 1535 def POPCrr : F3_1<2, 0b101110, 1536 (outs IntRegs:$rd), (ins IntRegs:$rs2), 1537 "popc $rs2, $rd", []>, Requires<[HasV9]>; 1538def : Pat<(i32 (ctpop i32:$src)), 1539 (POPCrr (SRLri $src, 0))>; 1540 1541let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in 1542 def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13), 1543 "membar $simm13", []>; 1544 1545let Predicates = [HasV9], rd = 15, rs1 = 0b00000 in 1546 def SIR: F3_2<2, 0b110000, (outs), 1547 (ins simm13Op:$simm13), 1548 "sir $simm13", []>; 1549 1550// The CAS instruction, unlike other instructions, only comes in a 1551// form which requires an ASI be provided. The ASI value hardcoded 1552// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9. 1553let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in 1554 def CASrr: F3_1_asi<3, 0b111100, 1555 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1556 IntRegs:$swap), 1557 "cas [$rs1], $rs2, $rd", 1558 [(set i32:$rd, 1559 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; 1560 1561 1562// CASA is supported as an instruction on some LEON3 and all LEON4 processors. 1563// This version can be automatically lowered from C code, selecting ASI 10 1564let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in 1565 def CASAasi10: F3_1_asi<3, 0b111100, 1566 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1567 IntRegs:$swap), 1568 "casa [$rs1] 10, $rs2, $rd", 1569 [(set i32:$rd, 1570 (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>; 1571 1572// CASA supported on some LEON3 and all LEON4 processors. Same pattern as 1573// CASrr, above, but with a different ASI. This version is supported for 1574// inline assembly lowering only. 1575let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in 1576 def CASArr: F3_1_asi<3, 0b111100, 1577 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, 1578 IntRegs:$swap, i8imm:$asi), 1579 "casa [$rs1] $asi, $rs2, $rd", []>; 1580 1581// TODO: Add DAG sequence to lower these instructions. Currently, only provided 1582// as inline assembler-supported instructions. 1583let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in { 1584 def SMACrr : F3_1<2, 0b111111, 1585 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), 1586 "smac $rs1, $rs2, $rd", 1587 [], IIC_smac_umac>; 1588 1589 def SMACri : F3_2<2, 0b111111, 1590 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), 1591 "smac $rs1, $simm13, $rd", 1592 [], IIC_smac_umac>; 1593 1594 def UMACrr : F3_1<2, 0b111110, 1595 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18), 1596 "umac $rs1, $rs2, $rd", 1597 [], IIC_smac_umac>; 1598 1599 def UMACri : F3_2<2, 0b111110, 1600 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18), 1601 "umac $rs1, $simm13, $rd", 1602 [], IIC_smac_umac>; 1603} 1604 1605// The partial write WRPSR instruction has a non-zero destination 1606// register value to separate it from the standard instruction. 1607let Predicates = [HasPWRPSR], Defs = [PSR], rd=1 in { 1608 def PWRPSRrr : F3_1<2, 0b110001, 1609 (outs), (ins IntRegs:$rs1, IntRegs:$rs2), 1610 "pwr $rs1, $rs2, %psr", []>; 1611 def PWRPSRri : F3_2<2, 0b110001, 1612 (outs), (ins IntRegs:$rs1, simm13Op:$simm13), 1613 "pwr $rs1, $simm13, %psr", []>; 1614} 1615 1616let Defs = [ICC] in { 1617defm TADDCC : F3_12np<"taddcc", 0b100000>; 1618defm TSUBCC : F3_12np<"tsubcc", 0b100001>; 1619 1620let hasSideEffects = 1 in { 1621 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>; 1622 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>; 1623} 1624} 1625 1626 1627// Section A.43 - Read Privileged Register Instructions 1628let Predicates = [HasV9] in { 1629let rs2 = 0 in 1630 def RDPR : F3_1<2, 0b101010, 1631 (outs IntRegs:$rd), (ins PRRegs:$rs1), 1632 "rdpr $rs1, $rd", []>; 1633} 1634 1635// Section A.62 - Write Privileged Register Instructions 1636let Predicates = [HasV9] in { 1637 def WRPRrr : F3_1<2, 0b110010, 1638 (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2), 1639 "wrpr $rs1, $rs2, $rd", []>; 1640 def WRPRri : F3_2<2, 0b110010, 1641 (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13), 1642 "wrpr $rs1, $simm13, $rd", []>; 1643} 1644 1645//===----------------------------------------------------------------------===// 1646// Non-Instruction Patterns 1647//===----------------------------------------------------------------------===// 1648 1649// Zero immediate. 1650def : Pat<(i32 0), 1651 (ORrr (i32 G0), (i32 G0))>; 1652// Small immediates. 1653def : Pat<(i32 simm13:$val), 1654 (ORri (i32 G0), imm:$val)>; 1655// Arbitrary immediates. 1656def : Pat<(i32 imm:$val), 1657 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 1658 1659 1660// Global addresses, constant pool entries 1661let Predicates = [Is32Bit] in { 1662 1663def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 1664def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>; 1665def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 1666def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>; 1667 1668// GlobalTLS addresses 1669def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 1670def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>; 1671def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 1672 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1673def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 1674 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 1675 1676// Blockaddress 1677def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 1678def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>; 1679 1680// Add reg, lo. This is used when taking the addr of a global/constpool entry. 1681def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 1682def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 1683def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 1684 (ADDri $r, tblockaddress:$in)>; 1685} 1686 1687// Calls: 1688def : Pat<(call tglobaladdr:$dst), 1689 (CALL tglobaladdr:$dst)>; 1690def : Pat<(call texternalsym:$dst), 1691 (CALL texternalsym:$dst)>; 1692 1693// Map integer extload's to zextloads. 1694def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1695def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1696def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1697def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1698def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1699def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1700 1701// zextload bool -> zextload byte 1702def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1703def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1704 1705// store 0, addr -> store %g0, addr 1706def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>; 1707def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>; 1708 1709// store bar for all atomic_fence in V8. 1710let Predicates = [HasNoV9] in 1711 def : Pat<(atomic_fence timm, timm), (STBAR)>; 1712 1713let Predicates = [HasV9] in 1714 def : Pat<(atomic_fence timm, timm), (MEMBARi 0xf)>; 1715 1716// atomic_load addr -> load addr 1717def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 1718def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 1719def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 1720def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 1721def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>; 1722def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>; 1723 1724// atomic_store val, addr -> store val, addr 1725def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>; 1726def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>; 1727def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>; 1728def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>; 1729def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>; 1730def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>; 1731 1732// extract_vector 1733def : Pat<(extractelt (v2i32 IntPair:$Rn), 0), 1734 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>; 1735def : Pat<(extractelt (v2i32 IntPair:$Rn), 1), 1736 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>; 1737 1738// build_vector 1739def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)), 1740 (INSERT_SUBREG 1741 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even), 1742 (i32 IntRegs:$a2), sub_odd)>; 1743 1744 1745include "SparcInstr64Bit.td" 1746include "SparcInstrVIS.td" 1747include "SparcInstrAliases.td" 1748