xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrInfo.td (revision 162ae9c834f6d9f9cb443bd62cceb23e0b5fef48)
1//===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file describes the Sparc instructions in TableGen format.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Instruction format superclass
15//===----------------------------------------------------------------------===//
16
17include "SparcInstrFormats.td"
18
19//===----------------------------------------------------------------------===//
20// Feature predicates.
21//===----------------------------------------------------------------------===//
22
23// True when generating 32-bit code.
24def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
25
26// True when generating 64-bit code. This also implies HasV9.
27def Is64Bit : Predicate<"Subtarget->is64Bit()">;
28
29def UseSoftMulDiv : Predicate<"Subtarget->useSoftMulDiv()">,
30              AssemblerPredicate<"FeatureSoftMulDiv">;
31
32// HasV9 - This predicate is true when the target processor supports V9
33// instructions.  Note that the machine may be running in 32-bit mode.
34def HasV9   : Predicate<"Subtarget->isV9()">,
35              AssemblerPredicate<"FeatureV9">;
36
37// HasNoV9 - This predicate is true when the target doesn't have V9
38// instructions.  Use of this is just a hack for the isel not having proper
39// costs for V8 instructions that are more expensive than their V9 ones.
40def HasNoV9 : Predicate<"!Subtarget->isV9()">;
41
42// HasVIS - This is true when the target processor has VIS extensions.
43def HasVIS : Predicate<"Subtarget->isVIS()">,
44             AssemblerPredicate<"FeatureVIS">;
45def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
46             AssemblerPredicate<"FeatureVIS2">;
47def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
48             AssemblerPredicate<"FeatureVIS3">;
49
50// HasHardQuad - This is true when the target processor supports quad floating
51// point instructions.
52def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
53
54// HasLeonCASA - This is true when the target processor supports the CASA
55// instruction
56def HasLeonCASA : Predicate<"Subtarget->hasLeonCasa()">;
57
58// HasPWRPSR - This is true when the target processor supports partial
59// writes to the PSR register that only affects the ET field.
60def HasPWRPSR : Predicate<"Subtarget->hasPWRPSR()">,
61                AssemblerPredicate<"FeaturePWRPSR">;
62
63// HasUMAC_SMAC - This is true when the target processor supports the
64// UMAC and SMAC instructions
65def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
66
67def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">;
68def HasFMULS : Predicate<"!Subtarget->hasNoFMULS()">;
69def HasFSMULD : Predicate<"!Subtarget->hasNoFSMULD()">;
70
71// UseDeprecatedInsts - This predicate is true when the target processor is a
72// V8, or when it is V9 but the V8 deprecated instructions are efficient enough
73// to use when appropriate.  In either of these cases, the instruction selector
74// will pick deprecated instructions.
75def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
76
77//===----------------------------------------------------------------------===//
78// Instruction Pattern Stuff
79//===----------------------------------------------------------------------===//
80
81def simm11  : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
82
83def simm13  : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
84
85def LO10 : SDNodeXForm<imm, [{
86  return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
87                                   MVT::i32);
88}]>;
89
90def HI22 : SDNodeXForm<imm, [{
91  // Transformation function: shift the immediate value down into the low bits.
92  return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
93                                   MVT::i32);
94}]>;
95
96// Return the complement of a HI22 immediate value.
97def HI22_not : SDNodeXForm<imm, [{
98  return CurDAG->getTargetConstant(~(unsigned)N->getZExtValue() >> 10, SDLoc(N),
99                                   MVT::i32);
100}]>;
101
102def SETHIimm : PatLeaf<(imm), [{
103  return isShiftedUInt<22, 10>(N->getZExtValue());
104}], HI22>;
105
106// The N->hasOneUse() prevents the immediate from being instantiated in both
107// normal and complement form.
108def SETHIimm_not : PatLeaf<(i32 imm), [{
109  return N->hasOneUse() && isShiftedUInt<22, 10>(~(unsigned)N->getZExtValue());
110}], HI22_not>;
111
112// Addressing modes.
113def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
114def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
115
116// Address operands
117def SparcMEMrrAsmOperand : AsmOperandClass {
118  let Name = "MEMrr";
119  let ParserMethod = "parseMEMOperand";
120}
121
122def SparcMEMriAsmOperand : AsmOperandClass {
123  let Name = "MEMri";
124  let ParserMethod = "parseMEMOperand";
125}
126
127def MEMrr : Operand<iPTR> {
128  let PrintMethod = "printMemOperand";
129  let MIOperandInfo = (ops ptr_rc, ptr_rc);
130  let ParserMatchClass = SparcMEMrrAsmOperand;
131}
132def MEMri : Operand<iPTR> {
133  let PrintMethod = "printMemOperand";
134  let MIOperandInfo = (ops ptr_rc, i32imm);
135  let ParserMatchClass = SparcMEMriAsmOperand;
136}
137
138def TLSSym : Operand<iPTR>;
139
140def SparcMembarTagAsmOperand : AsmOperandClass {
141  let Name = "MembarTag";
142  let ParserMethod = "parseMembarTag";
143}
144
145def MembarTag : Operand<i32> {
146  let PrintMethod = "printMembarTag";
147  let ParserMatchClass = SparcMembarTagAsmOperand;
148}
149
150// Branch targets have OtherVT type.
151def brtarget : Operand<OtherVT> {
152  let EncoderMethod = "getBranchTargetOpValue";
153}
154
155def bprtarget : Operand<OtherVT> {
156  let EncoderMethod = "getBranchPredTargetOpValue";
157}
158
159def bprtarget16 : Operand<OtherVT> {
160  let EncoderMethod = "getBranchOnRegTargetOpValue";
161}
162
163def calltarget : Operand<i32> {
164  let EncoderMethod = "getCallTargetOpValue";
165  let DecoderMethod = "DecodeCall";
166}
167
168def simm13Op : Operand<i32> {
169  let DecoderMethod = "DecodeSIMM13";
170}
171
172// Operand for printing out a condition code.
173let PrintMethod = "printCCOperand" in
174  def CCOp : Operand<i32>;
175
176def SDTSPcmpicc :
177SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
178def SDTSPcmpfcc :
179SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
180def SDTSPbrcc :
181SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
182def SDTSPselectcc :
183SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
184def SDTSPFTOI :
185SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
186def SDTSPITOF :
187SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
188def SDTSPFTOX :
189SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
190def SDTSPXTOF :
191SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
192
193def SDTSPtlsadd :
194SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
195def SDTSPtlsld :
196SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
197
198def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
199def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
200def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
201def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
202def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
203
204def SPhi    : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
205def SPlo    : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
206
207def SPftoi  : SDNode<"SPISD::FTOI", SDTSPFTOI>;
208def SPitof  : SDNode<"SPISD::ITOF", SDTSPITOF>;
209def SPftox  : SDNode<"SPISD::FTOX", SDTSPFTOX>;
210def SPxtof  : SDNode<"SPISD::XTOF", SDTSPXTOF>;
211
212def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
213def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
214def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
215
216//  These are target-independent nodes, but have target-specific formats.
217def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32>,
218                                          SDTCisVT<1, i32> ]>;
219def SDT_SPCallSeqEnd   : SDCallSeqEnd<[ SDTCisVT<0, i32>,
220                                        SDTCisVT<1, i32> ]>;
221
222def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
223                           [SDNPHasChain, SDNPOutGlue]>;
224def callseq_end   : SDNode<"ISD::CALLSEQ_END",   SDT_SPCallSeqEnd,
225                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
226
227def SDT_SPCall    : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
228def call          : SDNode<"SPISD::CALL", SDT_SPCall,
229                           [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
230                            SDNPVariadic]>;
231
232def SDT_SPRet     : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
233def retflag       : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
234                           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
235
236def flushw        : SDNode<"SPISD::FLUSHW", SDTNone,
237                           [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
238
239def tlsadd        : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
240def tlsld         : SDNode<"SPISD::TLS_LD",  SDTSPtlsld>;
241def tlscall       : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
242                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
243                             SDNPVariadic]>;
244
245def getPCX        : Operand<iPTR> {
246  let PrintMethod = "printGetPCX";
247}
248
249//===----------------------------------------------------------------------===//
250// SPARC Flag Conditions
251//===----------------------------------------------------------------------===//
252
253// Note that these values must be kept in sync with the CCOp::CondCode enum
254// values.
255class ICC_VAL<int N> : PatLeaf<(i32 N)>;
256def ICC_NE  : ICC_VAL< 9>;  // Not Equal
257def ICC_E   : ICC_VAL< 1>;  // Equal
258def ICC_G   : ICC_VAL<10>;  // Greater
259def ICC_LE  : ICC_VAL< 2>;  // Less or Equal
260def ICC_GE  : ICC_VAL<11>;  // Greater or Equal
261def ICC_L   : ICC_VAL< 3>;  // Less
262def ICC_GU  : ICC_VAL<12>;  // Greater Unsigned
263def ICC_LEU : ICC_VAL< 4>;  // Less or Equal Unsigned
264def ICC_CC  : ICC_VAL<13>;  // Carry Clear/Great or Equal Unsigned
265def ICC_CS  : ICC_VAL< 5>;  // Carry Set/Less Unsigned
266def ICC_POS : ICC_VAL<14>;  // Positive
267def ICC_NEG : ICC_VAL< 6>;  // Negative
268def ICC_VC  : ICC_VAL<15>;  // Overflow Clear
269def ICC_VS  : ICC_VAL< 7>;  // Overflow Set
270
271class FCC_VAL<int N> : PatLeaf<(i32 N)>;
272def FCC_U   : FCC_VAL<23>;  // Unordered
273def FCC_G   : FCC_VAL<22>;  // Greater
274def FCC_UG  : FCC_VAL<21>;  // Unordered or Greater
275def FCC_L   : FCC_VAL<20>;  // Less
276def FCC_UL  : FCC_VAL<19>;  // Unordered or Less
277def FCC_LG  : FCC_VAL<18>;  // Less or Greater
278def FCC_NE  : FCC_VAL<17>;  // Not Equal
279def FCC_E   : FCC_VAL<25>;  // Equal
280def FCC_UE  : FCC_VAL<26>;  // Unordered or Equal
281def FCC_GE  : FCC_VAL<27>;  // Greater or Equal
282def FCC_UGE : FCC_VAL<28>;  // Unordered or Greater or Equal
283def FCC_LE  : FCC_VAL<29>;  // Less or Equal
284def FCC_ULE : FCC_VAL<30>;  // Unordered or Less or Equal
285def FCC_O   : FCC_VAL<31>;  // Ordered
286
287class CPCC_VAL<int N> : PatLeaf<(i32 N)>;
288def CPCC_3   : CPCC_VAL<39>;  // 3
289def CPCC_2   : CPCC_VAL<38>;  // 2
290def CPCC_23  : CPCC_VAL<37>;  // 2 or 3
291def CPCC_1   : CPCC_VAL<36>;  // 1
292def CPCC_13  : CPCC_VAL<35>;  // 1 or 3
293def CPCC_12  : CPCC_VAL<34>;  // 1 or 2
294def CPCC_123 : CPCC_VAL<33>;  // 1 or 2 or 3
295def CPCC_0   : CPCC_VAL<41>;  // 0
296def CPCC_03  : CPCC_VAL<42>;  // 0 or 3
297def CPCC_02  : CPCC_VAL<43>;  // 0 or 2
298def CPCC_023 : CPCC_VAL<44>;  // 0 or 2 or 3
299def CPCC_01  : CPCC_VAL<45>;  // 0 or 1
300def CPCC_013 : CPCC_VAL<46>;  // 0 or 1 or 3
301def CPCC_012 : CPCC_VAL<47>;  // 0 or 1 or 2
302
303//===----------------------------------------------------------------------===//
304// Instruction Class Templates
305//===----------------------------------------------------------------------===//
306
307/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
308multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
309                 RegisterClass RC, ValueType Ty, Operand immOp,
310                 InstrItinClass itin = IIC_iu_instr> {
311  def rr  : F3_1<2, Op3Val,
312                 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
313                 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
314                 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
315                 itin>;
316  def ri  : F3_2<2, Op3Val,
317                 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
318                 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
319                 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))],
320                 itin>;
321}
322
323/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
324/// pattern.
325multiclass F3_12np<string OpcStr, bits<6> Op3Val, InstrItinClass itin = IIC_iu_instr> {
326  def rr  : F3_1<2, Op3Val,
327                 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
328                 !strconcat(OpcStr, " $rs1, $rs2, $rd"), [],
329                 itin>;
330  def ri  : F3_2<2, Op3Val,
331                 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
332                 !strconcat(OpcStr, " $rs1, $simm13, $rd"), [],
333                 itin>;
334}
335
336// Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
337multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
338           RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_iu_instr> {
339  def rr  : F3_1<3, Op3Val,
340                 (outs RC:$dst), (ins MEMrr:$addr),
341                 !strconcat(OpcStr, " [$addr], $dst"),
342                 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
343                 itin>;
344  def ri  : F3_2<3, Op3Val,
345                 (outs RC:$dst), (ins MEMri:$addr),
346                 !strconcat(OpcStr, " [$addr], $dst"),
347                 [(set Ty:$dst, (OpNode ADDRri:$addr))],
348                 itin>;
349}
350
351// TODO: Instructions of the LoadASI class are currently asm only; hooking up
352// CodeGen's address spaces to use these is a future task.
353class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
354              RegisterClass RC, ValueType Ty, InstrItinClass itin = NoItinerary> :
355  F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
356                !strconcat(OpcStr, "a [$addr] $asi, $dst"),
357                []>;
358
359// LoadA multiclass - As above, but also define alternate address space variant
360multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
361                 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
362                 InstrItinClass itin = NoItinerary> :
363             Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
364  def Arr  : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
365}
366
367// The LDSTUB instruction is supported for asm only.
368// It is unlikely that general-purpose code could make use of it.
369// CAS is preferred for sparc v9.
370def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
371                    "ldstub [$addr], $dst", []>;
372def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
373                    "ldstub [$addr], $dst", []>;
374def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst),
375                         (ins MEMrr:$addr, i8imm:$asi),
376                         "ldstuba [$addr] $asi, $dst", []>;
377
378// Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
379multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
380           RegisterClass RC, ValueType Ty, InstrItinClass itin = IIC_st> {
381  def rr  : F3_1<3, Op3Val,
382                 (outs), (ins MEMrr:$addr, RC:$rd),
383                 !strconcat(OpcStr, " $rd, [$addr]"),
384                 [(OpNode Ty:$rd, ADDRrr:$addr)],
385                 itin>;
386  def ri  : F3_2<3, Op3Val,
387                 (outs), (ins MEMri:$addr, RC:$rd),
388                 !strconcat(OpcStr, " $rd, [$addr]"),
389                 [(OpNode Ty:$rd, ADDRri:$addr)],
390                 itin>;
391}
392
393// TODO: Instructions of the StoreASI class are currently asm only; hooking up
394// CodeGen's address spaces to use these is a future task.
395class StoreASI<string OpcStr, bits<6> Op3Val,
396               SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
397               InstrItinClass itin = IIC_st> :
398  F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
399           !strconcat(OpcStr, "a $rd, [$addr] $asi"),
400           [],
401           itin>;
402
403multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
404                  SDPatternOperator OpNode, RegisterClass RC, ValueType Ty,
405                  InstrItinClass itin = IIC_st> :
406             Store<OpcStr, Op3Val, OpNode, RC, Ty> {
407  def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty, itin>;
408}
409
410//===----------------------------------------------------------------------===//
411// Instructions
412//===----------------------------------------------------------------------===//
413
414// Pseudo instructions.
415class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
416   : InstSP<outs, ins, asmstr, pattern> {
417  let isCodeGenOnly = 1;
418  let isPseudo = 1;
419}
420
421// GETPCX for PIC
422let Defs = [O7] in {
423  def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
424}
425
426let Defs = [O6], Uses = [O6] in {
427def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
428                               "!ADJCALLSTACKDOWN $amt1, $amt2",
429                               [(callseq_start timm:$amt1, timm:$amt2)]>;
430def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
431                            "!ADJCALLSTACKUP $amt1",
432                            [(callseq_end timm:$amt1, timm:$amt2)]>;
433}
434
435let hasSideEffects = 1, mayStore = 1 in {
436  let rd = 0, rs1 = 0, rs2 = 0 in
437    def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
438                      "flushw",
439                      [(flushw)]>, Requires<[HasV9]>;
440  let rd = 8, rs1 = 0, simm13 = 3 in
441    def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
442                   "ta 3",
443                   [(flushw)]>;
444}
445
446// SELECT_CC_* - Used to implement the SELECT_CC DAG operation.  Expanded after
447// instruction selection into a branch sequence.  This has to handle all
448// permutations of selection between i32/f32/f64 on ICC and FCC.
449// Expanded after instruction selection.
450let Uses = [ICC], usesCustomInserter = 1 in {
451  def SELECT_CC_Int_ICC
452   : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
453            "; SELECT_CC_Int_ICC PSEUDO!",
454            [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
455  def SELECT_CC_FP_ICC
456   : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
457            "; SELECT_CC_FP_ICC PSEUDO!",
458            [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
459
460  def SELECT_CC_DFP_ICC
461   : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
462            "; SELECT_CC_DFP_ICC PSEUDO!",
463            [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
464
465  def SELECT_CC_QFP_ICC
466   : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
467            "; SELECT_CC_QFP_ICC PSEUDO!",
468            [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
469}
470
471let usesCustomInserter = 1, Uses = [FCC0] in {
472
473  def SELECT_CC_Int_FCC
474   : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
475            "; SELECT_CC_Int_FCC PSEUDO!",
476            [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
477
478  def SELECT_CC_FP_FCC
479   : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
480            "; SELECT_CC_FP_FCC PSEUDO!",
481            [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
482  def SELECT_CC_DFP_FCC
483   : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
484            "; SELECT_CC_DFP_FCC PSEUDO!",
485            [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
486  def SELECT_CC_QFP_FCC
487   : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
488            "; SELECT_CC_QFP_FCC PSEUDO!",
489            [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
490}
491
492// Section B.1 - Load Integer Instructions, p. 90
493let DecoderMethod = "DecodeLoadInt" in {
494  defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8,  IntRegs, i32>;
495  defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
496  defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8,  IntRegs, i32>;
497  defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
498  defm LD   : LoadA<"ld",   0b000000, 0b010000, load,        IntRegs, i32>;
499}
500
501let DecoderMethod = "DecodeLoadIntPair" in
502  defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32, IIC_ldd>;
503
504// Section B.2 - Load Floating-point Instructions, p. 92
505let DecoderMethod = "DecodeLoadFP" in {
506  defm LDF   : Load<"ld",  0b100000, load,    FPRegs,  f32, IIC_iu_or_fpu_instr>;
507  def LDFArr : LoadASI<"ld",  0b110000, load, FPRegs,  f32, IIC_iu_or_fpu_instr>,
508                Requires<[HasV9]>;
509}
510let DecoderMethod = "DecodeLoadDFP" in {
511  defm LDDF   : Load<"ldd", 0b100011, load,    DFPRegs, f64, IIC_ldd>;
512  def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>,
513                 Requires<[HasV9]>;
514}
515let DecoderMethod = "DecodeLoadQFP" in
516  defm LDQF  : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
517               Requires<[HasV9, HasHardQuad]>;
518
519let DecoderMethod = "DecodeLoadCP" in
520  defm LDC   : Load<"ld", 0b110000, load, CoprocRegs, i32>;
521let DecoderMethod = "DecodeLoadCPPair" in
522  defm LDDC   : Load<"ldd", 0b110011, load, CoprocPair, v2i32, IIC_ldd>;
523
524let DecoderMethod = "DecodeLoadCP", Defs = [CPSR] in {
525  let rd = 0 in {
526    def LDCSRrr : F3_1<3, 0b110001, (outs), (ins MEMrr:$addr),
527                       "ld [$addr], %csr", []>;
528    def LDCSRri : F3_2<3, 0b110001, (outs), (ins MEMri:$addr),
529                       "ld [$addr], %csr", []>;
530  }
531}
532
533let DecoderMethod = "DecodeLoadFP" in
534  let Defs = [FSR] in {
535    let rd = 0 in {
536      def LDFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
537                     "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
538      def LDFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
539                     "ld [$addr], %fsr", [], IIC_iu_or_fpu_instr>;
540    }
541    let rd = 1 in {
542      def LDXFSRrr : F3_1<3, 0b100001, (outs), (ins MEMrr:$addr),
543                     "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
544      def LDXFSRri : F3_2<3, 0b100001, (outs), (ins MEMri:$addr),
545                     "ldx [$addr], %fsr", []>, Requires<[HasV9]>;
546    }
547  }
548
549// Section B.4 - Store Integer Instructions, p. 95
550let DecoderMethod = "DecodeStoreInt" in {
551  defm STB   : StoreA<"stb", 0b000101, 0b010101, truncstorei8,  IntRegs, i32>;
552  defm STH   : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
553  defm ST    : StoreA<"st",  0b000100, 0b010100, store,         IntRegs, i32>;
554}
555
556let DecoderMethod = "DecodeStoreIntPair" in
557  defm STD   : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32, IIC_std>;
558
559// Section B.5 - Store Floating-point Instructions, p. 97
560let DecoderMethod = "DecodeStoreFP" in {
561  defm STF   : Store<"st",  0b100100, store,         FPRegs,  f32>;
562  def STFArr : StoreASI<"st",  0b110100, store,      FPRegs,  f32>,
563               Requires<[HasV9]>;
564}
565let DecoderMethod = "DecodeStoreDFP" in {
566  defm STDF   : Store<"std", 0b100111, store,         DFPRegs, f64, IIC_std>;
567  def STDFArr : StoreASI<"std", 0b110111, store,      DFPRegs, f64>,
568                Requires<[HasV9]>;
569}
570let DecoderMethod = "DecodeStoreQFP" in
571  defm STQF  : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
572               Requires<[HasV9, HasHardQuad]>;
573
574let DecoderMethod = "DecodeStoreCP" in
575  defm STC   : Store<"st", 0b110100, store, CoprocRegs, i32>;
576
577let DecoderMethod = "DecodeStoreCPPair" in
578  defm STDC   : Store<"std", 0b110111, store, CoprocPair, v2i32, IIC_std>;
579
580let DecoderMethod = "DecodeStoreCP", rd = 0 in {
581  let Defs = [CPSR] in {
582    def STCSRrr : F3_1<3, 0b110101, (outs MEMrr:$addr), (ins),
583                       "st %csr, [$addr]", [], IIC_st>;
584    def STCSRri : F3_2<3, 0b110101, (outs MEMri:$addr), (ins),
585                       "st %csr, [$addr]", [], IIC_st>;
586  }
587  let Defs = [CPQ] in {
588    def STDCQrr : F3_1<3, 0b110110, (outs MEMrr:$addr), (ins),
589                       "std %cq, [$addr]", [], IIC_std>;
590    def STDCQri : F3_2<3, 0b110110, (outs MEMri:$addr), (ins),
591                       "std %cq, [$addr]", [], IIC_std>;
592  }
593}
594
595let DecoderMethod = "DecodeStoreFP" in {
596  let rd = 0 in {
597    let Defs = [FSR] in {
598      def STFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
599                     "st %fsr, [$addr]", [], IIC_st>;
600      def STFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
601                     "st %fsr, [$addr]", [], IIC_st>;
602    }
603    let Defs = [FQ] in {
604      def STDFQrr : F3_1<3, 0b100110, (outs MEMrr:$addr), (ins),
605                     "std %fq, [$addr]", [], IIC_std>;
606      def STDFQri : F3_2<3, 0b100110, (outs MEMri:$addr), (ins),
607                     "std %fq, [$addr]", [], IIC_std>;
608    }
609  }
610  let rd = 1, Defs = [FSR] in {
611    def STXFSRrr : F3_1<3, 0b100101, (outs MEMrr:$addr), (ins),
612                   "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
613    def STXFSRri : F3_2<3, 0b100101, (outs MEMri:$addr), (ins),
614                   "stx %fsr, [$addr]", []>, Requires<[HasV9]>;
615  }
616}
617
618// Section B.8 - SWAP Register with Memory Instruction
619// (Atomic swap)
620let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
621  def SWAPrr : F3_1<3, 0b001111,
622                 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
623                 "swap [$addr], $dst",
624                 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
625  def SWAPri : F3_2<3, 0b001111,
626                 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
627                 "swap [$addr], $dst",
628                 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
629  def SWAPArr : F3_1_asi<3, 0b011111,
630                 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
631                 "swapa [$addr] $asi, $dst",
632                 [/*FIXME: pattern?*/]>;
633}
634
635
636// Section B.9 - SETHI Instruction, p. 104
637def SETHIi: F2_1<0b100,
638                 (outs IntRegs:$rd), (ins i32imm:$imm22),
639                 "sethi $imm22, $rd",
640                 [(set i32:$rd, SETHIimm:$imm22)],
641                 IIC_iu_instr>;
642
643// Section B.10 - NOP Instruction, p. 105
644// (It's a special case of SETHI)
645let rd = 0, imm22 = 0 in
646  def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
647
648// Section B.11 - Logical Instructions, p. 106
649defm AND    : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
650
651def ANDNrr  : F3_1<2, 0b000101,
652                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
653                   "andn $rs1, $rs2, $rd",
654                   [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
655def ANDNri  : F3_2<2, 0b000101,
656                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
657                   "andn $rs1, $simm13, $rd", []>;
658
659defm OR     : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
660
661def ORNrr   : F3_1<2, 0b000110,
662                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
663                   "orn $rs1, $rs2, $rd",
664                   [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
665def ORNri   : F3_2<2, 0b000110,
666                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
667                   "orn $rs1, $simm13, $rd", []>;
668defm XOR    : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
669
670def XNORrr  : F3_1<2, 0b000111,
671                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
672                   "xnor $rs1, $rs2, $rd",
673                   [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
674def XNORri  : F3_2<2, 0b000111,
675                   (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
676                   "xnor $rs1, $simm13, $rd", []>;
677
678def : Pat<(and IntRegs:$rs1, SETHIimm_not:$rs2),
679          (ANDNrr i32:$rs1, (SETHIi SETHIimm_not:$rs2))>;
680
681def : Pat<(or IntRegs:$rs1, SETHIimm_not:$rs2),
682          (ORNrr i32:$rs1,  (SETHIi SETHIimm_not:$rs2))>;
683
684let Defs = [ICC] in {
685  defm ANDCC  : F3_12np<"andcc",  0b010001>;
686  defm ANDNCC : F3_12np<"andncc", 0b010101>;
687  defm ORCC   : F3_12np<"orcc",   0b010010>;
688  defm ORNCC  : F3_12np<"orncc",  0b010110>;
689  defm XORCC  : F3_12np<"xorcc",  0b010011>;
690  defm XNORCC : F3_12np<"xnorcc", 0b010111>;
691}
692
693// Section B.12 - Shift Instructions, p. 107
694defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
695defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
696defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
697
698// Section B.13 - Add Instructions, p. 108
699defm ADD   : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
700
701// "LEA" forms of add (patterns to make tblgen happy)
702let Predicates = [Is32Bit], isCodeGenOnly = 1 in
703  def LEA_ADDri   : F3_2<2, 0b000000,
704                     (outs IntRegs:$dst), (ins MEMri:$addr),
705                     "add ${addr:arith}, $dst",
706                     [(set iPTR:$dst, ADDRri:$addr)]>;
707
708let Defs = [ICC] in
709  defm ADDCC  : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
710
711let Uses = [ICC] in
712  defm ADDC   : F3_12np<"addx", 0b001000>;
713
714let Uses = [ICC], Defs = [ICC] in
715  defm ADDE  : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
716
717// Section B.15 - Subtract Instructions, p. 110
718defm SUB    : F3_12  <"sub"  , 0b000100, sub, IntRegs, i32, simm13Op>;
719let Uses = [ICC], Defs = [ICC] in
720  defm SUBE   : F3_12  <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
721
722let Defs = [ICC] in
723  defm SUBCC  : F3_12  <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
724
725let Uses = [ICC] in
726  defm SUBC   : F3_12np <"subx", 0b001100>;
727
728// cmp (from Section A.3) is a specialized alias for subcc
729let Defs = [ICC], rd = 0 in {
730  def CMPrr   : F3_1<2, 0b010100,
731                     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
732                     "cmp $rs1, $rs2",
733                     [(SPcmpicc i32:$rs1, i32:$rs2)]>;
734  def CMPri   : F3_2<2, 0b010100,
735                     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
736                     "cmp $rs1, $simm13",
737                     [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
738}
739
740// Section B.18 - Multiply Instructions, p. 113
741let Defs = [Y] in {
742  defm UMUL : F3_12<"umul", 0b001010, umullohi, IntRegs, i32, simm13Op, IIC_iu_umul>;
743  defm SMUL : F3_12<"smul", 0b001011, smullohi, IntRegs, i32, simm13Op, IIC_iu_smul>;
744}
745
746let Defs = [Y, ICC] in {
747  defm UMULCC : F3_12np<"umulcc", 0b011010, IIC_iu_umul>;
748  defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>;
749}
750
751let Defs = [Y, ICC], Uses = [Y, ICC] in {
752  defm MULSCC : F3_12np<"mulscc", 0b100100>;
753}
754
755// Section B.19 - Divide Instructions, p. 115
756let Uses = [Y], Defs = [Y] in {
757  defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>;
758  defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>;
759}
760
761let Uses = [Y], Defs = [Y, ICC] in {
762  defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>;
763  defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>;
764}
765
766// Section B.20 - SAVE and RESTORE, p. 117
767defm SAVE    : F3_12np<"save"   , 0b111100>;
768defm RESTORE : F3_12np<"restore", 0b111101>;
769
770// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
771
772// unconditional branch class.
773class BranchAlways<dag ins, string asmstr, list<dag> pattern>
774  : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
775  let isBranch     = 1;
776  let isTerminator = 1;
777  let hasDelaySlot = 1;
778  let isBarrier    = 1;
779}
780
781let cond = 8 in
782  def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
783
784
785let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
786
787// conditional branch class:
788class BranchSP<dag ins, string asmstr, list<dag> pattern>
789 : F2_2<0b010, 0, (outs), ins, asmstr, pattern, IIC_iu_instr>;
790
791// conditional branch with annul class:
792class BranchSPA<dag ins, string asmstr, list<dag> pattern>
793 : F2_2<0b010, 1, (outs), ins, asmstr, pattern, IIC_iu_instr>;
794
795// Conditional branch class on %icc|%xcc with predication:
796multiclass IPredBranch<string regstr, list<dag> CCPattern> {
797  def CC    : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
798                   !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
799                   CCPattern,
800                   IIC_iu_instr>;
801  def CCA   : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
802                   !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
803                   [],
804                   IIC_iu_instr>;
805  def CCNT  : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
806                   !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
807                   [],
808                   IIC_iu_instr>;
809  def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
810                   !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
811                   [],
812                   IIC_iu_instr>;
813}
814
815} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
816
817
818// Indirect branch instructions.
819let isTerminator = 1, isBarrier = 1,  hasDelaySlot = 1, isBranch =1,
820     isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
821  def BINDrr  : F3_1<2, 0b111000,
822                   (outs), (ins MEMrr:$ptr),
823                   "jmp $ptr",
824                   [(brind ADDRrr:$ptr)]>;
825  def BINDri  : F3_2<2, 0b111000,
826                   (outs), (ins MEMri:$ptr),
827                   "jmp $ptr",
828                   [(brind ADDRri:$ptr)]>;
829}
830
831let Uses = [ICC] in {
832  def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
833                         "b$cond $imm22",
834                        [(SPbricc bb:$imm22, imm:$cond)]>;
835  def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
836                         "b$cond,a $imm22", []>;
837
838  let Predicates = [HasV9], cc = 0b00 in
839    defm BPI : IPredBranch<"%icc", []>;
840}
841
842// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
843
844let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
845
846// floating-point conditional branch class:
847class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
848 : F2_2<0b110, 0, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
849
850// floating-point conditional branch with annul class:
851class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
852 : F2_2<0b110, 1, (outs), ins, asmstr, pattern, IIC_fpu_normal_instr>;
853
854// Conditional branch class on %fcc0-%fcc3 with predication:
855multiclass FPredBranch {
856  def CC    : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
857                                         FCCRegs:$cc),
858                  "fb$cond $cc, $imm19", [], IIC_fpu_normal_instr>;
859  def CCA   : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
860                                         FCCRegs:$cc),
861                  "fb$cond,a $cc, $imm19", [], IIC_fpu_normal_instr>;
862  def CCNT  : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
863                                         FCCRegs:$cc),
864                  "fb$cond,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
865  def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
866                                         FCCRegs:$cc),
867                  "fb$cond,a,pn $cc, $imm19", [], IIC_fpu_normal_instr>;
868}
869} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
870
871let Uses = [FCC0] in {
872  def FBCOND  : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
873                              "fb$cond $imm22",
874                              [(SPbrfcc bb:$imm22, imm:$cond)]>;
875  def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
876                             "fb$cond,a $imm22", []>;
877}
878
879let Predicates = [HasV9] in
880  defm BPF : FPredBranch;
881
882// Section B.22 - Branch on Co-processor Condition Codes Instructions, p. 123
883let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
884
885// co-processor conditional branch class:
886class CPBranchSP<dag ins, string asmstr, list<dag> pattern>
887 : F2_2<0b111, 0, (outs), ins, asmstr, pattern>;
888
889// co-processor conditional branch with annul class:
890class CPBranchSPA<dag ins, string asmstr, list<dag> pattern>
891 : F2_2<0b111, 1, (outs), ins, asmstr, pattern>;
892
893} // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
894
895def CBCOND  : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
896                          "cb$cond $imm22",
897                          [(SPbrfcc bb:$imm22, imm:$cond)]>;
898def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
899                           "cb$cond,a $imm22", []>;
900
901// Section B.24 - Call and Link Instruction, p. 125
902// This is the only Format 1 instruction
903let Uses = [O6],
904    hasDelaySlot = 1, isCall = 1 in {
905  def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
906                    "call $disp",
907                    [],
908                    IIC_jmp_or_call> {
909    bits<30> disp;
910    let op = 1;
911    let Inst{29-0} = disp;
912  }
913
914  // indirect calls: special cases of JMPL.
915  let isCodeGenOnly = 1, rd = 15 in {
916    def CALLrr : F3_1<2, 0b111000,
917                      (outs), (ins MEMrr:$ptr, variable_ops),
918                      "call $ptr",
919                      [(call ADDRrr:$ptr)],
920                      IIC_jmp_or_call>;
921    def CALLri : F3_2<2, 0b111000,
922                      (outs), (ins MEMri:$ptr, variable_ops),
923                      "call $ptr",
924                      [(call ADDRri:$ptr)],
925                      IIC_jmp_or_call>;
926  }
927}
928
929// Section B.25 - Jump and Link Instruction
930
931// JMPL Instruction.
932let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
933    DecoderMethod = "DecodeJMPL" in {
934  def JMPLrr: F3_1<2, 0b111000,
935                   (outs IntRegs:$dst), (ins MEMrr:$addr),
936                   "jmpl $addr, $dst",
937                   [],
938                   IIC_jmp_or_call>;
939  def JMPLri: F3_2<2, 0b111000,
940                   (outs IntRegs:$dst), (ins MEMri:$addr),
941                   "jmpl $addr, $dst",
942                   [],
943                   IIC_jmp_or_call>;
944}
945
946// Section A.3 - Synthetic Instructions, p. 85
947// special cases of JMPL:
948let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
949    isCodeGenOnly = 1 in {
950  let rd = 0, rs1 = 15 in
951    def RETL: F3_2<2, 0b111000,
952                   (outs), (ins i32imm:$val),
953                   "jmp %o7+$val",
954                   [(retflag simm13:$val)],
955                   IIC_jmp_or_call>;
956
957  let rd = 0, rs1 = 31 in
958    def RET: F3_2<2, 0b111000,
959                  (outs), (ins i32imm:$val),
960                  "jmp %i7+$val",
961                  [],
962                  IIC_jmp_or_call>;
963}
964
965// Section B.26 - Return from Trap Instruction
966let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
967     isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
968  def RETTrr : F3_1<2, 0b111001,
969                   (outs), (ins MEMrr:$addr),
970                   "rett $addr",
971                   [],
972                   IIC_jmp_or_call>;
973  def RETTri : F3_2<2, 0b111001,
974                    (outs), (ins MEMri:$addr),
975                    "rett $addr",
976                    [],
977                    IIC_jmp_or_call>;
978}
979
980
981// Section B.27 - Trap on Integer Condition Codes Instruction
982// conditional branch class:
983let DecoderNamespace = "SparcV8", DecoderMethod = "DecodeTRAP", hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
984{
985  def TRAPrr : TRAPSPrr<0b111010,
986                        (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
987                        "t$cond $rs1 + $rs2",
988                        []>;
989  def TRAPri : TRAPSPri<0b111010,
990                        (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
991                        "t$cond $rs1 + $imm",
992                        []>;
993}
994
995multiclass TRAP<string regStr> {
996  def rr : TRAPSPrr<0b111010,
997                    (outs), (ins IntRegs:$rs1, IntRegs:$rs2, CCOp:$cond),
998                    !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"),
999                    []>;
1000  def ri : TRAPSPri<0b111010,
1001                    (outs), (ins IntRegs:$rs1, i32imm:$imm, CCOp:$cond),
1002                    !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"),
1003                    []>;
1004}
1005
1006let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [HasV9], hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
1007  defm TICC : TRAP<"%icc">;
1008
1009
1010let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
1011  def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
1012
1013let hasSideEffects = 1, rd = 0b01000, rs1 = 0, simm13 = 1 in
1014  def TA1 : F3_2<0b10, 0b111010, (outs), (ins), "ta 1", [(debugtrap)]>;
1015
1016// Section B.28 - Read State Register Instructions
1017let rs2 = 0 in
1018  def RDASR : F3_1<2, 0b101000,
1019                 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
1020                 "rd $rs1, $rd", []>;
1021
1022// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1023let Predicates = [HasNoV9] in {
1024  let rs2 = 0, rs1 = 0, Uses=[PSR] in
1025    def RDPSR : F3_1<2, 0b101001,
1026		     (outs IntRegs:$rd), (ins),
1027		     "rd %psr, $rd", []>;
1028
1029  let rs2 = 0, rs1 = 0, Uses=[WIM] in
1030    def RDWIM : F3_1<2, 0b101010,
1031		     (outs IntRegs:$rd), (ins),
1032		     "rd %wim, $rd", []>;
1033
1034  let rs2 = 0, rs1 = 0, Uses=[TBR] in
1035    def RDTBR : F3_1<2, 0b101011,
1036		     (outs IntRegs:$rd), (ins),
1037		     "rd %tbr, $rd", []>;
1038}
1039
1040// Section B.29 - Write State Register Instructions
1041def WRASRrr : F3_1<2, 0b110000,
1042                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1043                 "wr $rs1, $rs2, $rd", []>;
1044def WRASRri : F3_2<2, 0b110000,
1045                 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1046                 "wr $rs1, $simm13, $rd", []>;
1047
1048// PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
1049let Predicates = [HasNoV9] in {
1050  let Defs = [PSR], rd=0 in {
1051    def WRPSRrr : F3_1<2, 0b110001,
1052		     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1053		     "wr $rs1, $rs2, %psr", []>;
1054    def WRPSRri : F3_2<2, 0b110001,
1055		     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1056		     "wr $rs1, $simm13, %psr", []>;
1057  }
1058
1059  let Defs = [WIM], rd=0 in {
1060    def WRWIMrr : F3_1<2, 0b110010,
1061		     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1062		     "wr $rs1, $rs2, %wim", []>;
1063    def WRWIMri : F3_2<2, 0b110010,
1064		     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1065		     "wr $rs1, $simm13, %wim", []>;
1066  }
1067
1068  let Defs = [TBR], rd=0 in {
1069    def WRTBRrr : F3_1<2, 0b110011,
1070		     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1071		     "wr $rs1, $rs2, %tbr", []>;
1072    def WRTBRri : F3_2<2, 0b110011,
1073		     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1074		     "wr $rs1, $simm13, %tbr", []>;
1075  }
1076}
1077
1078// Section B.30 - STBAR Instruction
1079let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1080  def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
1081
1082
1083// Section B.31 - Unimplmented Instruction
1084let rd = 0 in
1085  def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
1086                  "unimp $imm22", []>;
1087
1088// Section B.32 - Flush Instruction Memory
1089let rd = 0 in {
1090  def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
1091                       "flush $addr", []>;
1092  def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
1093                       "flush $addr", []>;
1094
1095  // The no-arg FLUSH is only here for the benefit of the InstAlias
1096  // "flush", which cannot seem to use FLUSHrr, due to the inability
1097  // to construct a MEMrr with fixed G0 registers.
1098  let rs1 = 0, rs2 = 0 in
1099    def FLUSH   : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
1100}
1101
1102// Section B.33 - Floating-point Operate (FPop) Instructions
1103
1104// Convert Integer to Floating-point Instructions, p. 141
1105def FITOS : F3_3u<2, 0b110100, 0b011000100,
1106                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1107                 "fitos $rs2, $rd",
1108                 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))],
1109                 IIC_fpu_fast_instr>;
1110def FITOD : F3_3u<2, 0b110100, 0b011001000,
1111                 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1112                 "fitod $rs2, $rd",
1113                 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))],
1114                 IIC_fpu_fast_instr>;
1115def FITOQ : F3_3u<2, 0b110100, 0b011001100,
1116                 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1117                 "fitoq $rs2, $rd",
1118                 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
1119                 Requires<[HasHardQuad]>;
1120
1121// Convert Floating-point to Integer Instructions, p. 142
1122def FSTOI : F3_3u<2, 0b110100, 0b011010001,
1123                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1124                 "fstoi $rs2, $rd",
1125                 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))],
1126                 IIC_fpu_fast_instr>;
1127def FDTOI : F3_3u<2, 0b110100, 0b011010010,
1128                 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1129                 "fdtoi $rs2, $rd",
1130                 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))],
1131                 IIC_fpu_fast_instr>;
1132def FQTOI : F3_3u<2, 0b110100, 0b011010011,
1133                 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1134                 "fqtoi $rs2, $rd",
1135                 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
1136                 Requires<[HasHardQuad]>;
1137
1138// Convert between Floating-point Formats Instructions, p. 143
1139def FSTOD : F3_3u<2, 0b110100, 0b011001001,
1140                 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
1141                 "fstod $rs2, $rd",
1142                 [(set f64:$rd, (fpextend f32:$rs2))],
1143                 IIC_fpu_stod>;
1144def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
1145                 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
1146                 "fstoq $rs2, $rd",
1147                 [(set f128:$rd, (fpextend f32:$rs2))]>,
1148                 Requires<[HasHardQuad]>;
1149def FDTOS : F3_3u<2, 0b110100, 0b011000110,
1150                 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
1151                 "fdtos $rs2, $rd",
1152                 [(set f32:$rd, (fpround f64:$rs2))],
1153                 IIC_fpu_fast_instr>;
1154def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
1155                 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
1156                 "fdtoq $rs2, $rd",
1157                 [(set f128:$rd, (fpextend f64:$rs2))]>,
1158                 Requires<[HasHardQuad]>;
1159def FQTOS : F3_3u<2, 0b110100, 0b011000111,
1160                 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
1161                 "fqtos $rs2, $rd",
1162                 [(set f32:$rd, (fpround f128:$rs2))]>,
1163                 Requires<[HasHardQuad]>;
1164def FQTOD : F3_3u<2, 0b110100, 0b011001011,
1165                 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
1166                 "fqtod $rs2, $rd",
1167                 [(set f64:$rd, (fpround f128:$rs2))]>,
1168                 Requires<[HasHardQuad]>;
1169
1170// Floating-point Move Instructions, p. 144
1171def FMOVS : F3_3u<2, 0b110100, 0b000000001,
1172                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1173                 "fmovs $rs2, $rd", []>;
1174def FNEGS : F3_3u<2, 0b110100, 0b000000101,
1175                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1176                 "fnegs $rs2, $rd",
1177                 [(set f32:$rd, (fneg f32:$rs2))],
1178                 IIC_fpu_negs>;
1179def FABSS : F3_3u<2, 0b110100, 0b000001001,
1180                 (outs FPRegs:$rd), (ins FPRegs:$rs2),
1181                 "fabss $rs2, $rd",
1182                 [(set f32:$rd, (fabs f32:$rs2))],
1183                 IIC_fpu_abs>;
1184
1185
1186// Floating-point Square Root Instructions, p.145
1187// FSQRTS generates an erratum on LEON processors, so by disabling this instruction
1188// this will be promoted to use FSQRTD with doubles instead.
1189let Predicates = [HasNoFdivSqrtFix] in
1190def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
1191                  (outs FPRegs:$rd), (ins FPRegs:$rs2),
1192                  "fsqrts $rs2, $rd",
1193                  [(set f32:$rd, (fsqrt f32:$rs2))],
1194                  IIC_fpu_sqrts>;
1195def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
1196                  (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1197                  "fsqrtd $rs2, $rd",
1198                  [(set f64:$rd, (fsqrt f64:$rs2))],
1199                  IIC_fpu_sqrtd>;
1200def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
1201                  (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1202                  "fsqrtq $rs2, $rd",
1203                  [(set f128:$rd, (fsqrt f128:$rs2))]>,
1204                  Requires<[HasHardQuad]>;
1205
1206
1207
1208// Floating-point Add and Subtract Instructions, p. 146
1209def FADDS  : F3_3<2, 0b110100, 0b001000001,
1210                  (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1211                  "fadds $rs1, $rs2, $rd",
1212                  [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))],
1213                  IIC_fpu_fast_instr>;
1214def FADDD  : F3_3<2, 0b110100, 0b001000010,
1215                  (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1216                  "faddd $rs1, $rs2, $rd",
1217                  [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))],
1218                  IIC_fpu_fast_instr>;
1219def FADDQ  : F3_3<2, 0b110100, 0b001000011,
1220                  (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1221                  "faddq $rs1, $rs2, $rd",
1222                  [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
1223                  Requires<[HasHardQuad]>;
1224
1225def FSUBS  : F3_3<2, 0b110100, 0b001000101,
1226                  (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1227                  "fsubs $rs1, $rs2, $rd",
1228                  [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))],
1229                  IIC_fpu_fast_instr>;
1230def FSUBD  : F3_3<2, 0b110100, 0b001000110,
1231                  (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1232                  "fsubd $rs1, $rs2, $rd",
1233                  [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))],
1234                  IIC_fpu_fast_instr>;
1235def FSUBQ  : F3_3<2, 0b110100, 0b001000111,
1236                  (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1237                  "fsubq $rs1, $rs2, $rd",
1238                  [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
1239                  Requires<[HasHardQuad]>;
1240
1241
1242// Floating-point Multiply and Divide Instructions, p. 147
1243def FMULS  : F3_3<2, 0b110100, 0b001001001,
1244                  (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1245                  "fmuls $rs1, $rs2, $rd",
1246                  [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))],
1247                  IIC_fpu_muls>,
1248		  Requires<[HasFMULS]>;
1249def FMULD  : F3_3<2, 0b110100, 0b001001010,
1250                  (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1251                  "fmuld $rs1, $rs2, $rd",
1252                  [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))],
1253                  IIC_fpu_muld>;
1254def FMULQ  : F3_3<2, 0b110100, 0b001001011,
1255                  (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1256                  "fmulq $rs1, $rs2, $rd",
1257                  [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1258                  Requires<[HasHardQuad]>;
1259
1260def FSMULD : F3_3<2, 0b110100, 0b001101001,
1261                  (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1262                  "fsmuld $rs1, $rs2, $rd",
1263                  [(set f64:$rd, (fmul (fpextend f32:$rs1),
1264                                        (fpextend f32:$rs2)))],
1265                  IIC_fpu_muld>,
1266		  Requires<[HasFSMULD]>;
1267def FDMULQ : F3_3<2, 0b110100, 0b001101110,
1268                  (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1269                  "fdmulq $rs1, $rs2, $rd",
1270                  [(set f128:$rd, (fmul (fpextend f64:$rs1),
1271                                         (fpextend f64:$rs2)))]>,
1272                  Requires<[HasHardQuad]>;
1273
1274// FDIVS generates an erratum on LEON processors, so by disabling this instruction
1275// this will be promoted to use FDIVD with doubles instead.
1276def FDIVS  : F3_3<2, 0b110100, 0b001001101,
1277                 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1278                 "fdivs $rs1, $rs2, $rd",
1279                 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))],
1280                 IIC_fpu_divs>;
1281def FDIVD  : F3_3<2, 0b110100, 0b001001110,
1282                 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1283                 "fdivd $rs1, $rs2, $rd",
1284                 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))],
1285                 IIC_fpu_divd>;
1286def FDIVQ  : F3_3<2, 0b110100, 0b001001111,
1287                 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1288                 "fdivq $rs1, $rs2, $rd",
1289                 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1290                 Requires<[HasHardQuad]>;
1291
1292// Floating-point Compare Instructions, p. 148
1293// Note: the 2nd template arg is different for these guys.
1294// Note 2: the result of a FCMP is not available until the 2nd cycle
1295// after the instr is retired, but there is no interlock in Sparc V8.
1296// This behavior is modeled with a forced noop after the instruction in
1297// DelaySlotFiller.
1298
1299let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1300  def FCMPS  : F3_3c<2, 0b110101, 0b001010001,
1301                   (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1302                   "fcmps $rs1, $rs2",
1303                   [(SPcmpfcc f32:$rs1, f32:$rs2)],
1304                   IIC_fpu_fast_instr>;
1305  def FCMPD  : F3_3c<2, 0b110101, 0b001010010,
1306                   (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1307                   "fcmpd $rs1, $rs2",
1308                   [(SPcmpfcc f64:$rs1, f64:$rs2)],
1309                   IIC_fpu_fast_instr>;
1310  def FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
1311                   (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1312                   "fcmpq $rs1, $rs2",
1313                   [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1314                   Requires<[HasHardQuad]>;
1315}
1316
1317//===----------------------------------------------------------------------===//
1318// Instructions for Thread Local Storage(TLS).
1319//===----------------------------------------------------------------------===//
1320let isAsmParserOnly = 1 in {
1321def TLS_ADDrr : F3_1<2, 0b000000,
1322                    (outs IntRegs:$rd),
1323                    (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1324                    "add $rs1, $rs2, $rd, $sym",
1325                    [(set i32:$rd,
1326                        (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1327
1328let mayLoad = 1 in
1329  def TLS_LDrr : F3_1<3, 0b000000,
1330                      (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1331                      "ld [$addr], $dst, $sym",
1332                      [(set i32:$dst,
1333                          (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
1334
1335let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
1336  def TLS_CALL : InstSP<(outs),
1337                        (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1338                        "call $disp, $sym",
1339                        [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)],
1340                        IIC_jmp_or_call> {
1341  bits<30> disp;
1342  let op = 1;
1343  let Inst{29-0} = disp;
1344}
1345}
1346
1347//===----------------------------------------------------------------------===//
1348// V9 Instructions
1349//===----------------------------------------------------------------------===//
1350
1351// V9 Conditional Moves.
1352let Predicates = [HasV9], Constraints = "$f = $rd" in {
1353  // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
1354  let Uses = [ICC], intcc = 1, cc = 0b00 in {
1355    def MOVICCrr
1356      : F4_1<0b101100, (outs IntRegs:$rd),
1357             (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1358             "mov$cond %icc, $rs2, $rd",
1359             [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1360
1361    def MOVICCri
1362      : F4_2<0b101100, (outs IntRegs:$rd),
1363             (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1364             "mov$cond %icc, $simm11, $rd",
1365             [(set i32:$rd,
1366                    (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1367  }
1368
1369  let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1370    def MOVFCCrr
1371      : F4_1<0b101100, (outs IntRegs:$rd),
1372             (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1373             "mov$cond %fcc0, $rs2, $rd",
1374             [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1375    def MOVFCCri
1376      : F4_2<0b101100, (outs IntRegs:$rd),
1377             (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1378             "mov$cond %fcc0, $simm11, $rd",
1379             [(set i32:$rd,
1380                    (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1381  }
1382
1383  let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
1384    def FMOVS_ICC
1385      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1386             (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1387             "fmovs$cond %icc, $rs2, $rd",
1388             [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1389    def FMOVD_ICC
1390      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1391               (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1392               "fmovd$cond %icc, $rs2, $rd",
1393               [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1394    def FMOVQ_ICC
1395      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1396               (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1397               "fmovq$cond %icc, $rs2, $rd",
1398               [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1399               Requires<[HasHardQuad]>;
1400  }
1401
1402  let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
1403    def FMOVS_FCC
1404      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1405             (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1406             "fmovs$cond %fcc0, $rs2, $rd",
1407             [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1408    def FMOVD_FCC
1409      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1410             (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1411             "fmovd$cond %fcc0, $rs2, $rd",
1412             [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1413    def FMOVQ_FCC
1414      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1415             (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1416             "fmovq$cond %fcc0, $rs2, $rd",
1417             [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1418             Requires<[HasHardQuad]>;
1419  }
1420
1421}
1422
1423// Floating-Point Move Instructions, p. 164 of the V9 manual.
1424let Predicates = [HasV9] in {
1425  def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1426                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1427                   "fmovd $rs2, $rd", []>;
1428  def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1429                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1430                   "fmovq $rs2, $rd", []>,
1431                   Requires<[HasHardQuad]>;
1432  def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1433                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1434                   "fnegd $rs2, $rd",
1435                   [(set f64:$rd, (fneg f64:$rs2))]>;
1436  def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1437                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1438                   "fnegq $rs2, $rd",
1439                   [(set f128:$rd, (fneg f128:$rs2))]>,
1440                   Requires<[HasHardQuad]>;
1441  def FABSD : F3_3u<2, 0b110100, 0b000001010,
1442                   (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1443                   "fabsd $rs2, $rd",
1444                   [(set f64:$rd, (fabs f64:$rs2))]>;
1445  def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1446                   (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1447                   "fabsq $rs2, $rd",
1448                   [(set f128:$rd, (fabs f128:$rs2))]>,
1449                   Requires<[HasHardQuad]>;
1450}
1451
1452// Floating-point compare instruction with %fcc0-%fcc3.
1453def V9FCMPS  : F3_3c<2, 0b110101, 0b001010001,
1454               (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1455               "fcmps $rd, $rs1, $rs2", []>;
1456def V9FCMPD  : F3_3c<2, 0b110101, 0b001010010,
1457                (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1458                "fcmpd $rd, $rs1, $rs2", []>;
1459def V9FCMPQ  : F3_3c<2, 0b110101, 0b001010011,
1460                (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1461                "fcmpq $rd, $rs1, $rs2", []>,
1462                 Requires<[HasHardQuad]>;
1463
1464let hasSideEffects = 1 in {
1465  def V9FCMPES  : F3_3c<2, 0b110101, 0b001010101,
1466                   (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1467                   "fcmpes $rd, $rs1, $rs2", []>;
1468  def V9FCMPED  : F3_3c<2, 0b110101, 0b001010110,
1469                   (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1470                   "fcmped $rd, $rs1, $rs2", []>;
1471  def V9FCMPEQ  : F3_3c<2, 0b110101, 0b001010111,
1472                   (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1473                   "fcmpeq $rd, $rs1, $rs2", []>,
1474                   Requires<[HasHardQuad]>;
1475}
1476
1477// Floating point conditional move instrucitons with %fcc0-%fcc3.
1478let Predicates = [HasV9] in {
1479  let Constraints = "$f = $rd", intcc = 0 in {
1480    def V9MOVFCCrr
1481      : F4_1<0b101100, (outs IntRegs:$rd),
1482             (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1483             "mov$cond $cc, $rs2, $rd", []>;
1484    def V9MOVFCCri
1485      : F4_2<0b101100, (outs IntRegs:$rd),
1486             (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1487             "mov$cond $cc, $simm11, $rd", []>;
1488    def V9FMOVS_FCC
1489      : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1490             (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1491             "fmovs$cond $opf_cc, $rs2, $rd", []>;
1492    def V9FMOVD_FCC
1493      : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1494             (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1495             "fmovd$cond $opf_cc, $rs2, $rd", []>;
1496    def V9FMOVQ_FCC
1497      : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1498             (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1499             "fmovq$cond $opf_cc, $rs2, $rd", []>,
1500             Requires<[HasHardQuad]>;
1501  } // Constraints = "$f = $rd", ...
1502} // let Predicates = [hasV9]
1503
1504
1505// POPCrr - This does a ctpop of a 64-bit register.  As such, we have to clear
1506// the top 32-bits before using it.  To do this clearing, we use a SRLri X,0.
1507let rs1 = 0 in
1508  def POPCrr : F3_1<2, 0b101110,
1509                    (outs IntRegs:$rd), (ins IntRegs:$rs2),
1510                    "popc $rs2, $rd", []>, Requires<[HasV9]>;
1511def : Pat<(ctpop i32:$src),
1512          (POPCrr (SRLri $src, 0))>;
1513
1514let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1515 def MEMBARi : F3_2<2, 0b101000, (outs), (ins MembarTag:$simm13),
1516                    "membar $simm13", []>;
1517
1518// The CAS instruction, unlike other instructions, only comes in a
1519// form which requires an ASI be provided. The ASI value hardcoded
1520// here is ASI_PRIMARY, the default unprivileged ASI for SparcV9.
1521let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1522  def CASrr: F3_1_asi<3, 0b111100,
1523                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1524                                     IntRegs:$swap),
1525                 "cas [$rs1], $rs2, $rd",
1526                 [(set i32:$rd,
1527                     (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1528
1529
1530// CASA is supported as an instruction on some LEON3 and all LEON4 processors.
1531// This version can be automatically lowered from C code, selecting ASI 10
1532let Predicates = [HasLeonCASA], Constraints = "$swap = $rd", asi = 0b00001010 in
1533  def CASAasi10: F3_1_asi<3, 0b111100,
1534                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1535                                     IntRegs:$swap),
1536                 "casa [$rs1] 10, $rs2, $rd",
1537                 [(set i32:$rd,
1538                     (atomic_cmp_swap_32 iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1539
1540// CASA supported on some LEON3 and all LEON4 processors. Same pattern as
1541// CASrr, above, but with a different ASI. This version is supported for
1542// inline assembly lowering only.
1543let Predicates = [HasLeonCASA], Constraints = "$swap = $rd" in
1544  def CASArr: F3_1_asi<3, 0b111100,
1545                (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1546                                     IntRegs:$swap, i8imm:$asi),
1547                 "casa [$rs1] $asi, $rs2, $rd", []>;
1548
1549// TODO: Add DAG sequence to lower these instructions. Currently, only provided
1550// as inline assembler-supported instructions.
1551let Predicates = [HasUMAC_SMAC], Defs = [Y, ASR18], Uses = [Y, ASR18] in {
1552  def SMACrr :  F3_1<2, 0b111111,
1553                   (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1554                   "smac $rs1, $rs2, $rd",
1555                   [], IIC_smac_umac>;
1556
1557  def SMACri :  F3_2<2, 0b111111,
1558                  (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1559                   "smac $rs1, $simm13, $rd",
1560                   [], IIC_smac_umac>;
1561
1562  def UMACrr :  F3_1<2, 0b111110,
1563                  (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2, ASRRegs:$asr18),
1564                   "umac $rs1, $rs2, $rd",
1565                   [], IIC_smac_umac>;
1566
1567  def UMACri :  F3_2<2, 0b111110,
1568                  (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13, ASRRegs:$asr18),
1569                   "umac $rs1, $simm13, $rd",
1570                   [], IIC_smac_umac>;
1571}
1572
1573// The partial write WRPSR instruction has a non-zero destination
1574// register value to separate it from the standard instruction.
1575let Predicates = [HasPWRPSR], Defs = [PSR], rd=1 in {
1576  def PWRPSRrr : F3_1<2, 0b110001,
1577     (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1578     "pwr $rs1, $rs2, %psr", []>;
1579  def PWRPSRri : F3_2<2, 0b110001,
1580     (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
1581     "pwr $rs1, $simm13, %psr", []>;
1582}
1583
1584let Defs = [ICC] in {
1585defm TADDCC   : F3_12np<"taddcc",   0b100000>;
1586defm TSUBCC   : F3_12np<"tsubcc",   0b100001>;
1587
1588let hasSideEffects = 1 in {
1589  defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1590  defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1591}
1592}
1593
1594
1595// Section A.43 - Read Privileged Register Instructions
1596let Predicates = [HasV9] in {
1597let rs2 = 0 in
1598  def RDPR : F3_1<2, 0b101010,
1599                 (outs IntRegs:$rd), (ins PRRegs:$rs1),
1600                 "rdpr $rs1, $rd", []>;
1601}
1602
1603// Section A.62 - Write Privileged Register Instructions
1604let Predicates = [HasV9] in {
1605  def WRPRrr : F3_1<2, 0b110010,
1606                   (outs PRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1607                   "wrpr $rs1, $rs2, $rd", []>;
1608  def WRPRri : F3_2<2, 0b110010,
1609                   (outs PRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
1610                   "wrpr $rs1, $simm13, $rd", []>;
1611}
1612
1613//===----------------------------------------------------------------------===//
1614// Non-Instruction Patterns
1615//===----------------------------------------------------------------------===//
1616
1617// Zero immediate.
1618def : Pat<(i32 0),
1619          (ORrr (i32 G0), (i32 G0))>;
1620// Small immediates.
1621def : Pat<(i32 simm13:$val),
1622          (ORri (i32 G0), imm:$val)>;
1623// Arbitrary immediates.
1624def : Pat<(i32 imm:$val),
1625          (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1626
1627
1628// Global addresses, constant pool entries
1629let Predicates = [Is32Bit] in {
1630
1631def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1632def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1633def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1634def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1635
1636// GlobalTLS addresses
1637def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1638def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1639def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1640          (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1641def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1642          (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1643
1644// Blockaddress
1645def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1646def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1647
1648// Add reg, lo.  This is used when taking the addr of a global/constpool entry.
1649def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1650def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)),  (ADDri $r, tconstpool:$in)>;
1651def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1652                        (ADDri $r, tblockaddress:$in)>;
1653}
1654
1655// Calls:
1656def : Pat<(call tglobaladdr:$dst),
1657          (CALL tglobaladdr:$dst)>;
1658def : Pat<(call texternalsym:$dst),
1659          (CALL texternalsym:$dst)>;
1660
1661// Map integer extload's to zextloads.
1662def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1663def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1664def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1665def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1666def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1667def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1668
1669// zextload bool -> zextload byte
1670def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1671def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1672
1673// store 0, addr -> store %g0, addr
1674def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1675def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1676
1677// store bar for all atomic_fence in V8.
1678let Predicates = [HasNoV9] in
1679  def : Pat<(atomic_fence imm, imm), (STBAR)>;
1680
1681// atomic_load addr -> load addr
1682def : Pat<(i32 (atomic_load_8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1683def : Pat<(i32 (atomic_load_8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1684def : Pat<(i32 (atomic_load_16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1685def : Pat<(i32 (atomic_load_16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1686def : Pat<(i32 (atomic_load_32 ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1687def : Pat<(i32 (atomic_load_32 ADDRri:$src)), (LDri ADDRri:$src)>;
1688
1689// atomic_store val, addr -> store val, addr
1690def : Pat<(atomic_store_8 ADDRrr:$dst, i32:$val), (STBrr ADDRrr:$dst, $val)>;
1691def : Pat<(atomic_store_8 ADDRri:$dst, i32:$val), (STBri ADDRri:$dst, $val)>;
1692def : Pat<(atomic_store_16 ADDRrr:$dst, i32:$val), (STHrr ADDRrr:$dst, $val)>;
1693def : Pat<(atomic_store_16 ADDRri:$dst, i32:$val), (STHri ADDRri:$dst, $val)>;
1694def : Pat<(atomic_store_32 ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1695def : Pat<(atomic_store_32 ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1696
1697// extract_vector
1698def : Pat<(extractelt (v2i32 IntPair:$Rn), 0),
1699          (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
1700def : Pat<(extractelt (v2i32 IntPair:$Rn), 1),
1701          (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
1702
1703// build_vector
1704def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1705          (INSERT_SUBREG
1706	    (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1707            (i32 IntRegs:$a2), sub_odd)>;
1708
1709
1710include "SparcInstr64Bit.td"
1711include "SparcInstrVIS.td"
1712include "SparcInstrAliases.td"
1713