1*0b57cec5SDimitry Andric //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric // 9*0b57cec5SDimitry Andric // This file contains the Sparc implementation of the TargetInstrInfo class. 10*0b57cec5SDimitry Andric // 11*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 12*0b57cec5SDimitry Andric 13*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H 14*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andric #include "SparcRegisterInfo.h" 17*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 20*0b57cec5SDimitry Andric #include "SparcGenInstrInfo.inc" 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric namespace llvm { 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric class SparcSubtarget; 25*0b57cec5SDimitry Andric 26*0b57cec5SDimitry Andric /// SPII - This namespace holds all of the target specific flags that 27*0b57cec5SDimitry Andric /// instruction info tracks. 28*0b57cec5SDimitry Andric /// 29*0b57cec5SDimitry Andric namespace SPII { 30*0b57cec5SDimitry Andric enum { 31*0b57cec5SDimitry Andric Pseudo = (1<<0), 32*0b57cec5SDimitry Andric Load = (1<<1), 33*0b57cec5SDimitry Andric Store = (1<<2), 34*0b57cec5SDimitry Andric DelaySlot = (1<<3) 35*0b57cec5SDimitry Andric }; 36*0b57cec5SDimitry Andric } 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric class SparcInstrInfo : public SparcGenInstrInfo { 39*0b57cec5SDimitry Andric const SparcRegisterInfo RI; 40*0b57cec5SDimitry Andric const SparcSubtarget& Subtarget; 41*0b57cec5SDimitry Andric virtual void anchor(); 42*0b57cec5SDimitry Andric public: 43*0b57cec5SDimitry Andric explicit SparcInstrInfo(SparcSubtarget &ST); 44*0b57cec5SDimitry Andric 45*0b57cec5SDimitry Andric /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 46*0b57cec5SDimitry Andric /// such, whenever a client has an instance of instruction info, it should 47*0b57cec5SDimitry Andric /// always be able to get register info as well (through this method). 48*0b57cec5SDimitry Andric /// 49*0b57cec5SDimitry Andric const SparcRegisterInfo &getRegisterInfo() const { return RI; } 50*0b57cec5SDimitry Andric 51*0b57cec5SDimitry Andric /// isLoadFromStackSlot - If the specified machine instruction is a direct 52*0b57cec5SDimitry Andric /// load from a stack slot, return the virtual or physical register number of 53*0b57cec5SDimitry Andric /// the destination along with the FrameIndex of the loaded stack slot. If 54*0b57cec5SDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 55*0b57cec5SDimitry Andric /// any side effects other than loading from the stack slot. 56*0b57cec5SDimitry Andric unsigned isLoadFromStackSlot(const MachineInstr &MI, 57*0b57cec5SDimitry Andric int &FrameIndex) const override; 58*0b57cec5SDimitry Andric 59*0b57cec5SDimitry Andric /// isStoreToStackSlot - If the specified machine instruction is a direct 60*0b57cec5SDimitry Andric /// store to a stack slot, return the virtual or physical register number of 61*0b57cec5SDimitry Andric /// the source reg along with the FrameIndex of the loaded stack slot. If 62*0b57cec5SDimitry Andric /// not, return 0. This predicate must return 0 if the instruction has 63*0b57cec5SDimitry Andric /// any side effects other than storing to the stack slot. 64*0b57cec5SDimitry Andric unsigned isStoreToStackSlot(const MachineInstr &MI, 65*0b57cec5SDimitry Andric int &FrameIndex) const override; 66*0b57cec5SDimitry Andric 67*0b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 68*0b57cec5SDimitry Andric MachineBasicBlock *&FBB, 69*0b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 70*0b57cec5SDimitry Andric bool AllowModify = false) const override; 71*0b57cec5SDimitry Andric 72*0b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 73*0b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 74*0b57cec5SDimitry Andric 75*0b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 76*0b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 77*0b57cec5SDimitry Andric const DebugLoc &DL, 78*0b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 79*0b57cec5SDimitry Andric 80*0b57cec5SDimitry Andric bool 81*0b57cec5SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 82*0b57cec5SDimitry Andric 83*0b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 84*0b57cec5SDimitry Andric const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 85*0b57cec5SDimitry Andric bool KillSrc) const override; 86*0b57cec5SDimitry Andric 87*0b57cec5SDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 88*0b57cec5SDimitry Andric MachineBasicBlock::iterator MBBI, 89*0b57cec5SDimitry Andric unsigned SrcReg, bool isKill, int FrameIndex, 90*0b57cec5SDimitry Andric const TargetRegisterClass *RC, 91*0b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 92*0b57cec5SDimitry Andric 93*0b57cec5SDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 94*0b57cec5SDimitry Andric MachineBasicBlock::iterator MBBI, 95*0b57cec5SDimitry Andric unsigned DestReg, int FrameIndex, 96*0b57cec5SDimitry Andric const TargetRegisterClass *RC, 97*0b57cec5SDimitry Andric const TargetRegisterInfo *TRI) const override; 98*0b57cec5SDimitry Andric 99*0b57cec5SDimitry Andric unsigned getGlobalBaseReg(MachineFunction *MF) const; 100*0b57cec5SDimitry Andric 101*0b57cec5SDimitry Andric // Lower pseudo instructions after register allocation. 102*0b57cec5SDimitry Andric bool expandPostRAPseudo(MachineInstr &MI) const override; 103*0b57cec5SDimitry Andric }; 104*0b57cec5SDimitry Andric 105*0b57cec5SDimitry Andric } 106*0b57cec5SDimitry Andric 107*0b57cec5SDimitry Andric #endif 108