1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern, 10 InstrItinClass itin = NoItinerary> 11 : Instruction { 12 field bits<32> Inst; 13 14 let Namespace = "SP"; 15 let Size = 4; 16 17 bits<2> op; 18 let Inst{31-30} = op; // Top two bits are the 'op' field 19 20 dag OutOperandList = outs; 21 dag InOperandList = ins; 22 let AsmString = asmstr; 23 let Pattern = pattern; 24 25 let DecoderNamespace = "Sparc"; 26 field bits<32> SoftFail = 0; 27 28 let Itinerary = itin; 29} 30 31//===----------------------------------------------------------------------===// 32// Format #2 instruction classes in the Sparc 33//===----------------------------------------------------------------------===// 34 35// Format 2 instructions 36class F2<dag outs, dag ins, string asmstr, list<dag> pattern, 37 InstrItinClass itin = NoItinerary> 38 : InstSP<outs, ins, asmstr, pattern, itin> { 39 bits<3> op2; 40 bits<22> imm22; 41 let op = 0; // op = 0 42 let Inst{24-22} = op2; 43 let Inst{21-0} = imm22; 44} 45 46// Specific F2 classes: SparcV8 manual, page 44 47// 48class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern, 49 InstrItinClass itin = NoItinerary> 50 : F2<outs, ins, asmstr, pattern, itin> { 51 bits<5> rd; 52 53 let op2 = op2Val; 54 55 let Inst{29-25} = rd; 56} 57 58class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, 59 list<dag> pattern, InstrItinClass itin = NoItinerary> 60 : F2<outs, ins, asmstr, pattern, itin> { 61 bits<4> cond; 62 let op2 = op2Val; 63 64 let Inst{29} = annul; 65 let Inst{28-25} = cond; 66} 67 68class F2_3<bits<3> op2Val, bit annul, bit pred, 69 dag outs, dag ins, string asmstr, list<dag> pattern, 70 InstrItinClass itin = NoItinerary> 71 : InstSP<outs, ins, asmstr, pattern, itin> { 72 bits<2> cc; 73 bits<4> cond; 74 bits<19> imm19; 75 76 let op = 0; // op = 0 77 78 let Inst{29} = annul; 79 let Inst{28-25} = cond; 80 let Inst{24-22} = op2Val; 81 let Inst{21-20} = cc; 82 let Inst{19} = pred; 83 let Inst{18-0} = imm19; 84} 85 86class F2_4<bit annul, bit pred, dag outs, dag ins, 87 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 88 : InstSP<outs, ins, asmstr, pattern, itin> { 89 bits<16> imm16; 90 bits<5> rs1; 91 bits<3> rcond; 92 93 let op = 0; // op = 0 94 95 let Inst{29} = annul; 96 let Inst{28} = 0; 97 let Inst{27-25} = rcond; 98 let Inst{24-22} = 0b011; 99 let Inst{21-20} = imm16{15-14}; 100 let Inst{19} = pred; 101 let Inst{18-14} = rs1; 102 let Inst{13-0} = imm16{13-0}; 103} 104 105 106//===----------------------------------------------------------------------===// 107// Format #3 instruction classes in the Sparc 108//===----------------------------------------------------------------------===// 109 110class F3<dag outs, dag ins, string asmstr, list<dag> pattern, 111 InstrItinClass itin = NoItinerary> 112 : InstSP<outs, ins, asmstr, pattern, itin> { 113 bits<5> rd; 114 bits<6> op3; 115 bits<5> rs1; 116 let op{1} = 1; // Op = 2 or 3 117 let Inst{29-25} = rd; 118 let Inst{24-19} = op3; 119 let Inst{18-14} = rs1; 120} 121 122// Specific F3 classes: SparcV8 manual, page 44 123// 124class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 125 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 126 : F3<outs, ins, asmstr, pattern, itin> { 127 bits<8> asi; 128 bits<5> rs2; 129 130 let op = opVal; 131 let op3 = op3val; 132 133 let Inst{13} = 0; // i field = 0 134 let Inst{12-5} = asi; // address space identifier 135 let Inst{4-0} = rs2; 136} 137 138// CAS instructions does not use an immediate even when i=1 139class F3_1_cas_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 140 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 141 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> { 142 let asi = 0; 143 let Inst{13} = 1; // i field = 1 144} 145 146class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 147 list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 148 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> { 149 let asi = 0; 150} 151 152class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 153 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 154 : F3<outs, ins, asmstr, pattern, itin> { 155 bits<13> simm13; 156 157 let op = opVal; 158 let op3 = op3val; 159 160 let Inst{13} = 1; // i field = 1 161 let Inst{12-0} = simm13; 162} 163 164// floating-point 165class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 166 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 167 : F3<outs, ins, asmstr, pattern, itin> { 168 bits<5> rs2; 169 170 let op = opVal; 171 let op3 = op3val; 172 173 let Inst{13-5} = opfval; // fp opcode 174 let Inst{4-0} = rs2; 175} 176 177// floating-point unary operations. 178class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 179 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 180 : F3<outs, ins, asmstr, pattern, itin> { 181 bits<5> rs2; 182 183 let op = opVal; 184 let op3 = op3val; 185 let rs1 = 0; 186 187 let Inst{13-5} = opfval; // fp opcode 188 let Inst{4-0} = rs2; 189} 190 191// floating-point compares. 192class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 193 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 194 : F3<outs, ins, asmstr, pattern, itin> { 195 bits<5> rs2; 196 197 let op = opVal; 198 let op3 = op3val; 199 200 let Inst{13-5} = opfval; // fp opcode 201 let Inst{4-0} = rs2; 202} 203 204// Shift by register rs2. 205class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 206 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 207 : F3<outs, ins, asmstr, pattern, itin> { 208 bit x = xVal; // 1 for 64-bit shifts. 209 bits<5> rs2; 210 211 let op = opVal; 212 let op3 = op3val; 213 214 let Inst{13} = 0; // i field = 0 215 let Inst{12} = x; // extended registers. 216 let Inst{4-0} = rs2; 217} 218 219// Shift by immediate. 220class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 221 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 222 : F3<outs, ins, asmstr, pattern, itin> { 223 bit x = xVal; // 1 for 64-bit shifts. 224 bits<6> shcnt; // shcnt32 / shcnt64. 225 226 let op = opVal; 227 let op3 = op3val; 228 229 let Inst{13} = 1; // i field = 1 230 let Inst{12} = x; // extended registers. 231 let Inst{5-0} = shcnt; 232} 233 234// Define rr and ri shift instructions with patterns. 235multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 236 ValueType VT, Operand SIT, RegisterClass RC, 237 InstrItinClass itin = IIC_iu_instr> { 238 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 239 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 240 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], 241 itin>; 242 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, SIT:$shcnt), 243 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 244 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))], 245 itin>; 246} 247 248class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern, 249 InstrItinClass itin = NoItinerary> 250 : InstSP<outs, ins, asmstr, pattern, itin> { 251 bits<5> rd; 252 253 let op = 2; 254 let Inst{29-25} = rd; 255 let Inst{24-19} = op3; 256} 257 258 259class F4_1<bits<6> op3, dag outs, dag ins, 260 string asmstr, list<dag> pattern, 261 InstrItinClass itin = NoItinerary> 262 : F4<op3, outs, ins, asmstr, pattern, itin> { 263 bit intcc; 264 bits<2> cc; 265 bits<4> cond; 266 bits<5> rs2; 267 268 let Inst{4-0} = rs2; 269 let Inst{12-11} = cc; 270 let Inst{13} = 0; 271 let Inst{17-14} = cond; 272 let Inst{18} = intcc; 273} 274 275class F4_2<bits<6> op3, dag outs, dag ins, 276 string asmstr, list<dag> pattern, 277 InstrItinClass itin = NoItinerary> 278 : F4<op3, outs, ins, asmstr, pattern, itin> { 279 bit intcc; 280 bits<2> cc; 281 bits<4> cond; 282 bits<11> simm11; 283 284 let Inst{10-0} = simm11; 285 let Inst{12-11} = cc; 286 let Inst{13} = 1; 287 let Inst{17-14} = cond; 288 let Inst{18} = intcc; 289} 290 291class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 292 string asmstr, list<dag> pattern, 293 InstrItinClass itin = NoItinerary> 294 : F4<op3, outs, ins, asmstr, pattern, itin> { 295 bits<4> cond; 296 bit intcc; 297 bits<2> opf_cc; 298 bits<5> rs2; 299 300 let Inst{18} = 0; 301 let Inst{17-14} = cond; 302 let Inst{13} = intcc; 303 let Inst{12-11} = opf_cc; 304 let Inst{10-5} = opf_low; 305 let Inst{4-0} = rs2; 306} 307 308class F4_4r<bits<6> op3, bits<5> opf_low, dag outs, dag ins, 309 string asmstr, list<dag> pattern, 310 InstrItinClass itin = NoItinerary> 311 : F4<op3, outs, ins, asmstr, pattern, itin> { 312 bits<5> rs1; 313 bits<5> rs2; 314 bits<3> rcond; 315 let Inst{18-14} = rs1; 316 let Inst{13} = 0; // IsImm 317 let Inst{12-10} = rcond; 318 let Inst{9-5} = opf_low; 319 let Inst{4-0} = rs2; 320} 321 322 323class F4_4i<bits<6> op3, dag outs, dag ins, 324 string asmstr, list<dag> pattern, 325 InstrItinClass itin = NoItinerary> 326 : F4<op3, outs, ins, asmstr, pattern, itin> { 327 bits<5> rs1; 328 bits<10> simm10; 329 bits<3> rcond; 330 let Inst{18-14} = rs1; 331 let Inst{13} = 1; // IsImm 332 let Inst{12-10} = rcond; 333 let Inst{9-0} = simm10; 334} 335 336 337class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, 338 string asmstr, list<dag> pattern, 339 InstrItinClass itin = NoItinerary> 340 : F3<outs, ins, asmstr, pattern, itin> { 341 bits<4> cond; 342 bits<2> cc; 343 344 let op = 0b10; 345 let rd{4} = 0; 346 let rd{3-0} = cond; 347 let op3 = op3Val; 348 let Inst{13} = isimm; 349 let Inst{12-11} = cc; 350 351} 352 353class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, 354 string asmstr, list<dag> pattern, 355 InstrItinClass itin = NoItinerary> 356 : TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> { 357 bits<5> rs2; 358 359 let Inst{10-5} = 0; 360 let Inst{4-0} = rs2; 361} 362 363class TRAPSPri<bits<6> op3Val, dag outs, dag ins, 364 string asmstr, list<dag> pattern, 365 InstrItinClass itin = NoItinerary> 366 : TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> { 367 bits<8> imm; 368 369 let Inst{10-8} = 0; 370 let Inst{7-0} = imm; 371} 372 373// Pseudo-instructions for alternate assembly syntax (never used by codegen). 374// These are aliases that require C++ handling to convert to the target 375// instruction, while InstAliases can be handled directly by tblgen. 376class AsmPseudoInst<dag outs, dag ins, string asm> 377 : InstSP<outs, ins, asm, []> { 378 let isPseudo = 1; 379} 380