1//===-- SparcInstrFormats.td - Sparc Instruction Formats ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern, 10 InstrItinClass itin = NoItinerary> 11 : Instruction { 12 field bits<32> Inst; 13 14 let Namespace = "SP"; 15 let Size = 4; 16 17 bits<2> op; 18 let Inst{31-30} = op; // Top two bits are the 'op' field 19 20 dag OutOperandList = outs; 21 dag InOperandList = ins; 22 let AsmString = asmstr; 23 let Pattern = pattern; 24 25 let DecoderNamespace = "Sparc"; 26 field bits<32> SoftFail = 0; 27 28 let Itinerary = itin; 29} 30 31//===----------------------------------------------------------------------===// 32// Format #2 instruction classes in the Sparc 33//===----------------------------------------------------------------------===// 34 35// Format 2 instructions 36class F2<dag outs, dag ins, string asmstr, list<dag> pattern, 37 InstrItinClass itin = NoItinerary> 38 : InstSP<outs, ins, asmstr, pattern, itin> { 39 bits<3> op2; 40 bits<22> imm22; 41 let op = 0; // op = 0 42 let Inst{24-22} = op2; 43 let Inst{21-0} = imm22; 44} 45 46// Specific F2 classes: SparcV8 manual, page 44 47// 48class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern, 49 InstrItinClass itin = NoItinerary> 50 : F2<outs, ins, asmstr, pattern, itin> { 51 bits<5> rd; 52 53 let op2 = op2Val; 54 55 let Inst{29-25} = rd; 56} 57 58class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr, 59 list<dag> pattern, InstrItinClass itin = NoItinerary> 60 : F2<outs, ins, asmstr, pattern, itin> { 61 bits<4> cond; 62 let op2 = op2Val; 63 64 let Inst{29} = annul; 65 let Inst{28-25} = cond; 66} 67 68class F2_3<bits<3> op2Val, bit annul, bit pred, 69 dag outs, dag ins, string asmstr, list<dag> pattern, 70 InstrItinClass itin = NoItinerary> 71 : InstSP<outs, ins, asmstr, pattern, itin> { 72 bits<2> cc; 73 bits<4> cond; 74 bits<19> imm19; 75 76 let op = 0; // op = 0 77 78 let Inst{29} = annul; 79 let Inst{28-25} = cond; 80 let Inst{24-22} = op2Val; 81 let Inst{21-20} = cc; 82 let Inst{19} = pred; 83 let Inst{18-0} = imm19; 84} 85 86class F2_4<bits<3> cond, bit annul, bit pred, dag outs, dag ins, 87 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 88 : InstSP<outs, ins, asmstr, pattern, itin> { 89 bits<16> imm16; 90 bits<5> rs1; 91 92 let op = 0; // op = 0 93 94 let Inst{29} = annul; 95 let Inst{28} = 0; 96 let Inst{27-25} = cond; 97 let Inst{24-22} = 0b011; 98 let Inst{21-20} = imm16{15-14}; 99 let Inst{19} = pred; 100 let Inst{18-14} = rs1; 101 let Inst{13-0} = imm16{13-0}; 102} 103 104 105//===----------------------------------------------------------------------===// 106// Format #3 instruction classes in the Sparc 107//===----------------------------------------------------------------------===// 108 109class F3<dag outs, dag ins, string asmstr, list<dag> pattern, 110 InstrItinClass itin = NoItinerary> 111 : InstSP<outs, ins, asmstr, pattern, itin> { 112 bits<5> rd; 113 bits<6> op3; 114 bits<5> rs1; 115 let op{1} = 1; // Op = 2 or 3 116 let Inst{29-25} = rd; 117 let Inst{24-19} = op3; 118 let Inst{18-14} = rs1; 119} 120 121// Specific F3 classes: SparcV8 manual, page 44 122// 123class F3_1_asi<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 124 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 125 : F3<outs, ins, asmstr, pattern, itin> { 126 bits<8> asi; 127 bits<5> rs2; 128 129 let op = opVal; 130 let op3 = op3val; 131 132 let Inst{13} = 0; // i field = 0 133 let Inst{12-5} = asi; // address space identifier 134 let Inst{4-0} = rs2; 135} 136 137class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins, string asmstr, 138 list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 139 : F3_1_asi<opVal, op3val, outs, ins, asmstr, pattern, itin> { 140 let asi = 0; 141} 142 143class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins, 144 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 145 : F3<outs, ins, asmstr, pattern, itin> { 146 bits<13> simm13; 147 148 let op = opVal; 149 let op3 = op3val; 150 151 let Inst{13} = 1; // i field = 1 152 let Inst{12-0} = simm13; 153} 154 155// floating-point 156class F3_3<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 157 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 158 : F3<outs, ins, asmstr, pattern, itin> { 159 bits<5> rs2; 160 161 let op = opVal; 162 let op3 = op3val; 163 164 let Inst{13-5} = opfval; // fp opcode 165 let Inst{4-0} = rs2; 166} 167 168// floating-point unary operations. 169class F3_3u<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 170 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 171 : F3<outs, ins, asmstr, pattern, itin> { 172 bits<5> rs2; 173 174 let op = opVal; 175 let op3 = op3val; 176 let rs1 = 0; 177 178 let Inst{13-5} = opfval; // fp opcode 179 let Inst{4-0} = rs2; 180} 181 182// floating-point compares. 183class F3_3c<bits<2> opVal, bits<6> op3val, bits<9> opfval, dag outs, dag ins, 184 string asmstr, list<dag> pattern, InstrItinClass itin = NoItinerary> 185 : F3<outs, ins, asmstr, pattern, itin> { 186 bits<5> rs2; 187 188 let op = opVal; 189 let op3 = op3val; 190 191 let Inst{13-5} = opfval; // fp opcode 192 let Inst{4-0} = rs2; 193} 194 195// Shift by register rs2. 196class F3_Sr<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 197 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 198 : F3<outs, ins, asmstr, pattern, itin> { 199 bit x = xVal; // 1 for 64-bit shifts. 200 bits<5> rs2; 201 202 let op = opVal; 203 let op3 = op3val; 204 205 let Inst{13} = 0; // i field = 0 206 let Inst{12} = x; // extended registers. 207 let Inst{4-0} = rs2; 208} 209 210// Shift by immediate. 211class F3_Si<bits<2> opVal, bits<6> op3val, bit xVal, dag outs, dag ins, 212 string asmstr, list<dag> pattern, InstrItinClass itin = IIC_iu_instr> 213 : F3<outs, ins, asmstr, pattern, itin> { 214 bit x = xVal; // 1 for 64-bit shifts. 215 bits<6> shcnt; // shcnt32 / shcnt64. 216 217 let op = opVal; 218 let op3 = op3val; 219 220 let Inst{13} = 1; // i field = 1 221 let Inst{12} = x; // extended registers. 222 let Inst{5-0} = shcnt; 223} 224 225// Define rr and ri shift instructions with patterns. 226multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode, 227 ValueType VT, RegisterClass RC, 228 InstrItinClass itin = IIC_iu_instr> { 229 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2), 230 !strconcat(OpcStr, " $rs1, $rs2, $rd"), 231 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))], 232 itin>; 233 def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt), 234 !strconcat(OpcStr, " $rs1, $shcnt, $rd"), 235 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))], 236 itin>; 237} 238 239class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern, 240 InstrItinClass itin = NoItinerary> 241 : InstSP<outs, ins, asmstr, pattern, itin> { 242 bits<5> rd; 243 244 let op = 2; 245 let Inst{29-25} = rd; 246 let Inst{24-19} = op3; 247} 248 249 250class F4_1<bits<6> op3, dag outs, dag ins, 251 string asmstr, list<dag> pattern, 252 InstrItinClass itin = NoItinerary> 253 : F4<op3, outs, ins, asmstr, pattern, itin> { 254 bit intcc; 255 bits<2> cc; 256 bits<4> cond; 257 bits<5> rs2; 258 259 let Inst{4-0} = rs2; 260 let Inst{12-11} = cc; 261 let Inst{13} = 0; 262 let Inst{17-14} = cond; 263 let Inst{18} = intcc; 264} 265 266class F4_2<bits<6> op3, dag outs, dag ins, 267 string asmstr, list<dag> pattern, 268 InstrItinClass itin = NoItinerary> 269 : F4<op3, outs, ins, asmstr, pattern, itin> { 270 bit intcc; 271 bits<2> cc; 272 bits<4> cond; 273 bits<11> simm11; 274 275 let Inst{10-0} = simm11; 276 let Inst{12-11} = cc; 277 let Inst{13} = 1; 278 let Inst{17-14} = cond; 279 let Inst{18} = intcc; 280} 281 282class F4_3<bits<6> op3, bits<6> opf_low, dag outs, dag ins, 283 string asmstr, list<dag> pattern, 284 InstrItinClass itin = NoItinerary> 285 : F4<op3, outs, ins, asmstr, pattern, itin> { 286 bits<4> cond; 287 bit intcc; 288 bits<2> opf_cc; 289 bits<5> rs2; 290 291 let Inst{18} = 0; 292 let Inst{17-14} = cond; 293 let Inst{13} = intcc; 294 let Inst{12-11} = opf_cc; 295 let Inst{10-5} = opf_low; 296 let Inst{4-0} = rs2; 297} 298 299class F4_4r<bits<6> op3, bits<5> opf_low, bits<3> rcond, dag outs, dag ins, 300 string asmstr, list<dag> pattern, 301 InstrItinClass itin = NoItinerary> 302 : F4<op3, outs, ins, asmstr, pattern, itin> { 303 bits <5> rs1; 304 bits <5> rs2; 305 let Inst{18-14} = rs1; 306 let Inst{13} = 0; // IsImm 307 let Inst{12-10} = rcond; 308 let Inst{9-5} = opf_low; 309 let Inst{4-0} = rs2; 310} 311 312 313class F4_4i<bits<6> op3, bits<3> rcond, dag outs, dag ins, 314 string asmstr, list<dag> pattern, 315 InstrItinClass itin = NoItinerary> 316 : F4<op3, outs, ins, asmstr, pattern, itin> { 317 bits<5> rs1; 318 bits<10> simm10; 319 let Inst{18-14} = rs1; 320 let Inst{13} = 1; // IsImm 321 let Inst{12-10} = rcond; 322 let Inst{9-0} = simm10; 323} 324 325 326class TRAPSP<bits<6> op3Val, bit isimm, dag outs, dag ins, 327 string asmstr, list<dag> pattern, 328 InstrItinClass itin = NoItinerary> 329 : F3<outs, ins, asmstr, pattern, itin> { 330 bits<4> cond; 331 bits<2> cc; 332 333 let op = 0b10; 334 let rd{4} = 0; 335 let rd{3-0} = cond; 336 let op3 = op3Val; 337 let Inst{13} = isimm; 338 let Inst{12-11} = cc; 339 340} 341 342class TRAPSPrr<bits<6> op3Val, dag outs, dag ins, 343 string asmstr, list<dag> pattern, 344 InstrItinClass itin = NoItinerary> 345 : TRAPSP<op3Val, 0, outs, ins, asmstr, pattern, itin> { 346 bits<5> rs2; 347 348 let Inst{10-5} = 0; 349 let Inst{4-0} = rs2; 350} 351 352class TRAPSPri<bits<6> op3Val, dag outs, dag ins, 353 string asmstr, list<dag> pattern, 354 InstrItinClass itin = NoItinerary> 355 : TRAPSP<op3Val, 1, outs, ins, asmstr, pattern, itin> { 356 bits<8> imm; 357 358 let Inst{10-8} = 0; 359 let Inst{7-0} = imm; 360} 361 362// Pseudo-instructions for alternate assembly syntax (never used by codegen). 363// These are aliases that require C++ handling to convert to the target 364// instruction, while InstAliases can be handled directly by tblgen. 365class AsmPseudoInst<dag outs, dag ins, string asm> 366 : InstSP<outs, ins, asm, []> { 367 let isPseudo = 1; 368} 369