xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrAliases.td (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145) 
1//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains instruction aliases for Sparc.
10//===----------------------------------------------------------------------===//
11
12// Instruction aliases for conditional moves.
13
14// mov<cond> <ccreg> rs2, rd
15multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
16                          Instruction movrr, Instruction movri,
17                          Instruction fmovs, Instruction fmovd> {
18
19  // mov<cond> (%icc|%xcc), rs2, rd
20  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
21                             ", $rs2, $rd"),
22                  (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
23
24  // mov<cond> (%icc|%xcc), simm11, rd
25  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
26                             ", $simm11, $rd"),
27                  (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
28
29  // fmovs<cond> (%icc|%xcc), $rs2, $rd
30  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
31                             ", $rs2, $rd"),
32                  (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
33
34  // fmovd<cond> (%icc|%xcc), $rs2, $rd
35  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
36                             ", $rs2, $rd"),
37                  (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
38}
39
40// mov<cond> <ccreg> rs2, rd
41multiclass fpcond_mov_alias<string cond, int condVal,
42                           Instruction movrr, Instruction movri,
43                           Instruction fmovs, Instruction fmovd> {
44
45  // mov<cond> %fcc[0-3], rs2, rd
46  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
47                  (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
48
49  // mov<cond> %fcc[0-3], simm11, rd
50  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
51                  (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
52
53  // fmovs<cond> %fcc[0-3], $rs2, $rd
54  def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
55                  (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
56
57  // fmovd<cond> %fcc[0-3], $rs2, $rd
58  def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
59                  (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
60}
61
62// movr<cond> rs1, rs2, rd
63multiclass regcond_mov_alias<string rcond, int condVal,
64                          Instruction movrrr, Instruction movrri,
65                          Instruction fmovrs, Instruction fmovrd,
66                          Instruction fmovrq> {
67
68  // movr<cond> $rs1, $rs2, $rd
69  def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $rs2, $rd"),
70                  (movrrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, condVal)>;
71
72  // movr<cond> $rs1, $simm10, $rd
73  def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $simm10, $rd"),
74                  (movrri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, condVal)>;
75
76  // fmovrs<cond> $rs1, $rs2, $rd
77  def : InstAlias<!strconcat(!strconcat("fmovrs", rcond), " $rs1, $rs2, $rd"),
78                  (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
79
80  // fmovrd<cond> $rs1, $rs2, $rd
81  def : InstAlias<!strconcat(!strconcat("fmovrd", rcond), " $rs1, $rs2, $rd"),
82                  (fmovrd DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, condVal)>;
83
84  // fmovrq<cond> $rs1, $rs2, $rd
85  let Predicates = [HasHardQuad] in
86  def : InstAlias<!strconcat(!strconcat("fmovrq", rcond), " $rs1, $rs2, $rd"),
87                  (fmovrq QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, condVal)>;
88}
89
90// Instruction aliases for integer conditional branches and moves.
91multiclass int_cond_alias<string cond, int condVal> {
92
93  // b<cond> $imm
94  def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
95                  (BCOND brtarget:$imm, condVal)>;
96
97  // b<cond>,a $imm
98  def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
99                  (BCONDA brtarget:$imm, condVal)>;
100
101  // b<cond> %icc, $imm
102  def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
103                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
104
105  // b<cond>,pt %icc, $imm
106  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
107                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
108
109  // b<cond>,a %icc, $imm
110  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
111                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
112
113  // b<cond>,a,pt %icc, $imm
114  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
115                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
116
117  // b<cond>,pn %icc, $imm
118  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
119                  (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
120
121  // b<cond>,a,pn %icc, $imm
122  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
123                  (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
124
125  // b<cond> %xcc, $imm
126  def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
127                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
128
129  // b<cond>,pt %xcc, $imm
130  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
131                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
132
133  // b<cond>,a %xcc, $imm
134  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
135                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
136
137  // b<cond>,a,pt %xcc, $imm
138  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
139                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
140
141  // b<cond>,pn %xcc, $imm
142  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
143                  (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
144
145  // b<cond>,a,pn %xcc, $imm
146  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
147                  (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
148
149
150  defm : intcond_mov_alias<cond, condVal, " %icc",
151                            MOVICCrr, MOVICCri,
152                            FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
153
154  defm : intcond_mov_alias<cond, condVal, " %xcc",
155                            MOVXCCrr, MOVXCCri,
156                            FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
157
158  // fmovq<cond> (%icc|%xcc), $rs2, $rd
159  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
160                  (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
161                  Requires<[HasV9, HasHardQuad]>;
162  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
163                  (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
164                  Requires<[Is64Bit, HasHardQuad]>;
165
166  // t<cond> %icc,  rs => t<cond> %icc, G0 + rs
167  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
168                  (TICCrr G0, IntRegs:$rs2, condVal)>,
169                  Requires<[HasV9]>;
170  // t<cond> %icc, rs1 + rs2
171  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
172                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
173                  Requires<[HasV9]>;
174
175
176  // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
177  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
178                  (TXCCrr G0, IntRegs:$rs2, condVal)>,
179                  Requires<[HasV9]>;
180  // t<cond> %xcc, rs1 + rs2
181  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
182                  (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
183                  Requires<[HasV9]>;
184
185
186  // t<cond> rs=> t<cond> %icc,  G0 + rs2
187  //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
188  //                (TICCrr G0, IntRegs:$rs2, condVal)>,
189  //                Requires<[HasV9]>;
190
191  // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
192  //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
193  //                (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
194  //                Requires<[HasV9]>;
195
196  // t<cond> %icc, imm => t<cond> %icc, G0 + imm
197  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
198                  (TICCri G0, i32imm:$imm, condVal)>,
199                  Requires<[HasV9]>;
200  // t<cond> %icc, rs1 + imm
201  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
202                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
203                  Requires<[HasV9]>;
204  // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
205  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
206                  (TXCCri G0, i32imm:$imm, condVal)>,
207                  Requires<[HasV9]>;
208  // t<cond> %xcc, rs1 + imm
209  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
210                  (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
211                  Requires<[HasV9]>;
212
213  // t<cond> imm => t<cond> G0 + imm
214  def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
215                  (TRAPri G0, i32imm:$imm, condVal)>;
216
217  // t<cond> rs1 + imm => t<cond> rs1 + imm
218  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
219                  (TRAPri IntRegs:$rs1, i32imm:$imm, condVal)>;
220
221  // t<cond> rs1 => t<cond> G0 + rs1
222  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1"),
223                  (TRAPrr G0, IntRegs:$rs1, condVal)>;
224
225  // t<cond> rs1 + rs2
226  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
227                  (TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
228}
229
230
231// Instruction aliases for floating point conditional branches and moves.
232multiclass fp_cond_alias<string cond, int condVal> {
233
234  // fb<cond> $imm
235  def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
236                  (FBCOND brtarget:$imm, condVal), 0>;
237
238  // fb<cond>,a $imm
239  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
240                  (FBCONDA brtarget:$imm, condVal), 0>;
241
242  // fb<cond> %fcc0, $imm
243  def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
244                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
245                  Requires<[HasV9]>;
246
247  // fb<cond>,pt %fcc0, $imm
248  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
249                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
250                  Requires<[HasV9]>;
251
252  // fb<cond>,a %fcc0, $imm
253  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
254                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
255                  Requires<[HasV9]>;
256
257  // fb<cond>,a,pt %fcc0, $imm
258  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
259                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
260                   Requires<[HasV9]>;
261
262  // fb<cond>,pn %fcc0, $imm
263  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
264                  (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
265                   Requires<[HasV9]>;
266
267  // fb<cond>,a,pn %fcc0, $imm
268  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
269                  (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
270                  Requires<[HasV9]>;
271
272  defm : fpcond_mov_alias<cond, condVal,
273                          V9MOVFCCrr, V9MOVFCCri,
274                          V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
275
276  // fmovq<cond> %fcc0, $rs2, $rd
277  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
278                  (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
279                                                          condVal)>,
280                  Requires<[HasV9, HasHardQuad]>;
281}
282
283
284// Instruction aliases for co-processor conditional branches.
285multiclass cp_cond_alias<string cond, int condVal> {
286
287  // cb<cond> $imm
288  def : InstAlias<!strconcat(!strconcat("cb", cond), " $imm"),
289                  (CBCOND brtarget:$imm, condVal), 0>;
290
291  // cb<cond>,a $imm
292  def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),
293                  (CBCONDA brtarget:$imm, condVal), 0>;
294}
295
296// Instruction aliases for register conditional branches and moves.
297multiclass reg_cond_alias<string rcond, int condVal> {
298  // br<rcond> $rs1, $imm
299  def : InstAlias<!strconcat(!strconcat("br", rcond), " $rs1, $imm"),
300                  (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,
301                  Requires<[Is64Bit]>;
302
303  // br<rcond>,pt $rs1, $imm
304  def : InstAlias<!strconcat(!strconcat("br", rcond), ",pt $rs1, $imm"),
305                  (BPR bprtarget16:$imm, condVal, I64Regs:$rs1)>,
306                  Requires<[Is64Bit]>;
307
308  // br<rcond>,pn $rs1, $imm
309  def : InstAlias<!strconcat(!strconcat("br", rcond), ",pn $rs1, $imm"),
310                  (BPRNT bprtarget16:$imm, condVal, I64Regs:$rs1)>,
311                  Requires<[Is64Bit]>;
312
313  // br<rcond>,a $rs1, $imm
314  def : InstAlias<!strconcat(!strconcat("br", rcond), ",a $rs1, $imm"),
315                  (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,
316                  Requires<[Is64Bit]>;
317
318  // br<rcond>,a,pt $rs1, $imm
319  def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pt $rs1, $imm"),
320                  (BPRA bprtarget16:$imm, condVal, I64Regs:$rs1)>,
321                  Requires<[Is64Bit]>;
322
323  // br<rcond>,a,pn $rs1, $imm
324  def : InstAlias<!strconcat(!strconcat("br", rcond), ",a,pn $rs1, $imm"),
325                  (BPRANT bprtarget16:$imm, condVal, I64Regs:$rs1)>,
326                  Requires<[Is64Bit]>;
327
328  defm : regcond_mov_alias<rcond, condVal,
329                            MOVRrr, MOVRri,
330                            FMOVRS, FMOVRD, FMOVRQ>,
331                            Requires<[Is64Bit]>;
332}
333
334defm : int_cond_alias<"a",    0b1000>;
335defm : int_cond_alias<"n",    0b0000>;
336defm : int_cond_alias<"ne",   0b1001>;
337defm : int_cond_alias<"e",    0b0001>;
338defm : int_cond_alias<"g",    0b1010>;
339defm : int_cond_alias<"le",   0b0010>;
340defm : int_cond_alias<"ge",   0b1011>;
341defm : int_cond_alias<"l",    0b0011>;
342defm : int_cond_alias<"gu",   0b1100>;
343defm : int_cond_alias<"leu",  0b0100>;
344defm : int_cond_alias<"cc",   0b1101>;
345defm : int_cond_alias<"cs",   0b0101>;
346defm : int_cond_alias<"pos",  0b1110>;
347defm : int_cond_alias<"neg",  0b0110>;
348defm : int_cond_alias<"vc",   0b1111>;
349defm : int_cond_alias<"vs",   0b0111>;
350let EmitPriority = 0 in
351{
352  defm : int_cond_alias<"",     0b1000>; // same as a; gnu asm, not in manual
353  defm : int_cond_alias<"gt",   0b1010>; // same as g; gnu asm, not in manual
354  defm : int_cond_alias<"lt",   0b0011>; // same as l; gnu asm, not in manual
355  defm : int_cond_alias<"nz",   0b1001>; // same as ne
356  defm : int_cond_alias<"eq",   0b0001>; // same as e
357  defm : int_cond_alias<"z",    0b0001>; // same as e
358  defm : int_cond_alias<"geu",  0b1101>; // same as cc
359  defm : int_cond_alias<"lu",   0b0101>; // same as cs
360}
361defm : fp_cond_alias<"a",     0b1000>;
362defm : fp_cond_alias<"n",     0b0000>;
363defm : fp_cond_alias<"u",     0b0111>;
364defm : fp_cond_alias<"g",     0b0110>;
365defm : fp_cond_alias<"ug",    0b0101>;
366defm : fp_cond_alias<"l",     0b0100>;
367defm : fp_cond_alias<"ul",    0b0011>;
368defm : fp_cond_alias<"lg",    0b0010>;
369defm : fp_cond_alias<"ne",    0b0001>;
370defm : fp_cond_alias<"e",     0b1001>;
371defm : fp_cond_alias<"ue",    0b1010>;
372defm : fp_cond_alias<"ge",    0b1011>;
373defm : fp_cond_alias<"uge",   0b1100>;
374defm : fp_cond_alias<"le",    0b1101>;
375defm : fp_cond_alias<"ule",   0b1110>;
376defm : fp_cond_alias<"o",     0b1111>;
377let EmitPriority = 0 in
378{
379  defm : fp_cond_alias<"",      0b1000>; // same as a; gnu asm, not in manual
380  defm : fp_cond_alias<"nz",    0b0001>; // same as ne
381  defm : fp_cond_alias<"z",     0b1001>; // same as e
382}
383
384defm : cp_cond_alias<"a",     0b1000>;
385defm : cp_cond_alias<"n",     0b0000>;
386defm : cp_cond_alias<"3",     0b0111>;
387defm : cp_cond_alias<"2",     0b0110>;
388defm : cp_cond_alias<"23",    0b0101>;
389defm : cp_cond_alias<"1",     0b0100>;
390defm : cp_cond_alias<"13",    0b0011>;
391defm : cp_cond_alias<"12",    0b0010>;
392defm : cp_cond_alias<"123",   0b0001>;
393defm : cp_cond_alias<"0",     0b1001>;
394defm : cp_cond_alias<"03",    0b1010>;
395defm : cp_cond_alias<"02",    0b1011>;
396defm : cp_cond_alias<"023",   0b1100>;
397defm : cp_cond_alias<"01",    0b1101>;
398defm : cp_cond_alias<"013",   0b1110>;
399defm : cp_cond_alias<"012",   0b1111>;
400let EmitPriority = 0 in defm : cp_cond_alias<"",      0b1000>; // same as a; gnu asm, not in manual
401
402defm : reg_cond_alias<"z",    0b001>;
403defm : reg_cond_alias<"lez",  0b010>;
404defm : reg_cond_alias<"lz",   0b011>;
405defm : reg_cond_alias<"nz",   0b101>;
406defm : reg_cond_alias<"gz",   0b110>;
407defm : reg_cond_alias<"gez",  0b111>;
408
409// Section A.3 Synthetic Instructions
410
411// Most are marked as Emit=0, so that they are not used for disassembly. This is
412// an aesthetic issue, but the chosen policy is to typically prefer using the
413// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
414// call, tst, ret, retl.
415
416// Note: jmp/call/ret/retl have special case handling for output in
417//       SparcInstPrinter.cpp
418
419// cmp rs1, reg_or_imm -> subcc rs1, reg_or_imm, %g0
420def : InstAlias<"cmp $rs1, $rs2", (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2)>;
421def : InstAlias<"cmp $rs1, $imm", (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm)>;
422
423// jmp addr -> jmpl addr, %g0
424def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
425def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
426
427// call addr -> jmpl addr, %o7
428def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
429def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
430
431// tst reg -> orcc %g0, reg, %g0
432def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
433
434// ret -> jmpl %i7+8, %g0 (aka RET 8)
435def : InstAlias<"ret", (RET 8)>;
436
437// retl -> jmpl %o7+8, %g0 (aka RETL 8)
438def : InstAlias<"retl", (RETL 8)>;
439
440// restore -> restore %g0, %g0, %g0
441def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
442
443// save -> restore %g0, %g0, %g0
444def : InstAlias<"save", (SAVErr G0, G0, G0)>;
445
446// set value, rd
447// (turns into a sequence of sethi+or, depending on the value)
448// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
449def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
450
451// setx value, tmp, rd
452// (turns into a sequence of sethi+or+shift, depending on the value)
453def SETX : AsmPseudoInst<(outs I64Regs:$rd),
454                         (ins i64imm:$val, I64Regs:$tmp),
455                         "setx $val, $tmp, $rd">,
456                         Requires<[Is64Bit, HasV9]>;
457
458// not rd -> xnor rd, %g0, rd
459def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
460
461// not reg, rd -> xnor reg, %g0, rd
462def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
463
464// neg rd -> sub %g0, rd, rd
465def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
466
467// neg reg, rd -> sub %g0, reg, rd
468def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
469
470let Predicates = [HasV9] in {
471  // cas [rs1], rs2, rd -> casa [rs1] #ASI_P, rs2, rd
472  def : InstAlias<"cas [$rs1], $rs2, $rd",
473                  (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x80)>;
474
475  // casl [rs1], rs2, rd -> casa [rs1] #ASI_P_L, rs2, rd
476  def : InstAlias<"casl [$rs1], $rs2, $rd",
477                  (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 0x88)>;
478
479  // casx [rs1], rs2, rd -> casxa [rs1] #ASI_P, rs2, rd
480  def : InstAlias<"casx [$rs1], $rs2, $rd",
481                  (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x80)>;
482
483  // casxl [rs1], rs2, rd -> casxa [rs1] #ASI_P_L, rs2, rd
484  def : InstAlias<"casxl [$rs1], $rs2, $rd",
485                  (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 0x88)>;
486}
487
488// inc rd -> add rd, 1, rd
489def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
490
491// inc simm13, rd -> add rd, simm13, rd
492def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
493
494// inccc rd -> addcc rd, 1, rd
495def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
496
497// inccc simm13, rd -> addcc rd, simm13, rd
498def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
499
500// dec rd -> sub rd, 1, rd
501def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
502
503// dec simm13, rd -> sub rd, simm13, rd
504def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
505
506// deccc rd -> subcc rd, 1, rd
507def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
508
509// deccc simm13, rd -> subcc rd, simm13, rd
510def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
511
512// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
513def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
514def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, simm13Op:$simm13), 0>;
515
516// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
517def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
518def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
519
520// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
521def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
522def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
523
524// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
525def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
526def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, simm13Op:$simm13), 0>;
527
528
529// clr rd -> or %g0, %g0, rd
530def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
531
532// clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
533def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
534def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
535def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
536def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
537def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
538def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
539
540
541// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
542def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
543def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, simm13Op:$simm13)>;
544
545// mov specialreg, rd -> rd specialreg, rd
546def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
547def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
548def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
549def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
550
551// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
552def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
553def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
554def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
555def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;
556def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
557def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;
558def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
559def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;
560
561// End of Section A.3
562
563// or imm, reg, rd -> or reg, imm, rd
564// Nonstandard GNU extension.
565let EmitPriority = 0 in
566  def : InstAlias<"or $simm13, $rs1, $rd", (ORri IntRegs:$rd, IntRegs:$rs1, simm13Op:$simm13)>;
567
568// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
569// (aka: omit the first arg when it's g0. This is not in the manual, but is
570// supported by gnu and solaris as)
571def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
572def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, simm13Op:$simm13), 0>;
573def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
574def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, simm13Op:$simm13), 0>;
575def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
576def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, simm13Op:$simm13), 0>;
577def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
578def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, simm13Op:$simm13), 0>;
579
580def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
581def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, simm13Op:$simm13), 0>;
582
583// wrpr %reg, %rd -> wrpr %reg, %g0, %rd
584// wrpr  imm, %rd -> wrpr  %g0, imm, %rd
585// Nonstandard GNU extensions.
586let Predicates = [HasV9] in {
587  def : InstAlias<"wrpr $rs1, $rd", (WRPRrr PRRegs:$rd, IntRegs:$rs1, G0), 0>;
588  def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, simm13Op:$simm13), 0>;
589}
590
591// flush -> flush %g0
592def : InstAlias<"flush", (FLUSH), 0>;
593
594// unimp -> unimp 0
595def : InstAlias<"unimp", (UNIMP 0), 0>;
596
597def : MnemonicAlias<"iflush", "flush">;
598
599def : MnemonicAlias<"stub", "stb">;
600def : MnemonicAlias<"stsb", "stb">;
601
602def : MnemonicAlias<"stuba", "stba">;
603def : MnemonicAlias<"stsba", "stba">;
604
605def : MnemonicAlias<"stuh", "sth">;
606def : MnemonicAlias<"stsh", "sth">;
607
608def : MnemonicAlias<"stuha", "stha">;
609def : MnemonicAlias<"stsha", "stha">;
610
611def : MnemonicAlias<"stw", "st">, Requires<[HasV9]>;
612def : MnemonicAlias<"stuw", "st">, Requires<[HasV9]>;
613def : MnemonicAlias<"stsw", "st">, Requires<[HasV9]>;
614
615def : MnemonicAlias<"stwa", "sta">, Requires<[HasV9]>;
616def : MnemonicAlias<"stuwa", "sta">, Requires<[HasV9]>;
617def : MnemonicAlias<"stswa", "sta">, Requires<[HasV9]>;
618
619def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;
620def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
621
622def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
623
624def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
625def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
626
627def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
628def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
629
630
631def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
632def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
633def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
634                Requires<[HasHardQuad]>;
635
636def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
637def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
638                                                     DFPRegs:$rs2)>;
639def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
640                                                     QFPRegs:$rs2)>,
641                Requires<[HasHardQuad]>;
642
643// signx rd -> sra rd, %g0, rd
644def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
645
646// signx reg, rd -> sra reg, %g0, rd
647def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
648
649// sir -> sir 0
650def : InstAlias<"sir", (SIR 0), 0>;
651