xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrAliases.td (revision 9e5787d2284e187abb5b654d924394a65772e004) 
1//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains instruction aliases for Sparc.
10//===----------------------------------------------------------------------===//
11
12// Instruction aliases for conditional moves.
13
14// mov<cond> <ccreg> rs2, rd
15multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
16                          Instruction movrr, Instruction movri,
17                          Instruction fmovs, Instruction fmovd> {
18
19  // mov<cond> (%icc|%xcc), rs2, rd
20  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
21                             ", $rs2, $rd"),
22                  (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
23
24  // mov<cond> (%icc|%xcc), simm11, rd
25  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
26                             ", $simm11, $rd"),
27                  (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
28
29  // fmovs<cond> (%icc|%xcc), $rs2, $rd
30  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
31                             ", $rs2, $rd"),
32                  (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
33
34  // fmovd<cond> (%icc|%xcc), $rs2, $rd
35  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
36                             ", $rs2, $rd"),
37                  (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
38}
39
40// mov<cond> <ccreg> rs2, rd
41multiclass fpcond_mov_alias<string cond, int condVal,
42                           Instruction movrr, Instruction movri,
43                           Instruction fmovs, Instruction fmovd> {
44
45  // mov<cond> %fcc[0-3], rs2, rd
46  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
47                  (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
48
49  // mov<cond> %fcc[0-3], simm11, rd
50  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
51                  (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
52
53  // fmovs<cond> %fcc[0-3], $rs2, $rd
54  def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
55                  (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
56
57  // fmovd<cond> %fcc[0-3], $rs2, $rd
58  def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
59                  (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
60}
61
62// Instruction aliases for integer conditional branches and moves.
63multiclass int_cond_alias<string cond, int condVal> {
64
65  // b<cond> $imm
66  def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
67                  (BCOND brtarget:$imm, condVal)>;
68
69  // b<cond>,a $imm
70  def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
71                  (BCONDA brtarget:$imm, condVal)>;
72
73  // b<cond> %icc, $imm
74  def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
75                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
76
77  // b<cond>,pt %icc, $imm
78  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
79                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80
81  // b<cond>,a %icc, $imm
82  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
83                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
84
85  // b<cond>,a,pt %icc, $imm
86  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
87                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88
89  // b<cond>,pn %icc, $imm
90  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
91                  (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
92
93  // b<cond>,a,pn %icc, $imm
94  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
95                  (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96
97  // b<cond> %xcc, $imm
98  def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
99                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
100
101  // b<cond>,pt %xcc, $imm
102  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
103                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104
105  // b<cond>,a %xcc, $imm
106  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
107                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
108
109  // b<cond>,a,pt %xcc, $imm
110  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
111                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
112
113  // b<cond>,pn %xcc, $imm
114  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
115                  (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
116
117  // b<cond>,a,pn %xcc, $imm
118  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
119                  (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
120
121
122  defm : intcond_mov_alias<cond, condVal, " %icc",
123                            MOVICCrr, MOVICCri,
124                            FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
125
126  defm : intcond_mov_alias<cond, condVal, " %xcc",
127                            MOVXCCrr, MOVXCCri,
128                            FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
129
130  // fmovq<cond> (%icc|%xcc), $rs2, $rd
131  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
132                  (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
133                  Requires<[HasV9, HasHardQuad]>;
134  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
135                  (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
136                  Requires<[Is64Bit, HasHardQuad]>;
137
138  // t<cond> %icc,  rs => t<cond> %icc, G0 + rs
139  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
140                  (TICCrr G0, IntRegs:$rs2, condVal)>,
141                  Requires<[HasV9]>;
142  // t<cond> %icc, rs1 + rs2
143  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
144                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
145                  Requires<[HasV9]>;
146
147
148  // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
149  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
150                  (TXCCrr G0, IntRegs:$rs2, condVal)>,
151                  Requires<[HasV9]>;
152  // t<cond> %xcc, rs1 + rs2
153  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
154                  (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
155                  Requires<[HasV9]>;
156
157
158  // t<cond> rs=> t<cond> %icc,  G0 + rs2
159  //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
160  //                (TICCrr G0, IntRegs:$rs2, condVal)>,
161  //                Requires<[HasV9]>;
162
163  // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
164  //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
165  //                (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
166  //                Requires<[HasV9]>;
167
168  // t<cond> %icc, imm => t<cond> %icc, G0 + imm
169  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
170                  (TICCri G0, i32imm:$imm, condVal)>,
171                  Requires<[HasV9]>;
172  // t<cond> %icc, rs1 + imm
173  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
174                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
175                  Requires<[HasV9]>;
176  // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
177  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
178                  (TXCCri G0, i32imm:$imm, condVal)>,
179                  Requires<[HasV9]>;
180  // t<cond> %xcc, rs1 + imm
181  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
182                  (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
183                  Requires<[HasV9]>;
184
185  // t<cond> imm => t<cond> G0 + imm
186  def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
187                  (TRAPri G0, i32imm:$imm, condVal)>;
188
189  // t<cond> rs1 + imm => t<cond> rs1 + imm
190  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
191                  (TRAPri IntRegs:$rs1, i32imm:$imm, condVal)>;
192
193  // t<cond> rs1 => t<cond> G0 + rs1
194  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1"),
195                  (TRAPrr G0, IntRegs:$rs1, condVal)>;
196
197  // t<cond> rs1 + rs2
198  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
199                  (TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
200}
201
202
203// Instruction aliases for floating point conditional branches and moves.
204multiclass fp_cond_alias<string cond, int condVal> {
205
206  // fb<cond> $imm
207  def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
208                  (FBCOND brtarget:$imm, condVal), 0>;
209
210  // fb<cond>,a $imm
211  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
212                  (FBCONDA brtarget:$imm, condVal), 0>;
213
214  // fb<cond> %fcc0, $imm
215  def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
216                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
217                  Requires<[HasV9]>;
218
219  // fb<cond>,pt %fcc0, $imm
220  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
221                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
222                  Requires<[HasV9]>;
223
224  // fb<cond>,a %fcc0, $imm
225  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
226                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
227                  Requires<[HasV9]>;
228
229  // fb<cond>,a,pt %fcc0, $imm
230  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
231                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
232                   Requires<[HasV9]>;
233
234  // fb<cond>,pn %fcc0, $imm
235  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
236                  (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
237                   Requires<[HasV9]>;
238
239  // fb<cond>,a,pn %fcc0, $imm
240  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
241                  (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
242                  Requires<[HasV9]>;
243
244  defm : fpcond_mov_alias<cond, condVal,
245                          V9MOVFCCrr, V9MOVFCCri,
246                          V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
247
248  // fmovq<cond> %fcc0, $rs2, $rd
249  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
250                  (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
251                                                          condVal)>,
252                  Requires<[HasV9, HasHardQuad]>;
253}
254
255
256// Instruction aliases for co-processor conditional branches.
257multiclass cp_cond_alias<string cond, int condVal> {
258
259  // cb<cond> $imm
260  def : InstAlias<!strconcat(!strconcat("cb", cond), " $imm"),
261                  (CBCOND brtarget:$imm, condVal), 0>;
262
263  // cb<cond>,a $imm
264  def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),
265                  (CBCONDA brtarget:$imm, condVal), 0>;
266}
267
268defm : int_cond_alias<"a",    0b1000>;
269defm : int_cond_alias<"n",    0b0000>;
270defm : int_cond_alias<"ne",   0b1001>;
271defm : int_cond_alias<"e",    0b0001>;
272defm : int_cond_alias<"g",    0b1010>;
273defm : int_cond_alias<"le",   0b0010>;
274defm : int_cond_alias<"ge",   0b1011>;
275defm : int_cond_alias<"l",    0b0011>;
276defm : int_cond_alias<"gu",   0b1100>;
277defm : int_cond_alias<"leu",  0b0100>;
278defm : int_cond_alias<"cc",   0b1101>;
279defm : int_cond_alias<"cs",   0b0101>;
280defm : int_cond_alias<"pos",  0b1110>;
281defm : int_cond_alias<"neg",  0b0110>;
282defm : int_cond_alias<"vc",   0b1111>;
283defm : int_cond_alias<"vs",   0b0111>;
284let EmitPriority = 0 in
285{
286  defm : int_cond_alias<"",     0b1000>; // same as a; gnu asm, not in manual
287  defm : int_cond_alias<"nz",   0b1001>; // same as ne
288  defm : int_cond_alias<"eq",   0b0001>; // same as e
289  defm : int_cond_alias<"z",    0b0001>; // same as e
290  defm : int_cond_alias<"geu",  0b1101>; // same as cc
291  defm : int_cond_alias<"lu",   0b0101>; // same as cs
292}
293defm : fp_cond_alias<"a",     0b1000>;
294defm : fp_cond_alias<"n",     0b0000>;
295defm : fp_cond_alias<"u",     0b0111>;
296defm : fp_cond_alias<"g",     0b0110>;
297defm : fp_cond_alias<"ug",    0b0101>;
298defm : fp_cond_alias<"l",     0b0100>;
299defm : fp_cond_alias<"ul",    0b0011>;
300defm : fp_cond_alias<"lg",    0b0010>;
301defm : fp_cond_alias<"ne",    0b0001>;
302defm : fp_cond_alias<"e",     0b1001>;
303defm : fp_cond_alias<"ue",    0b1010>;
304defm : fp_cond_alias<"ge",    0b1011>;
305defm : fp_cond_alias<"uge",   0b1100>;
306defm : fp_cond_alias<"le",    0b1101>;
307defm : fp_cond_alias<"ule",   0b1110>;
308defm : fp_cond_alias<"o",     0b1111>;
309let EmitPriority = 0 in
310{
311  defm : fp_cond_alias<"",      0b1000>; // same as a; gnu asm, not in manual
312  defm : fp_cond_alias<"nz",    0b0001>; // same as ne
313  defm : fp_cond_alias<"z",     0b1001>; // same as e
314}
315
316defm : cp_cond_alias<"a",     0b1000>;
317defm : cp_cond_alias<"n",     0b0000>;
318defm : cp_cond_alias<"3",     0b0111>;
319defm : cp_cond_alias<"2",     0b0110>;
320defm : cp_cond_alias<"23",    0b0101>;
321defm : cp_cond_alias<"1",     0b0100>;
322defm : cp_cond_alias<"13",    0b0011>;
323defm : cp_cond_alias<"12",    0b0010>;
324defm : cp_cond_alias<"123",   0b0001>;
325defm : cp_cond_alias<"0",     0b1001>;
326defm : cp_cond_alias<"03",    0b1010>;
327defm : cp_cond_alias<"02",    0b1011>;
328defm : cp_cond_alias<"023",   0b1100>;
329defm : cp_cond_alias<"01",    0b1101>;
330defm : cp_cond_alias<"013",   0b1110>;
331defm : cp_cond_alias<"012",   0b1111>;
332let EmitPriority = 0 in defm : cp_cond_alias<"",      0b1000>; // same as a; gnu asm, not in manual
333
334// Section A.3 Synthetic Instructions
335
336// Most are marked as Emit=0, so that they are not used for disassembly. This is
337// an aesthetic issue, but the chosen policy is to typically prefer using the
338// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
339// call, tst, ret, retl.
340
341// Note: cmp is handled in SparcInstrInfo.
342//       jmp/call/ret/retl have special case handling for output in
343//       SparcInstPrinter.cpp
344
345// jmp addr -> jmpl addr, %g0
346def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
347def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
348
349// call addr -> jmpl addr, %o7
350def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
351def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
352
353// tst reg -> orcc %g0, reg, %g0
354def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
355
356// ret -> jmpl %i7+8, %g0 (aka RET 8)
357def : InstAlias<"ret", (RET 8)>;
358
359// retl -> jmpl %o7+8, %g0 (aka RETL 8)
360def : InstAlias<"retl", (RETL 8)>;
361
362// restore -> restore %g0, %g0, %g0
363def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
364
365// save -> restore %g0, %g0, %g0
366def : InstAlias<"save", (SAVErr G0, G0, G0)>;
367
368// set value, rd
369// (turns into a sequence of sethi+or, depending on the value)
370// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
371def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
372
373// not rd -> xnor rd, %g0, rd
374def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
375
376// not reg, rd -> xnor reg, %g0, rd
377def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
378
379// neg rd -> sub %g0, rd, rd
380def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
381
382// neg reg, rd -> sub %g0, reg, rd
383def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
384
385// inc rd -> add rd, 1, rd
386def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
387
388// inc simm13, rd -> add rd, simm13, rd
389def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
390
391// inccc rd -> addcc rd, 1, rd
392def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
393
394// inccc simm13, rd -> addcc rd, simm13, rd
395def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
396
397// dec rd -> sub rd, 1, rd
398def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
399
400// dec simm13, rd -> sub rd, simm13, rd
401def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
402
403// deccc rd -> subcc rd, 1, rd
404def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
405
406// deccc simm13, rd -> subcc rd, simm13, rd
407def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
408
409// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
410def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
411def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
412
413// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
414def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
415def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
416
417// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
418def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
419def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
420
421// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
422def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
423def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
424
425
426// clr rd -> or %g0, %g0, rd
427def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
428
429// clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
430def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
431def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
432def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
433def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
434def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
435def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
436
437
438// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
439def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
440def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
441
442// mov specialreg, rd -> rd specialreg, rd
443def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
444def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
445def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
446def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
447
448// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
449def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
450def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
451def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
452def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
453def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
454def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
455def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
456def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
457
458// End of Section A.3
459
460// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
461// (aka: omit the first arg when it's g0. This is not in the manual, but is
462// supported by gnu and solaris as)
463def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
464def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
465def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
466def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
467def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
468def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
469def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
470def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
471
472def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
473def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>;
474
475// flush -> flush %g0
476def : InstAlias<"flush", (FLUSH), 0>;
477
478// unimp -> unimp 0
479def : InstAlias<"unimp", (UNIMP 0), 0>;
480
481def : MnemonicAlias<"iflush", "flush">;
482
483def : MnemonicAlias<"stub", "stb">;
484def : MnemonicAlias<"stsb", "stb">;
485
486def : MnemonicAlias<"stuba", "stba">;
487def : MnemonicAlias<"stsba", "stba">;
488
489def : MnemonicAlias<"stuh", "sth">;
490def : MnemonicAlias<"stsh", "sth">;
491
492def : MnemonicAlias<"stuha", "stha">;
493def : MnemonicAlias<"stsha", "stha">;
494
495def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;
496def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
497
498def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
499
500def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
501def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
502
503def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
504def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
505
506
507def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
508def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
509def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
510                Requires<[HasHardQuad]>;
511
512def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
513def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
514                                                     DFPRegs:$rs2)>;
515def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
516                                                     QFPRegs:$rs2)>,
517                Requires<[HasHardQuad]>;
518
519// signx rd -> sra rd, %g0, rd
520def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
521
522// signx reg, rd -> sra reg, %g0, rd
523def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
524