xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/SparcInstrAliases.td (revision 7ef62cebc2f965b0f640263e179276928885e33d) 
1//===-- SparcInstrAliases.td - Instruction Aliases for Sparc Target -------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains instruction aliases for Sparc.
10//===----------------------------------------------------------------------===//
11
12// Instruction aliases for conditional moves.
13
14// mov<cond> <ccreg> rs2, rd
15multiclass intcond_mov_alias<string cond, int condVal, string ccreg,
16                          Instruction movrr, Instruction movri,
17                          Instruction fmovs, Instruction fmovd> {
18
19  // mov<cond> (%icc|%xcc), rs2, rd
20  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
21                             ", $rs2, $rd"),
22                  (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
23
24  // mov<cond> (%icc|%xcc), simm11, rd
25  def : InstAlias<!strconcat(!strconcat(!strconcat("mov", cond), ccreg),
26                             ", $simm11, $rd"),
27                  (movri IntRegs:$rd, i32imm:$simm11, condVal)>;
28
29  // fmovs<cond> (%icc|%xcc), $rs2, $rd
30  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovs", cond), ccreg),
31                             ", $rs2, $rd"),
32                  (fmovs FPRegs:$rd, FPRegs:$rs2, condVal)>;
33
34  // fmovd<cond> (%icc|%xcc), $rs2, $rd
35  def : InstAlias<!strconcat(!strconcat(!strconcat("fmovd", cond), ccreg),
36                             ", $rs2, $rd"),
37                  (fmovd DFPRegs:$rd, DFPRegs:$rs2, condVal)>;
38}
39
40// mov<cond> <ccreg> rs2, rd
41multiclass fpcond_mov_alias<string cond, int condVal,
42                           Instruction movrr, Instruction movri,
43                           Instruction fmovs, Instruction fmovd> {
44
45  // mov<cond> %fcc[0-3], rs2, rd
46  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $rs2, $rd"),
47                  (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
48
49  // mov<cond> %fcc[0-3], simm11, rd
50  def : InstAlias<!strconcat(!strconcat("mov", cond), " $cc, $simm11, $rd"),
51                  (movri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, condVal)>;
52
53  // fmovs<cond> %fcc[0-3], $rs2, $rd
54  def : InstAlias<!strconcat(!strconcat("fmovs", cond), " $cc, $rs2, $rd"),
55                  (fmovs FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, condVal)>;
56
57  // fmovd<cond> %fcc[0-3], $rs2, $rd
58  def : InstAlias<!strconcat(!strconcat("fmovd", cond), " $cc, $rs2, $rd"),
59                  (fmovd DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, condVal)>;
60}
61
62// movr<cond> rs1, rs2, rd
63multiclass regcond_mov_alias<string rcond, int condVal,
64                          Instruction movrrr, Instruction movrri,
65                          Instruction fmovrs, Instruction fmovrd,
66                          Instruction fmovrq> {
67
68  // movr<cond> $rs1, $rs2, $rd
69  def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $rs2, $rd"),
70                  (movrrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, condVal)>;
71
72  // movr<cond> $rs1, $simm10, $rd
73  def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $simm10, $rd"),
74                  (movrri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, condVal)>;
75
76  // fmovrs<cond> $rs1, $rs2, $rd
77  def : InstAlias<!strconcat(!strconcat("fmovrs", rcond), " $rs1, $rs2, $rd"),
78                  (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
79
80  // fmovrd<cond> $rs1, $rs2, $rd
81  def : InstAlias<!strconcat(!strconcat("fmovrd", rcond), " $rs1, $rs2, $rd"),
82                  (fmovrd DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, condVal)>;
83
84  // fmovrq<cond> $rs1, $rs2, $rd
85  let Predicates = [HasHardQuad] in
86  def : InstAlias<!strconcat(!strconcat("fmovrq", rcond), " $rs1, $rs2, $rd"),
87                  (fmovrq QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, condVal)>;
88}
89
90// Instruction aliases for integer conditional branches and moves.
91multiclass int_cond_alias<string cond, int condVal> {
92
93  // b<cond> $imm
94  def : InstAlias<!strconcat(!strconcat("b", cond), " $imm"),
95                  (BCOND brtarget:$imm, condVal)>;
96
97  // b<cond>,a $imm
98  def : InstAlias<!strconcat(!strconcat("b", cond), ",a $imm"),
99                  (BCONDA brtarget:$imm, condVal)>;
100
101  // b<cond> %icc, $imm
102  def : InstAlias<!strconcat(!strconcat("b", cond), " %icc, $imm"),
103                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
104
105  // b<cond>,pt %icc, $imm
106  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %icc, $imm"),
107                  (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
108
109  // b<cond>,a %icc, $imm
110  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %icc, $imm"),
111                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
112
113  // b<cond>,a,pt %icc, $imm
114  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %icc, $imm"),
115                  (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
116
117  // b<cond>,pn %icc, $imm
118  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %icc, $imm"),
119                  (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
120
121  // b<cond>,a,pn %icc, $imm
122  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %icc, $imm"),
123                  (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
124
125  // b<cond> %xcc, $imm
126  def : InstAlias<!strconcat(!strconcat("b", cond), " %xcc, $imm"),
127                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
128
129  // b<cond>,pt %xcc, $imm
130  def : InstAlias<!strconcat(!strconcat("b", cond), ",pt %xcc, $imm"),
131                  (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
132
133  // b<cond>,a %xcc, $imm
134  def : InstAlias<!strconcat(!strconcat("b", cond), ",a %xcc, $imm"),
135                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
136
137  // b<cond>,a,pt %xcc, $imm
138  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pt %xcc, $imm"),
139                  (BPXCCA brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
140
141  // b<cond>,pn %xcc, $imm
142  def : InstAlias<!strconcat(!strconcat("b", cond), ",pn %xcc, $imm"),
143                  (BPXCCNT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
144
145  // b<cond>,a,pn %xcc, $imm
146  def : InstAlias<!strconcat(!strconcat("b", cond), ",a,pn %xcc, $imm"),
147                  (BPXCCANT brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
148
149
150  defm : intcond_mov_alias<cond, condVal, " %icc",
151                            MOVICCrr, MOVICCri,
152                            FMOVS_ICC, FMOVD_ICC>, Requires<[HasV9]>;
153
154  defm : intcond_mov_alias<cond, condVal, " %xcc",
155                            MOVXCCrr, MOVXCCri,
156                            FMOVS_XCC, FMOVD_XCC>, Requires<[Is64Bit]>;
157
158  // fmovq<cond> (%icc|%xcc), $rs2, $rd
159  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %icc, $rs2, $rd"),
160                  (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
161                  Requires<[HasV9, HasHardQuad]>;
162  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " %xcc, $rs2, $rd"),
163                  (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, condVal)>,
164                  Requires<[Is64Bit, HasHardQuad]>;
165
166  // t<cond> %icc,  rs => t<cond> %icc, G0 + rs
167  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs2"),
168                  (TICCrr G0, IntRegs:$rs2, condVal)>,
169                  Requires<[HasV9]>;
170  // t<cond> %icc, rs1 + rs2
171  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $rs2"),
172                  (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
173                  Requires<[HasV9]>;
174
175
176  // t<cond> %xcc, rs => t<cond> %xcc, G0 + rs
177  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs2"),
178                  (TXCCrr G0, IntRegs:$rs2, condVal)>,
179                  Requires<[HasV9]>;
180  // t<cond> %xcc, rs1 + rs2
181  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $rs2"),
182                  (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
183                  Requires<[HasV9]>;
184
185
186  // t<cond> rs=> t<cond> %icc,  G0 + rs2
187  //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs2"),
188  //                (TICCrr G0, IntRegs:$rs2, condVal)>,
189  //                Requires<[HasV9]>;
190
191  // t<cond> rs1 + rs2 => t<cond> %icc, rs1 + rs2
192  //def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
193  //                (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
194  //                Requires<[HasV9]>;
195
196  // t<cond> %icc, imm => t<cond> %icc, G0 + imm
197  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $imm"),
198                  (TICCri G0, i32imm:$imm, condVal)>,
199                  Requires<[HasV9]>;
200  // t<cond> %icc, rs1 + imm
201  def : InstAlias<!strconcat(!strconcat("t", cond), " %icc, $rs1 + $imm"),
202                  (TICCri IntRegs:$rs1, i32imm:$imm, condVal)>,
203                  Requires<[HasV9]>;
204  // t<cond> %xcc, imm => t<cond> %xcc, G0 + imm
205  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $imm"),
206                  (TXCCri G0, i32imm:$imm, condVal)>,
207                  Requires<[HasV9]>;
208  // t<cond> %xcc, rs1 + imm
209  def : InstAlias<!strconcat(!strconcat("t", cond), " %xcc, $rs1 + $imm"),
210                  (TXCCri IntRegs:$rs1, i32imm:$imm, condVal)>,
211                  Requires<[HasV9]>;
212
213  // t<cond> imm => t<cond> G0 + imm
214  def : InstAlias<!strconcat(!strconcat("t", cond), " $imm"),
215                  (TRAPri G0, i32imm:$imm, condVal)>;
216
217  // t<cond> rs1 + imm => t<cond> rs1 + imm
218  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $imm"),
219                  (TRAPri IntRegs:$rs1, i32imm:$imm, condVal)>;
220
221  // t<cond> rs1 => t<cond> G0 + rs1
222  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1"),
223                  (TRAPrr G0, IntRegs:$rs1, condVal)>;
224
225  // t<cond> rs1 + rs2
226  def : InstAlias<!strconcat(!strconcat("t", cond), " $rs1 + $rs2"),
227                  (TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
228}
229
230
231// Instruction aliases for floating point conditional branches and moves.
232multiclass fp_cond_alias<string cond, int condVal> {
233
234  // fb<cond> $imm
235  def : InstAlias<!strconcat(!strconcat("fb", cond), " $imm"),
236                  (FBCOND brtarget:$imm, condVal), 0>;
237
238  // fb<cond>,a $imm
239  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $imm"),
240                  (FBCONDA brtarget:$imm, condVal), 0>;
241
242  // fb<cond> %fcc0, $imm
243  def : InstAlias<!strconcat(!strconcat("fb", cond), " $cc, $imm"),
244                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
245                  Requires<[HasV9]>;
246
247  // fb<cond>,pt %fcc0, $imm
248  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pt $cc, $imm"),
249                  (BPFCC brtarget:$imm, condVal, FCCRegs:$cc)>,
250                  Requires<[HasV9]>;
251
252  // fb<cond>,a %fcc0, $imm
253  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a $cc, $imm"),
254                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
255                  Requires<[HasV9]>;
256
257  // fb<cond>,a,pt %fcc0, $imm
258  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pt $cc, $imm"),
259                  (BPFCCA brtarget:$imm, condVal, FCCRegs:$cc)>,
260                   Requires<[HasV9]>;
261
262  // fb<cond>,pn %fcc0, $imm
263  def : InstAlias<!strconcat(!strconcat("fb", cond), ",pn $cc, $imm"),
264                  (BPFCCNT brtarget:$imm, condVal, FCCRegs:$cc)>,
265                   Requires<[HasV9]>;
266
267  // fb<cond>,a,pn %fcc0, $imm
268  def : InstAlias<!strconcat(!strconcat("fb", cond), ",a,pn $cc, $imm"),
269                  (BPFCCANT brtarget:$imm, condVal, FCCRegs:$cc)>,
270                  Requires<[HasV9]>;
271
272  defm : fpcond_mov_alias<cond, condVal,
273                          V9MOVFCCrr, V9MOVFCCri,
274                          V9FMOVS_FCC, V9FMOVD_FCC>, Requires<[HasV9]>;
275
276  // fmovq<cond> %fcc0, $rs2, $rd
277  def : InstAlias<!strconcat(!strconcat("fmovq", cond), " $cc, $rs2, $rd"),
278                  (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2,
279                                                          condVal)>,
280                  Requires<[HasV9, HasHardQuad]>;
281}
282
283
284// Instruction aliases for co-processor conditional branches.
285multiclass cp_cond_alias<string cond, int condVal> {
286
287  // cb<cond> $imm
288  def : InstAlias<!strconcat(!strconcat("cb", cond), " $imm"),
289                  (CBCOND brtarget:$imm, condVal), 0>;
290
291  // cb<cond>,a $imm
292  def : InstAlias<!strconcat(!strconcat("cb", cond), ",a $imm"),
293                  (CBCONDA brtarget:$imm, condVal), 0>;
294}
295
296// Instruction aliases for register conditional branches and moves.
297multiclass reg_cond_alias<string rcond, int condVal> {
298  defm : regcond_mov_alias<rcond, condVal,
299                            MOVRrr, MOVRri,
300                            FMOVRS, FMOVRD, FMOVRQ>,
301                            Requires<[Is64Bit]>;
302}
303
304defm : int_cond_alias<"a",    0b1000>;
305defm : int_cond_alias<"n",    0b0000>;
306defm : int_cond_alias<"ne",   0b1001>;
307defm : int_cond_alias<"e",    0b0001>;
308defm : int_cond_alias<"g",    0b1010>;
309defm : int_cond_alias<"le",   0b0010>;
310defm : int_cond_alias<"ge",   0b1011>;
311defm : int_cond_alias<"l",    0b0011>;
312defm : int_cond_alias<"gu",   0b1100>;
313defm : int_cond_alias<"leu",  0b0100>;
314defm : int_cond_alias<"cc",   0b1101>;
315defm : int_cond_alias<"cs",   0b0101>;
316defm : int_cond_alias<"pos",  0b1110>;
317defm : int_cond_alias<"neg",  0b0110>;
318defm : int_cond_alias<"vc",   0b1111>;
319defm : int_cond_alias<"vs",   0b0111>;
320let EmitPriority = 0 in
321{
322  defm : int_cond_alias<"",     0b1000>; // same as a; gnu asm, not in manual
323  defm : int_cond_alias<"nz",   0b1001>; // same as ne
324  defm : int_cond_alias<"eq",   0b0001>; // same as e
325  defm : int_cond_alias<"z",    0b0001>; // same as e
326  defm : int_cond_alias<"geu",  0b1101>; // same as cc
327  defm : int_cond_alias<"lu",   0b0101>; // same as cs
328}
329defm : fp_cond_alias<"a",     0b1000>;
330defm : fp_cond_alias<"n",     0b0000>;
331defm : fp_cond_alias<"u",     0b0111>;
332defm : fp_cond_alias<"g",     0b0110>;
333defm : fp_cond_alias<"ug",    0b0101>;
334defm : fp_cond_alias<"l",     0b0100>;
335defm : fp_cond_alias<"ul",    0b0011>;
336defm : fp_cond_alias<"lg",    0b0010>;
337defm : fp_cond_alias<"ne",    0b0001>;
338defm : fp_cond_alias<"e",     0b1001>;
339defm : fp_cond_alias<"ue",    0b1010>;
340defm : fp_cond_alias<"ge",    0b1011>;
341defm : fp_cond_alias<"uge",   0b1100>;
342defm : fp_cond_alias<"le",    0b1101>;
343defm : fp_cond_alias<"ule",   0b1110>;
344defm : fp_cond_alias<"o",     0b1111>;
345let EmitPriority = 0 in
346{
347  defm : fp_cond_alias<"",      0b1000>; // same as a; gnu asm, not in manual
348  defm : fp_cond_alias<"nz",    0b0001>; // same as ne
349  defm : fp_cond_alias<"z",     0b1001>; // same as e
350}
351
352defm : cp_cond_alias<"a",     0b1000>;
353defm : cp_cond_alias<"n",     0b0000>;
354defm : cp_cond_alias<"3",     0b0111>;
355defm : cp_cond_alias<"2",     0b0110>;
356defm : cp_cond_alias<"23",    0b0101>;
357defm : cp_cond_alias<"1",     0b0100>;
358defm : cp_cond_alias<"13",    0b0011>;
359defm : cp_cond_alias<"12",    0b0010>;
360defm : cp_cond_alias<"123",   0b0001>;
361defm : cp_cond_alias<"0",     0b1001>;
362defm : cp_cond_alias<"03",    0b1010>;
363defm : cp_cond_alias<"02",    0b1011>;
364defm : cp_cond_alias<"023",   0b1100>;
365defm : cp_cond_alias<"01",    0b1101>;
366defm : cp_cond_alias<"013",   0b1110>;
367defm : cp_cond_alias<"012",   0b1111>;
368let EmitPriority = 0 in defm : cp_cond_alias<"",      0b1000>; // same as a; gnu asm, not in manual
369
370defm : reg_cond_alias<"z",    0b001>;
371defm : reg_cond_alias<"lez",  0b010>;
372defm : reg_cond_alias<"lz",   0b011>;
373defm : reg_cond_alias<"nz",   0b101>;
374defm : reg_cond_alias<"gz",   0b110>;
375defm : reg_cond_alias<"gez",  0b111>;
376
377// Section A.3 Synthetic Instructions
378
379// Most are marked as Emit=0, so that they are not used for disassembly. This is
380// an aesthetic issue, but the chosen policy is to typically prefer using the
381// non-alias form, except for the most obvious and clarifying aliases: cmp, jmp,
382// call, tst, ret, retl.
383
384// Note: cmp is handled in SparcInstrInfo.
385//       jmp/call/ret/retl have special case handling for output in
386//       SparcInstPrinter.cpp
387
388// jmp addr -> jmpl addr, %g0
389def : InstAlias<"jmp $addr", (JMPLrr G0, MEMrr:$addr), 0>;
390def : InstAlias<"jmp $addr", (JMPLri G0, MEMri:$addr), 0>;
391
392// call addr -> jmpl addr, %o7
393def : InstAlias<"call $addr", (JMPLrr O7, MEMrr:$addr), 0>;
394def : InstAlias<"call $addr", (JMPLri O7, MEMri:$addr), 0>;
395
396// tst reg -> orcc %g0, reg, %g0
397def : InstAlias<"tst $rs2", (ORCCrr G0, IntRegs:$rs2, G0)>;
398
399// ret -> jmpl %i7+8, %g0 (aka RET 8)
400def : InstAlias<"ret", (RET 8)>;
401
402// retl -> jmpl %o7+8, %g0 (aka RETL 8)
403def : InstAlias<"retl", (RETL 8)>;
404
405// restore -> restore %g0, %g0, %g0
406def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
407
408// save -> restore %g0, %g0, %g0
409def : InstAlias<"save", (SAVErr G0, G0, G0)>;
410
411// set value, rd
412// (turns into a sequence of sethi+or, depending on the value)
413// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
414def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
415
416// not rd -> xnor rd, %g0, rd
417def : InstAlias<"not $rd", (XNORrr IntRegs:$rd, IntRegs:$rd, G0), 0>;
418
419// not reg, rd -> xnor reg, %g0, rd
420def : InstAlias<"not $rs1, $rd", (XNORrr IntRegs:$rd, IntRegs:$rs1, G0), 0>;
421
422// neg rd -> sub %g0, rd, rd
423def : InstAlias<"neg $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rd), 0>;
424
425// neg reg, rd -> sub %g0, reg, rd
426def : InstAlias<"neg $rs2, $rd", (SUBrr IntRegs:$rd, G0, IntRegs:$rs2), 0>;
427
428// inc rd -> add rd, 1, rd
429def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
430
431// inc simm13, rd -> add rd, simm13, rd
432def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
433
434// inccc rd -> addcc rd, 1, rd
435def : InstAlias<"inccc $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
436
437// inccc simm13, rd -> addcc rd, simm13, rd
438def : InstAlias<"inccc $simm13, $rd", (ADDCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
439
440// dec rd -> sub rd, 1, rd
441def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
442
443// dec simm13, rd -> sub rd, simm13, rd
444def : InstAlias<"dec $simm13, $rd", (SUBri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
445
446// deccc rd -> subcc rd, 1, rd
447def : InstAlias<"deccc $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, 1), 0>;
448
449// deccc simm13, rd -> subcc rd, simm13, rd
450def : InstAlias<"deccc $simm13, $rd", (SUBCCri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
451
452// btst reg_or_imm, reg -> andcc reg,reg_or_imm,%g0
453def : InstAlias<"btst $rs2, $rs1", (ANDCCrr G0, IntRegs:$rs1, IntRegs:$rs2), 0>;
454def : InstAlias<"btst $simm13, $rs1", (ANDCCri G0, IntRegs:$rs1, i32imm:$simm13), 0>;
455
456// bset reg_or_imm, rd -> or rd,reg_or_imm,rd
457def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
458def : InstAlias<"bset $simm13, $rd", (ORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
459
460// bclr reg_or_imm, rd -> andn rd,reg_or_imm,rd
461def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
462def : InstAlias<"bclr $simm13, $rd", (ANDNri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
463
464// btog reg_or_imm, rd -> xor rd,reg_or_imm,rd
465def : InstAlias<"btog $rs2, $rd", (XORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
466def : InstAlias<"btog $simm13, $rd", (XORri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
467
468
469// clr rd -> or %g0, %g0, rd
470def : InstAlias<"clr $rd", (ORrr IntRegs:$rd, G0, G0), 0>;
471
472// clr{b,h,} [addr] -> st{b,h,} %g0, [addr]
473def : InstAlias<"clrb [$addr]", (STBrr MEMrr:$addr, G0), 0>;
474def : InstAlias<"clrb [$addr]", (STBri MEMri:$addr, G0), 0>;
475def : InstAlias<"clrh [$addr]", (STHrr MEMrr:$addr, G0), 0>;
476def : InstAlias<"clrh [$addr]", (STHri MEMri:$addr, G0), 0>;
477def : InstAlias<"clr [$addr]", (STrr MEMrr:$addr, G0), 0>;
478def : InstAlias<"clr [$addr]", (STri MEMri:$addr, G0), 0>;
479
480
481// mov reg_or_imm, rd -> or %g0, reg_or_imm, rd
482def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
483def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
484
485// mov specialreg, rd -> rd specialreg, rd
486def : InstAlias<"mov $asr, $rd", (RDASR IntRegs:$rd, ASRRegs:$asr), 0>;
487def : InstAlias<"mov %psr, $rd", (RDPSR IntRegs:$rd), 0>;
488def : InstAlias<"mov %wim, $rd", (RDWIM IntRegs:$rd), 0>;
489def : InstAlias<"mov %tbr, $rd", (RDTBR IntRegs:$rd), 0>;
490def : InstAlias<"mov %pc, $rd", (RDPC IntRegs:$rd), 0>;
491
492// mov reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
493def : InstAlias<"mov $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
494def : InstAlias<"mov $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
495def : InstAlias<"mov $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
496def : InstAlias<"mov $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
497def : InstAlias<"mov $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
498def : InstAlias<"mov $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
499def : InstAlias<"mov $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
500def : InstAlias<"mov $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
501
502// End of Section A.3
503
504// wr reg_or_imm, specialreg -> wr %g0, reg_or_imm, specialreg
505// (aka: omit the first arg when it's g0. This is not in the manual, but is
506// supported by gnu and solaris as)
507def : InstAlias<"wr $rs2, $asr", (WRASRrr ASRRegs:$asr, G0, IntRegs:$rs2), 0>;
508def : InstAlias<"wr $simm13, $asr", (WRASRri ASRRegs:$asr, G0, i32imm:$simm13), 0>;
509def : InstAlias<"wr $rs2, %psr", (WRPSRrr G0, IntRegs:$rs2), 0>;
510def : InstAlias<"wr $simm13, %psr", (WRPSRri G0, i32imm:$simm13), 0>;
511def : InstAlias<"wr $rs2, %wim", (WRWIMrr G0, IntRegs:$rs2), 0>;
512def : InstAlias<"wr $simm13, %wim", (WRWIMri G0, i32imm:$simm13), 0>;
513def : InstAlias<"wr $rs2, %tbr", (WRTBRrr G0, IntRegs:$rs2), 0>;
514def : InstAlias<"wr $simm13, %tbr", (WRTBRri G0, i32imm:$simm13), 0>;
515
516def : InstAlias<"pwr $rs2, %psr", (PWRPSRrr G0, IntRegs:$rs2), 0>;
517def : InstAlias<"pwr $simm13, %psr", (PWRPSRri G0, i32imm:$simm13), 0>;
518
519// wrpr %reg, %rd -> wrpr %reg, %g0, %rd
520// wrpr  imm, %rd -> wrpr  %g0, imm, %rd
521// Nonstandard GNU extensions.
522let Predicates = [HasV9] in {
523  def : InstAlias<"wrpr $rs1, $rd", (WRPRrr PRRegs:$rd, IntRegs:$rs1, G0), 0>;
524  def : InstAlias<"wrpr $simm13, $rd", (WRPRri PRRegs:$rd, G0, i32imm:$simm13), 0>;
525}
526
527// flush -> flush %g0
528def : InstAlias<"flush", (FLUSH), 0>;
529
530// unimp -> unimp 0
531def : InstAlias<"unimp", (UNIMP 0), 0>;
532
533def : MnemonicAlias<"iflush", "flush">;
534
535def : MnemonicAlias<"stub", "stb">;
536def : MnemonicAlias<"stsb", "stb">;
537
538def : MnemonicAlias<"stuba", "stba">;
539def : MnemonicAlias<"stsba", "stba">;
540
541def : MnemonicAlias<"stuh", "sth">;
542def : MnemonicAlias<"stsh", "sth">;
543
544def : MnemonicAlias<"stuha", "stha">;
545def : MnemonicAlias<"stsha", "stha">;
546def : MnemonicAlias<"stw", "st">, Requires<[HasV9]>;
547
548def : MnemonicAlias<"lduw", "ld">, Requires<[HasV9]>;
549def : MnemonicAlias<"lduwa", "lda">, Requires<[HasV9]>;
550
551def : MnemonicAlias<"return", "rett">, Requires<[HasV9]>;
552
553def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
554def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
555
556def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
557def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
558
559
560def : InstAlias<"fcmps $rs1, $rs2", (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
561def : InstAlias<"fcmpd $rs1, $rs2", (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)>;
562def : InstAlias<"fcmpq $rs1, $rs2", (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)>,
563                Requires<[HasHardQuad]>;
564
565def : InstAlias<"fcmpes $rs1, $rs2", (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)>;
566def : InstAlias<"fcmped $rs1, $rs2", (V9FCMPED FCC0, DFPRegs:$rs1,
567                                                     DFPRegs:$rs2)>;
568def : InstAlias<"fcmpeq $rs1, $rs2", (V9FCMPEQ FCC0, QFPRegs:$rs1,
569                                                     QFPRegs:$rs2)>,
570                Requires<[HasHardQuad]>;
571
572// signx rd -> sra rd, %g0, rd
573def : InstAlias<"signx $rd", (SRArr IntRegs:$rd, IntRegs:$rd, G0), 0>, Requires<[HasV9]>;
574
575// signx reg, rd -> sra reg, %g0, rd
576def : InstAlias<"signx $rs1, $rd", (SRArr IntRegs:$rd, IntRegs:$rs1, G0), 0>, Requires<[HasV9]>;
577
578// sir -> sir 0
579def : InstAlias<"sir", (SIR 0), 0>;
580