1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains instruction definitions and patterns needed for 64-bit 10// code generation on SPARC v9. 11// 12// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can 13// also be used in 32-bit code running on a SPARC v9 CPU. 14// 15//===----------------------------------------------------------------------===// 16 17let Predicates = [Is64Bit] in { 18// The same integer registers are used for i32 and i64 values. 19// When registers hold i32 values, the high bits are don't care. 20// This give us free trunc and anyext. 21def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>; 22def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>; 23 24} // Predicates = [Is64Bit] 25 26 27//===----------------------------------------------------------------------===// 28// 64-bit Shift Instructions. 29//===----------------------------------------------------------------------===// 30// 31// The 32-bit shift instructions are still available. The left shift srl 32// instructions shift all 64 bits, but it only accepts a 5-bit shift amount. 33// 34// The srl instructions only shift the low 32 bits and clear the high 32 bits. 35// Finally, sra shifts the low 32 bits and sign-extends to 64 bits. 36 37let Predicates = [Is64Bit] in { 38 39def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>; 40def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>; 41 42def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>; 43def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>; 44 45defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, shift_imm6, I64Regs>; 46defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, shift_imm6, I64Regs>; 47defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>; 48 49} // Predicates = [Is64Bit] 50 51 52//===----------------------------------------------------------------------===// 53// 64-bit Immediates. 54//===----------------------------------------------------------------------===// 55// 56// All 32-bit immediates can be materialized with sethi+or, but 64-bit 57// immediates may require more code. There may be a point where it is 58// preferable to use a constant pool load instead, depending on the 59// microarchitecture. 60 61// Single-instruction patterns. 62 63// Zero immediate. 64def : Pat<(i64 0), (COPY (i64 G0))>, 65 Requires<[Is64Bit]>; 66 67// The ALU instructions want their simm13 operands as i32 immediates. 68// FIXME: This is no longer true, they are now pointer-sized. 69def as_i32imm : SDNodeXForm<imm, [{ 70 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 71}]>; 72def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; 73def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; 74 75// Double-instruction patterns. 76 77// All unsigned i32 immediates can be handled by sethi+or. 78def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 79def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>, 80 Requires<[Is64Bit]>; 81 82// All negative i33 immediates can be handled by sethi+xor. 83def nimm33 : PatLeaf<(imm), [{ 84 int64_t Imm = N->getSExtValue(); 85 return Imm < 0 && isInt<33>(Imm); 86}]>; 87// Bits 10-31 inverted. Same as assembler's %hix. 88def HIX22 : SDNodeXForm<imm, [{ 89 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); 90 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 91}]>; 92// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. 93def LOX10 : SDNodeXForm<imm, [{ 94 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N), 95 MVT::i32); 96}]>; 97def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, 98 Requires<[Is64Bit]>; 99 100// More possible patterns: 101// 102// (sllx sethi, n) 103// (sllx simm13, n) 104// 105// 3 instrs: 106// 107// (xor (sllx sethi), simm13) 108// (sllx (xor sethi, simm13)) 109// 110// 4 instrs: 111// 112// (or sethi, (sllx sethi)) 113// (xnor sethi, (sllx sethi)) 114// 115// 5 instrs: 116// 117// (or (sllx sethi), (or sethi, simm13)) 118// (xnor (sllx sethi), (or sethi, simm13)) 119// (or (sllx sethi), (sllx sethi)) 120// (xnor (sllx sethi), (sllx sethi)) 121// 122// Worst case is 6 instrs: 123// 124// (or (sllx (or sethi, simmm13)), (or sethi, simm13)) 125 126// Bits 42-63, same as assembler's %hh. 127def HH22 : SDNodeXForm<imm, [{ 128 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); 129 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 130}]>; 131// Bits 32-41, same as assembler's %hm. 132def HM10 : SDNodeXForm<imm, [{ 133 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); 134 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 135}]>; 136def : Pat<(i64 imm:$val), 137 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), 138 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>, 139 Requires<[Is64Bit]>; 140 141 142//===----------------------------------------------------------------------===// 143// 64-bit Integer Arithmetic and Logic. 144//===----------------------------------------------------------------------===// 145 146let Predicates = [Is64Bit] in { 147 148def : Pat<(and i64:$lhs, i64:$rhs), (ANDrr $lhs, $rhs)>; 149def : Pat<(or i64:$lhs, i64:$rhs), (ORrr $lhs, $rhs)>; 150def : Pat<(xor i64:$lhs, i64:$rhs), (XORrr $lhs, $rhs)>; 151 152def : Pat<(and i64:$lhs, (i64 simm13:$rhs)), (ANDri $lhs, imm:$rhs)>; 153def : Pat<(or i64:$lhs, (i64 simm13:$rhs)), (ORri $lhs, imm:$rhs)>; 154def : Pat<(xor i64:$lhs, (i64 simm13:$rhs)), (XORri $lhs, imm:$rhs)>; 155 156def : Pat<(and i64:$lhs, (not i64:$rhs)), (ANDNrr $lhs, $rhs)>; 157def : Pat<(or i64:$lhs, (not i64:$rhs)), (ORNrr $lhs, $rhs)>; 158def : Pat<(not (xor i64:$lhs, i64:$rhs)), (XNORrr $lhs, $rhs)>; 159 160def : Pat<(add i64:$lhs, i64:$rhs), (ADDrr $lhs, $rhs)>; 161def : Pat<(sub i64:$lhs, i64:$rhs), (SUBrr $lhs, $rhs)>; 162 163def : Pat<(add i64:$lhs, (i64 simm13:$rhs)), (ADDri $lhs, imm:$rhs)>; 164def : Pat<(sub i64:$lhs, (i64 simm13:$rhs)), (SUBri $lhs, imm:$rhs)>; 165 166def : Pat<(tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym), 167 (TLS_ADDrr $rs1, $rs2, $sym)>; 168 169def : Pat<(SPcmpicc i64:$lhs, i64:$rhs), (SUBCCrr $lhs, $rhs)>; 170def : Pat<(SPcmpicc i64:$lhs, (i64 simm13:$rhs)), (SUBCCri $lhs, imm:$rhs)>; 171def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>; 172 173} // Predicates = [Is64Bit] 174 175 176//===----------------------------------------------------------------------===// 177// 64-bit Integer Multiply and Divide. 178//===----------------------------------------------------------------------===// 179 180let Predicates = [Is64Bit] in { 181 182def MULXrr : F3_1<2, 0b001001, 183 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 184 "mulx $rs1, $rs2, $rd", 185 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 186def MULXri : F3_2<2, 0b001001, 187 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 188 "mulx $rs1, $simm13, $rd", 189 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 190 191// Division can trap. 192let hasSideEffects = 1 in { 193def SDIVXrr : F3_1<2, 0b101101, 194 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 195 "sdivx $rs1, $rs2, $rd", 196 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; 197def SDIVXri : F3_2<2, 0b101101, 198 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 199 "sdivx $rs1, $simm13, $rd", 200 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; 201 202def UDIVXrr : F3_1<2, 0b001101, 203 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 204 "udivx $rs1, $rs2, $rd", 205 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; 206def UDIVXri : F3_2<2, 0b001101, 207 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 208 "udivx $rs1, $simm13, $rd", 209 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; 210} // hasSideEffects = 1 211 212} // Predicates = [Is64Bit] 213 214 215//===----------------------------------------------------------------------===// 216// 64-bit Loads and Stores. 217//===----------------------------------------------------------------------===// 218// 219// All the 32-bit loads and stores are available. The extending loads are sign 220// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits 221// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned 222// Word). 223// 224// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads. 225 226let Predicates = [Is64Bit] in { 227 228// 64-bit loads. 229defm LDX : LoadA<"ldx", 0b001011, 0b011011, load, I64Regs, i64>; 230 231let mayLoad = 1, isAsmParserOnly = 1 in { 232 def TLS_LDXrr : F3_1<3, 0b001011, 233 (outs IntRegs:$rd), 234 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym), 235 "ldx [$addr], $rd, $sym", 236 [(set i64:$rd, 237 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 238 def GDOP_LDXrr : F3_1<3, 0b001011, 239 (outs I64Regs:$rd), 240 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym), 241 "ldx [$addr], $rd, $sym", 242 [(set i64:$rd, 243 (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>; 244} 245 246// Extending loads to i64. 247def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 248def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 249def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 250def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 251 252def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 253def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 254def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 255def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 256def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>; 257def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>; 258 259def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 260def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 261def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 262def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 263def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>; 264def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>; 265 266def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 267def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 268def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 269def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 270 271// Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 272defm LDSW : LoadA<"ldsw", 0b001000, 0b011000, sextloadi32, I64Regs, i64>; 273 274// 64-bit stores. 275defm STX : StoreA<"stx", 0b001110, 0b011110, store, I64Regs, i64>; 276 277// Truncating stores from i64 are identical to the i32 stores. 278def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 279def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>; 280def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>; 281def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>; 282def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>; 283def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>; 284 285// store 0, addr -> store %g0, addr 286def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>; 287def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>; 288 289} // Predicates = [Is64Bit] 290 291 292//===----------------------------------------------------------------------===// 293// 64-bit Conditionals. 294//===----------------------------------------------------------------------===// 295 296// 297// Flag-setting instructions like subcc and addcc set both icc and xcc flags. 298// The icc flags correspond to the 32-bit result, and the xcc are for the 299// full 64-bit result. 300// 301// We reuse CMPICC SDNodes for compares, but use new BPXCC branch nodes for 302// 64-bit compares. See LowerBR_CC. 303 304let Predicates = [Is64Bit] in { 305 306let Uses = [ICC], cc = 0b10 in 307 defm BPX : IPredBranch<"%xcc", [(SPbpxcc bb:$imm19, imm:$cond)]>; 308 309// Conditional moves on %xcc. 310let Uses = [ICC], Constraints = "$f = $rd" in { 311let intcc = 1, cc = 0b10 in { 312def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd), 313 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 314 "mov$cond %xcc, $rs2, $rd", 315 [(set i32:$rd, 316 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; 317def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd), 318 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 319 "mov$cond %xcc, $simm11, $rd", 320 [(set i32:$rd, 321 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>; 322} // cc 323 324let intcc = 1, opf_cc = 0b10 in { 325def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 326 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 327 "fmovs$cond %xcc, $rs2, $rd", 328 [(set f32:$rd, 329 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; 330def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 331 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 332 "fmovd$cond %xcc, $rs2, $rd", 333 [(set f64:$rd, 334 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 335let Predicates = [Is64Bit, HasHardQuad] in 336def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 337 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 338 "fmovq$cond %xcc, $rs2, $rd", 339 [(set f128:$rd, 340 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>; 341} // opf_cc 342} // Uses, Constraints 343 344// Branch On integer register with Prediction (BPr). 345let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in 346multiclass BranchOnReg<list<dag> CCPattern> { 347 def R : F2_4<0, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 348 "br$rcond $rs1, $imm16", CCPattern>; 349 def RA : F2_4<1, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 350 "br$rcond,a $rs1, $imm16", []>; 351 def RNT : F2_4<0, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 352 "br$rcond,pn $rs1, $imm16", []>; 353 def RANT : F2_4<1, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 354 "br$rcond,a,pn $rs1, $imm16", []>; 355} 356 357multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> { 358 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"), 359 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>; 360 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"), 361 (APT I64Regs:$rs1, bprtarget16:$imm16), 0>; 362} 363 364let Predicates = [Is64Bit] in 365 defm BP : BranchOnReg<[(SPbrreg bb:$imm16, imm:$rcond, i64:$rs1)]>; 366 367// Move integer register on register condition (MOVr). 368let Predicates = [Is64Bit], Constraints = "$f = $rd" in { 369 def MOVRrr : F4_4r<0b101111, 0b00000, (outs IntRegs:$rd), 370 (ins I64Regs:$rs1, IntRegs:$rs2, IntRegs:$f, RegCCOp:$rcond), 371 "movr$rcond $rs1, $rs2, $rd", 372 [(set i32:$rd, (SPselectreg i32:$rs2, i32:$f, imm:$rcond, i64:$rs1))]>; 373 374 def MOVRri : F4_4i<0b101111, (outs IntRegs:$rd), 375 (ins I64Regs:$rs1, i32imm:$simm10, IntRegs:$f, RegCCOp:$rcond), 376 "movr$rcond $rs1, $simm10, $rd", 377 [(set i32:$rd, (SPselectreg simm10:$simm10, i32:$f, imm:$rcond, i64:$rs1))]>; 378} 379 380// Move FP register on integer register condition (FMOVr). 381let Predicates = [Is64Bit], Constraints = "$f = $rd" in { 382 def FMOVRS : F4_4r<0b110101, 0b00101, 383 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2, FPRegs:$f, RegCCOp:$rcond), 384 "fmovrs$rcond $rs1, $rs2, $rd", 385 [(set f32:$rd, (SPselectreg f32:$rs2, f32:$f, imm:$rcond, i64:$rs1))]>; 386 def FMOVRD : F4_4r<0b110101, 0b00110, 387 (outs DFPRegs:$rd), (ins I64Regs:$rs1, DFPRegs:$rs2, DFPRegs:$f, RegCCOp:$rcond), 388 "fmovrd$rcond $rs1, $rs2, $rd", 389 [(set f64:$rd, (SPselectreg f64:$rs2, f64:$f, imm:$rcond, i64:$rs1))]>; 390 let Predicates = [HasHardQuad] in 391 def FMOVRQ : F4_4r<0b110101, 0b00111, 392 (outs QFPRegs:$rd), (ins I64Regs:$rs1, QFPRegs:$rs2, QFPRegs:$f, RegCCOp:$rcond), 393 "fmovrq$rcond $rs1, $rs2, $rd", 394 [(set f128:$rd, (SPselectreg f128:$rs2, f128:$f, imm:$rcond, i64:$rs1))]>; 395} 396 397//===----------------------------------------------------------------------===// 398// 64-bit Floating Point Conversions. 399//===----------------------------------------------------------------------===// 400 401let Predicates = [Is64Bit] in { 402 403def FXTOS : F3_3u<2, 0b110100, 0b010000100, 404 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 405 "fxtos $rs2, $rd", 406 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 407def FXTOD : F3_3u<2, 0b110100, 0b010001000, 408 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 409 "fxtod $rs2, $rd", 410 [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 411let Predicates = [Is64Bit, HasHardQuad] in 412def FXTOQ : F3_3u<2, 0b110100, 0b010001100, 413 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 414 "fxtoq $rs2, $rd", 415 [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 416 417def FSTOX : F3_3u<2, 0b110100, 0b010000001, 418 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 419 "fstox $rs2, $rd", 420 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>; 421def FDTOX : F3_3u<2, 0b110100, 0b010000010, 422 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 423 "fdtox $rs2, $rd", 424 [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>; 425let Predicates = [Is64Bit, HasHardQuad] in 426def FQTOX : F3_3u<2, 0b110100, 0b010000011, 427 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 428 "fqtox $rs2, $rd", 429 [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>; 430 431} // Predicates = [Is64Bit] 432 433def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), 434 (MOVXCCrr $t, $f, imm:$cond)>; 435def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond), 436 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>; 437 438def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond), 439 (MOVICCrr $t, $f, imm:$cond)>; 440def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond), 441 (MOVICCri (as_i32imm $t), $f, imm:$cond)>; 442 443def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond), 444 (MOVFCCrr $t, $f, imm:$cond)>; 445def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond), 446 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>; 447 448def : Pat<(SPselectreg i64:$t, i64:$f, imm:$rcond, i64:$rs1), 449 (MOVRrr $rs1, $t, $f, imm:$rcond)>; 450def : Pat<(SPselectreg (i64 simm10:$t), i64:$f, imm:$rcond, i64:$rs1), 451 (MOVRri $rs1, (as_i32imm $t), $f, imm:$rcond)>; 452 453} // Predicates = [Is64Bit] 454 455// ATOMICS. 456let Predicates = [Is64Bit, HasV9], Constraints = "$swap = $rd" in { 457 def CASXArr: F3_1_asi<3, 0b111110, 458 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, 459 I64Regs:$swap, ASITag:$asi), 460 "casxa [$rs1] $asi, $rs2, $rd", 461 []>; 462 463 let Uses = [ASR3] in 464 def CASXAri: F3_1_cas_asi<3, 0b111110, 465 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, 466 I64Regs:$swap), 467 "casxa [$rs1] %asi, $rs2, $rd", 468 []>; 469} // Predicates = [Is64Bit], Constraints = ... 470 471let Predicates = [Is64Bit] in { 472 473// atomic_load_64 addr -> load addr 474def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>; 475def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>; 476 477// atomic_store_64 val, addr -> store val, addr 478def : Pat<(atomic_store_64 i64:$val, ADDRrr:$dst), (STXrr ADDRrr:$dst, $val)>; 479def : Pat<(atomic_store_64 i64:$val, ADDRri:$dst), (STXri ADDRri:$dst, $val)>; 480 481def : Pat<(atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap), 482 (CASXArr $rs1, $rs2, $swap, 0x80)>; 483 484} // Predicates = [Is64Bit] 485 486let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in 487 defm TXCC : TRAP<"%xcc">; 488 489// Global addresses, constant pool entries 490let Predicates = [Is64Bit] in { 491 492def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 493def : Pat<(SPlo tglobaladdr:$in), (ORri (i64 G0), tglobaladdr:$in)>; 494def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 495def : Pat<(SPlo tconstpool:$in), (ORri (i64 G0), tconstpool:$in)>; 496 497// GlobalTLS addresses 498def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 499def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i64 G0), tglobaltlsaddr:$in)>; 500def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 501 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 502def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 503 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 504 505// Blockaddress 506def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 507def : Pat<(SPlo tblockaddress:$in), (ORri (i64 G0), tblockaddress:$in)>; 508 509// Add reg, lo. This is used when taking the addr of a global/constpool entry. 510def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>; 511def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>; 512def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 513 (ADDri $r, tblockaddress:$in)>; 514} 515