1//===-- SparcInstr64Bit.td - 64-bit instructions for Sparc Target ---------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains instruction definitions and patterns needed for 64-bit 10// code generation on SPARC v9. 11// 12// Some SPARC v9 instructions are defined in SparcInstrInfo.td because they can 13// also be used in 32-bit code running on a SPARC v9 CPU. 14// 15//===----------------------------------------------------------------------===// 16 17let Predicates = [Is64Bit] in { 18// The same integer registers are used for i32 and i64 values. 19// When registers hold i32 values, the high bits are don't care. 20// This give us free trunc and anyext. 21def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>; 22def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>; 23 24} // Predicates = [Is64Bit] 25 26 27//===----------------------------------------------------------------------===// 28// 64-bit Shift Instructions. 29//===----------------------------------------------------------------------===// 30// 31// The 32-bit shift instructions are still available. The left shift srl 32// instructions shift all 64 bits, but it only accepts a 5-bit shift amount. 33// 34// The srl instructions only shift the low 32 bits and clear the high 32 bits. 35// Finally, sra shifts the low 32 bits and sign-extends to 64 bits. 36 37let Predicates = [Is64Bit] in { 38 39def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>; 40def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>; 41 42def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>; 43def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>; 44 45defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, shift_imm6, I64Regs>; 46defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, shift_imm6, I64Regs>; 47defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, shift_imm6, I64Regs>; 48 49} // Predicates = [Is64Bit] 50 51 52//===----------------------------------------------------------------------===// 53// 64-bit Immediates. 54//===----------------------------------------------------------------------===// 55// 56// All 32-bit immediates can be materialized with sethi+or, but 64-bit 57// immediates may require more code. There may be a point where it is 58// preferable to use a constant pool load instead, depending on the 59// microarchitecture. 60 61// Single-instruction patterns. 62 63// Zero immediate. 64def : Pat<(i64 0), (COPY (i64 G0))>, 65 Requires<[Is64Bit]>; 66 67// The ALU instructions want their simm13 operands as i32 immediates. 68def as_i32imm : SDNodeXForm<imm, [{ 69 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32); 70}]>; 71def : Pat<(i64 simm13:$val), (ORri (i64 G0), (as_i32imm $val))>; 72def : Pat<(i64 SETHIimm:$val), (SETHIi (HI22 $val))>; 73 74// Double-instruction patterns. 75 76// All unsigned i32 immediates can be handled by sethi+or. 77def uimm32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; 78def : Pat<(i64 uimm32:$val), (ORri (SETHIi (HI22 $val)), (LO10 $val))>, 79 Requires<[Is64Bit]>; 80 81// All negative i33 immediates can be handled by sethi+xor. 82def nimm33 : PatLeaf<(imm), [{ 83 int64_t Imm = N->getSExtValue(); 84 return Imm < 0 && isInt<33>(Imm); 85}]>; 86// Bits 10-31 inverted. Same as assembler's %hix. 87def HIX22 : SDNodeXForm<imm, [{ 88 uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1); 89 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 90}]>; 91// Bits 0-9 with ones in bits 10-31. Same as assembler's %lox. 92def LOX10 : SDNodeXForm<imm, [{ 93 return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N), 94 MVT::i32); 95}]>; 96def : Pat<(i64 nimm33:$val), (XORri (SETHIi (HIX22 $val)), (LOX10 $val))>, 97 Requires<[Is64Bit]>; 98 99// More possible patterns: 100// 101// (sllx sethi, n) 102// (sllx simm13, n) 103// 104// 3 instrs: 105// 106// (xor (sllx sethi), simm13) 107// (sllx (xor sethi, simm13)) 108// 109// 4 instrs: 110// 111// (or sethi, (sllx sethi)) 112// (xnor sethi, (sllx sethi)) 113// 114// 5 instrs: 115// 116// (or (sllx sethi), (or sethi, simm13)) 117// (xnor (sllx sethi), (or sethi, simm13)) 118// (or (sllx sethi), (sllx sethi)) 119// (xnor (sllx sethi), (sllx sethi)) 120// 121// Worst case is 6 instrs: 122// 123// (or (sllx (or sethi, simmm13)), (or sethi, simm13)) 124 125// Bits 42-63, same as assembler's %hh. 126def HH22 : SDNodeXForm<imm, [{ 127 uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1); 128 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 129}]>; 130// Bits 32-41, same as assembler's %hm. 131def HM10 : SDNodeXForm<imm, [{ 132 uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1); 133 return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32); 134}]>; 135def : Pat<(i64 imm:$val), 136 (ORrr (SLLXri (ORri (SETHIi (HH22 $val)), (HM10 $val)), (i32 32)), 137 (ORri (SETHIi (HI22 $val)), (LO10 $val)))>, 138 Requires<[Is64Bit]>; 139 140 141//===----------------------------------------------------------------------===// 142// 64-bit Integer Arithmetic and Logic. 143//===----------------------------------------------------------------------===// 144 145let Predicates = [Is64Bit] in { 146 147// Register-register instructions. 148let isCodeGenOnly = 1 in { 149defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>; 150defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>; 151defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>; 152 153def ANDXNrr : F3_1<2, 0b000101, 154 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 155 "andn $rs1, $rs2, $rd", 156 [(set i64:$rd, (and i64:$rs1, (not i64:$rs2)))]>; 157def ORXNrr : F3_1<2, 0b000110, 158 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 159 "orn $rs1, $rs2, $rd", 160 [(set i64:$rd, (or i64:$rs1, (not i64:$rs2)))]>; 161def XNORXrr : F3_1<2, 0b000111, 162 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 163 "xnor $rs1, $rs2, $rd", 164 [(set i64:$rd, (not (xor i64:$rs1, i64:$rs2)))]>; 165 166defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>; 167defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>; 168 169def TLS_ADDXrr : F3_1<2, 0b000000, (outs I64Regs:$rd), 170 (ins I64Regs:$rs1, I64Regs:$rs2, TailRelocSymTLSAdd:$sym), 171 "add $rs1, $rs2, $rd, $sym", 172 [(set i64:$rd, 173 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>; 174 175// "LEA" form of add 176def LEAX_ADDri : F3_2<2, 0b000000, 177 (outs I64Regs:$rd), (ins (MEMri $rs1, $simm13):$addr), 178 "add ${addr:arith}, $rd", 179 [(set iPTR:$rd, ADDRri:$addr)]>; 180} 181 182def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; 183def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; 184def : Pat<(i64 (ctpop i64:$src)), (POPCrr $src)>; 185 186} // Predicates = [Is64Bit] 187 188 189//===----------------------------------------------------------------------===// 190// 64-bit Integer Multiply and Divide. 191//===----------------------------------------------------------------------===// 192 193let Predicates = [Is64Bit] in { 194 195def MULXrr : F3_1<2, 0b001001, 196 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 197 "mulx $rs1, $rs2, $rd", 198 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>; 199def MULXri : F3_2<2, 0b001001, 200 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 201 "mulx $rs1, $simm13, $rd", 202 [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>; 203 204// Division can trap. 205let hasSideEffects = 1 in { 206def SDIVXrr : F3_1<2, 0b101101, 207 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 208 "sdivx $rs1, $rs2, $rd", 209 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>; 210def SDIVXri : F3_2<2, 0b101101, 211 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 212 "sdivx $rs1, $simm13, $rd", 213 [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>; 214 215def UDIVXrr : F3_1<2, 0b001101, 216 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2), 217 "udivx $rs1, $rs2, $rd", 218 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>; 219def UDIVXri : F3_2<2, 0b001101, 220 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13), 221 "udivx $rs1, $simm13, $rd", 222 [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>; 223} // hasSideEffects = 1 224 225} // Predicates = [Is64Bit] 226 227 228//===----------------------------------------------------------------------===// 229// 64-bit Loads and Stores. 230//===----------------------------------------------------------------------===// 231// 232// All the 32-bit loads and stores are available. The extending loads are sign 233// or zero-extending to 64 bits. The LDrr and LDri instructions load 32 bits 234// zero-extended to i64. Their mnemonic is lduw in SPARC v9 (Load Unsigned 235// Word). 236// 237// SPARC v9 adds 64-bit loads as well as a sign-extending ldsw i32 loads. 238 239let Predicates = [Is64Bit] in { 240 241// 64-bit loads. 242defm LDX : Load<"ldx", 0b001011, load, I64Regs, i64>; 243 244let mayLoad = 1, isAsmParserOnly = 1 in { 245 def TLS_LDXrr : F3_1<3, 0b001011, 246 (outs IntRegs:$rd), 247 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymTLSLoad:$sym), 248 "ldx [$addr], $rd, $sym", 249 [(set i64:$rd, 250 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>; 251 def GDOP_LDXrr : F3_1<3, 0b001011, 252 (outs I64Regs:$rd), 253 (ins (MEMrr $rs1, $rs2):$addr, TailRelocSymGOTLoad:$sym), 254 "ldx [$addr], $rd, $sym", 255 [(set i64:$rd, 256 (load_gdop ADDRrr:$addr, tglobaladdr:$sym))]>; 257} 258 259// Extending loads to i64. 260def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 261def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 262def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 263def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 264 265def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 266def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 267def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; 268def : Pat<(i64 (extloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; 269def : Pat<(i64 (sextloadi8 ADDRrr:$addr)), (LDSBrr ADDRrr:$addr)>; 270def : Pat<(i64 (sextloadi8 ADDRri:$addr)), (LDSBri ADDRri:$addr)>; 271 272def : Pat<(i64 (zextloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 273def : Pat<(i64 (zextloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 274def : Pat<(i64 (extloadi16 ADDRrr:$addr)), (LDUHrr ADDRrr:$addr)>; 275def : Pat<(i64 (extloadi16 ADDRri:$addr)), (LDUHri ADDRri:$addr)>; 276def : Pat<(i64 (sextloadi16 ADDRrr:$addr)), (LDSHrr ADDRrr:$addr)>; 277def : Pat<(i64 (sextloadi16 ADDRri:$addr)), (LDSHri ADDRri:$addr)>; 278 279def : Pat<(i64 (zextloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 280def : Pat<(i64 (zextloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 281def : Pat<(i64 (extloadi32 ADDRrr:$addr)), (LDrr ADDRrr:$addr)>; 282def : Pat<(i64 (extloadi32 ADDRri:$addr)), (LDri ADDRri:$addr)>; 283 284// Sign-extending load of i32 into i64 is a new SPARC v9 instruction. 285defm LDSW : Load<"ldsw", 0b001000, sextloadi32, I64Regs, i64>; 286 287// 64-bit stores. 288defm STX : Store<"stx", 0b001110, store, I64Regs, i64>; 289 290// Truncating stores from i64 are identical to the i32 stores. 291def : Pat<(truncstorei8 i64:$src, ADDRrr:$addr), (STBrr ADDRrr:$addr, $src)>; 292def : Pat<(truncstorei8 i64:$src, ADDRri:$addr), (STBri ADDRri:$addr, $src)>; 293def : Pat<(truncstorei16 i64:$src, ADDRrr:$addr), (STHrr ADDRrr:$addr, $src)>; 294def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>; 295def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>; 296def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>; 297 298// store 0, addr -> store %g0, addr 299def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>; 300def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>; 301 302} // Predicates = [Is64Bit] 303 304 305//===----------------------------------------------------------------------===// 306// 64-bit Conditionals. 307//===----------------------------------------------------------------------===// 308 309// 310// Flag-setting instructions like subcc and addcc set both icc and xcc flags. 311// The icc flags correspond to the 32-bit result, and the xcc are for the 312// full 64-bit result. 313// 314// We reuse CMPICC SDNodes for compares, but use new BPXCC branch nodes for 315// 64-bit compares. See LowerBR_CC. 316 317let Predicates = [Is64Bit] in { 318 319let Uses = [ICC], cc = 0b10 in 320 defm BPX : IPredBranch<"%xcc", [(SPbpxcc bb:$imm19, imm:$cond)]>; 321 322// Conditional moves on %xcc. 323let Uses = [ICC], Constraints = "$f = $rd" in { 324let intcc = 1, cc = 0b10 in { 325def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd), 326 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond), 327 "mov$cond %xcc, $rs2, $rd", 328 [(set i32:$rd, 329 (SPselectxcc i32:$rs2, i32:$f, imm:$cond))]>; 330def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd), 331 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond), 332 "mov$cond %xcc, $simm11, $rd", 333 [(set i32:$rd, 334 (SPselectxcc simm11:$simm11, i32:$f, imm:$cond))]>; 335} // cc 336 337let intcc = 1, opf_cc = 0b10 in { 338def FMOVS_XCC : F4_3<0b110101, 0b000001, (outs FPRegs:$rd), 339 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), 340 "fmovs$cond %xcc, $rs2, $rd", 341 [(set f32:$rd, 342 (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; 343def FMOVD_XCC : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd), 344 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), 345 "fmovd$cond %xcc, $rs2, $rd", 346 [(set f64:$rd, 347 (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; 348let Predicates = [Is64Bit, HasHardQuad] in 349def FMOVQ_XCC : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd), 350 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond), 351 "fmovq$cond %xcc, $rs2, $rd", 352 [(set f128:$rd, 353 (SPselectxcc f128:$rs2, f128:$f, imm:$cond))]>; 354} // opf_cc 355} // Uses, Constraints 356 357// Branch On integer register with Prediction (BPr). 358let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in 359multiclass BranchOnReg<list<dag> CCPattern> { 360 def R : F2_4<0, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 361 "br$rcond $rs1, $imm16", CCPattern>; 362 def RA : F2_4<1, 1, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 363 "br$rcond,a $rs1, $imm16", []>; 364 def RNT : F2_4<0, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 365 "br$rcond,pn $rs1, $imm16", []>; 366 def RANT : F2_4<1, 0, (outs), (ins bprtarget16:$imm16, RegCCOp:$rcond, I64Regs:$rs1), 367 "br$rcond,a,pn $rs1, $imm16", []>; 368} 369 370multiclass bpr_alias<string OpcStr, Instruction NAPT, Instruction APT> { 371 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"), 372 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>; 373 def : InstAlias<!strconcat(OpcStr, ",a,pt $rs1, $imm16"), 374 (APT I64Regs:$rs1, bprtarget16:$imm16), 0>; 375} 376 377let Predicates = [Is64Bit] in 378 defm BP : BranchOnReg<[(SPbrreg bb:$imm16, imm:$rcond, i64:$rs1)]>; 379 380// Move integer register on register condition (MOVr). 381let Predicates = [Is64Bit], Constraints = "$f = $rd" in { 382 def MOVRrr : F4_4r<0b101111, 0b00000, (outs IntRegs:$rd), 383 (ins I64Regs:$rs1, IntRegs:$rs2, IntRegs:$f, RegCCOp:$rcond), 384 "movr$rcond $rs1, $rs2, $rd", 385 [(set i32:$rd, (SPselectreg i32:$rs2, i32:$f, imm:$rcond, i64:$rs1))]>; 386 387 def MOVRri : F4_4i<0b101111, (outs IntRegs:$rd), 388 (ins I64Regs:$rs1, i32imm:$simm10, IntRegs:$f, RegCCOp:$rcond), 389 "movr$rcond $rs1, $simm10, $rd", 390 [(set i32:$rd, (SPselectreg simm10:$simm10, i32:$f, imm:$rcond, i64:$rs1))]>; 391} 392 393// Move FP register on integer register condition (FMOVr). 394let Predicates = [Is64Bit], Constraints = "$f = $rd" in { 395 def FMOVRS : F4_4r<0b110101, 0b00101, 396 (outs FPRegs:$rd), (ins I64Regs:$rs1, FPRegs:$rs2, FPRegs:$f, RegCCOp:$rcond), 397 "fmovrs$rcond $rs1, $rs2, $rd", 398 [(set f32:$rd, (SPselectreg f32:$rs2, f32:$f, imm:$rcond, i64:$rs1))]>; 399 def FMOVRD : F4_4r<0b110101, 0b00110, 400 (outs DFPRegs:$rd), (ins I64Regs:$rs1, DFPRegs:$rs2, DFPRegs:$f, RegCCOp:$rcond), 401 "fmovrd$rcond $rs1, $rs2, $rd", 402 [(set f64:$rd, (SPselectreg f64:$rs2, f64:$f, imm:$rcond, i64:$rs1))]>; 403 let Predicates = [HasHardQuad] in 404 def FMOVRQ : F4_4r<0b110101, 0b00111, 405 (outs QFPRegs:$rd), (ins I64Regs:$rs1, QFPRegs:$rs2, QFPRegs:$f, RegCCOp:$rcond), 406 "fmovrq$rcond $rs1, $rs2, $rd", 407 [(set f128:$rd, (SPselectreg f128:$rs2, f128:$f, imm:$rcond, i64:$rs1))]>; 408} 409 410//===----------------------------------------------------------------------===// 411// 64-bit Floating Point Conversions. 412//===----------------------------------------------------------------------===// 413 414let Predicates = [Is64Bit] in { 415 416def FXTOS : F3_3u<2, 0b110100, 0b010000100, 417 (outs FPRegs:$rd), (ins DFPRegs:$rs2), 418 "fxtos $rs2, $rd", 419 [(set FPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 420def FXTOD : F3_3u<2, 0b110100, 0b010001000, 421 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 422 "fxtod $rs2, $rd", 423 [(set DFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 424let Predicates = [Is64Bit, HasHardQuad] in 425def FXTOQ : F3_3u<2, 0b110100, 0b010001100, 426 (outs QFPRegs:$rd), (ins DFPRegs:$rs2), 427 "fxtoq $rs2, $rd", 428 [(set QFPRegs:$rd, (SPxtof DFPRegs:$rs2))]>; 429 430def FSTOX : F3_3u<2, 0b110100, 0b010000001, 431 (outs DFPRegs:$rd), (ins FPRegs:$rs2), 432 "fstox $rs2, $rd", 433 [(set DFPRegs:$rd, (SPftox FPRegs:$rs2))]>; 434def FDTOX : F3_3u<2, 0b110100, 0b010000010, 435 (outs DFPRegs:$rd), (ins DFPRegs:$rs2), 436 "fdtox $rs2, $rd", 437 [(set DFPRegs:$rd, (SPftox DFPRegs:$rs2))]>; 438let Predicates = [Is64Bit, HasHardQuad] in 439def FQTOX : F3_3u<2, 0b110100, 0b010000011, 440 (outs DFPRegs:$rd), (ins QFPRegs:$rs2), 441 "fqtox $rs2, $rd", 442 [(set DFPRegs:$rd, (SPftox QFPRegs:$rs2))]>; 443 444} // Predicates = [Is64Bit] 445 446def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), 447 (MOVXCCrr $t, $f, imm:$cond)>; 448def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond), 449 (MOVXCCri (as_i32imm $t), $f, imm:$cond)>; 450 451def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond), 452 (MOVICCrr $t, $f, imm:$cond)>; 453def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond), 454 (MOVICCri (as_i32imm $t), $f, imm:$cond)>; 455 456def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond), 457 (MOVFCCrr $t, $f, imm:$cond)>; 458def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond), 459 (MOVFCCri (as_i32imm $t), $f, imm:$cond)>; 460 461def : Pat<(SPselectreg i64:$t, i64:$f, imm:$rcond, i64:$rs1), 462 (MOVRrr $rs1, $t, $f, imm:$rcond)>; 463def : Pat<(SPselectreg (i64 simm10:$t), i64:$f, imm:$rcond, i64:$rs1), 464 (MOVRri $rs1, (as_i32imm $t), $f, imm:$rcond)>; 465 466} // Predicates = [Is64Bit] 467 468 469// 64 bit SETHI 470let Predicates = [Is64Bit], isCodeGenOnly = 1 in { 471def SETHIXi : F2_1<0b100, 472 (outs IntRegs:$rd), (ins i64imm:$imm22), 473 "sethi $imm22, $rd", 474 [(set i64:$rd, SETHIimm:$imm22)]>; 475} 476 477// ATOMICS. 478let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in { 479 def CASXrr: F3_1_asi<3, 0b111110, 480 (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2, 481 I64Regs:$swap), 482 "casx [$rs1], $rs2, $rd", 483 [(set i64:$rd, 484 (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>; 485 486} // Predicates = [Is64Bit], Constraints = ... 487 488let Predicates = [Is64Bit] in { 489 490// atomic_load_64 addr -> load addr 491def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>; 492def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>; 493 494// atomic_store_64 val, addr -> store val, addr 495def : Pat<(atomic_store_64 ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>; 496def : Pat<(atomic_store_64 ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>; 497 498} // Predicates = [Is64Bit] 499 500let Predicates = [Is64Bit], hasSideEffects = 1, Uses = [ICC], cc = 0b10 in 501 defm TXCC : TRAP<"%xcc">; 502 503// Global addresses, constant pool entries 504let Predicates = [Is64Bit] in { 505 506def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 507def : Pat<(SPlo tglobaladdr:$in), (ORXri (i64 G0), tglobaladdr:$in)>; 508def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 509def : Pat<(SPlo tconstpool:$in), (ORXri (i64 G0), tconstpool:$in)>; 510 511// GlobalTLS addresses 512def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>; 513def : Pat<(SPlo tglobaltlsaddr:$in), (ORXri (i64 G0), tglobaltlsaddr:$in)>; 514def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 515 (ADDXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 516def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)), 517 (XORXri (SETHIXi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>; 518 519// Blockaddress 520def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>; 521def : Pat<(SPlo tblockaddress:$in), (ORXri (i64 G0), tblockaddress:$in)>; 522 523// Add reg, lo. This is used when taking the addr of a global/constpool entry. 524def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDXri $r, tglobaladdr:$in)>; 525def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDXri $r, tconstpool:$in)>; 526def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)), 527 (ADDXri $r, tblockaddress:$in)>; 528} 529