1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that Sparc uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 15 #define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H 16 17 #include "Sparc.h" 18 #include "llvm/CodeGen/TargetLowering.h" 19 20 namespace llvm { 21 class SparcSubtarget; 22 23 namespace SPISD { 24 enum NodeType : unsigned { 25 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 CMPICC, // Compare two GPR operands, set icc+xcc. 27 CMPFCC, // Compare two FP operands, set fcc. 28 CMPFCC_V9, // Compare two FP operands, set fcc (v9 variant). 29 BRICC, // Branch to dest on icc condition 30 BPICC, // Branch to dest on icc condition, with prediction (64-bit only). 31 BPXCC, // Branch to dest on xcc condition, with prediction (64-bit only). 32 BRFCC, // Branch to dest on fcc condition 33 BRFCC_V9, // Branch to dest on fcc condition (v9 variant). 34 BR_REG, // Branch to dest using the comparison of a register with zero. 35 SELECT_ICC, // Select between two values using the current ICC flags. 36 SELECT_XCC, // Select between two values using the current XCC flags. 37 SELECT_FCC, // Select between two values using the current FCC flags. 38 SELECT_REG, // Select between two values using the comparison of a register 39 // with zero. 40 41 Hi, 42 Lo, // Hi/Lo operations, typically on a global address. 43 44 FTOI, // FP to Int within a FP register. 45 ITOF, // Int to FP within a FP register. 46 FTOX, // FP to Int64 within a FP register. 47 XTOF, // Int64 to FP within a FP register. 48 49 CALL, // A call instruction. 50 RET_GLUE, // Return with a glue operand. 51 GLOBAL_BASE_REG, // Global base reg for PIC. 52 FLUSHW, // FLUSH register windows to stack. 53 54 TAIL_CALL, // Tail call 55 56 TLS_ADD, // For Thread Local Storage (TLS). 57 TLS_LD, 58 TLS_CALL, 59 60 LOAD_GDOP, // Load operation w/ gdop relocation. 61 }; 62 } 63 64 class SparcTargetLowering : public TargetLowering { 65 const SparcSubtarget *Subtarget; 66 public: 67 SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI); 68 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 69 70 bool useSoftFloat() const override; 71 72 /// computeKnownBitsForTargetNode - Determine which of the bits specified 73 /// in Mask are known to be either zero or one and return them in the 74 /// KnownZero/KnownOne bitsets. 75 void computeKnownBitsForTargetNode(const SDValue Op, 76 KnownBits &Known, 77 const APInt &DemandedElts, 78 const SelectionDAG &DAG, 79 unsigned Depth = 0) const override; 80 81 MachineBasicBlock * 82 EmitInstrWithCustomInserter(MachineInstr &MI, 83 MachineBasicBlock *MBB) const override; 84 85 const char *getTargetNodeName(unsigned Opcode) const override; 86 87 ConstraintType getConstraintType(StringRef Constraint) const override; 88 ConstraintWeight 89 getSingleConstraintMatchWeight(AsmOperandInfo &info, 90 const char *constraint) const override; 91 void LowerAsmOperandForConstraint(SDValue Op, 92 std::string &Constraint, 93 std::vector<SDValue> &Ops, 94 SelectionDAG &DAG) const override; 95 96 std::pair<unsigned, const TargetRegisterClass *> 97 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 98 StringRef Constraint, MVT VT) const override; 99 100 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 101 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 102 return MVT::i32; 103 } 104 105 Register getRegisterByName(const char* RegName, LLT VT, 106 const MachineFunction &MF) const override; 107 108 /// If a physical register, this returns the register that receives the 109 /// exception address on entry to an EH pad. 110 Register 111 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 112 return SP::I0; 113 } 114 115 /// If a physical register, this returns the register that receives the 116 /// exception typeid on entry to a landing pad. 117 Register 118 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 119 return SP::I1; 120 } 121 122 /// Override to support customized stack guard loading. 123 bool useLoadStackGuardNode() const override; 124 void insertSSPDeclarations(Module &M) const override; 125 126 /// getSetCCResultType - Return the ISD::SETCC ValueType 127 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 128 EVT VT) const override; 129 130 SDValue 131 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 132 const SmallVectorImpl<ISD::InputArg> &Ins, 133 const SDLoc &dl, SelectionDAG &DAG, 134 SmallVectorImpl<SDValue> &InVals) const override; 135 SDValue LowerFormalArguments_32(SDValue Chain, CallingConv::ID CallConv, 136 bool isVarArg, 137 const SmallVectorImpl<ISD::InputArg> &Ins, 138 const SDLoc &dl, SelectionDAG &DAG, 139 SmallVectorImpl<SDValue> &InVals) const; 140 SDValue LowerFormalArguments_64(SDValue Chain, CallingConv::ID CallConv, 141 bool isVarArg, 142 const SmallVectorImpl<ISD::InputArg> &Ins, 143 const SDLoc &dl, SelectionDAG &DAG, 144 SmallVectorImpl<SDValue> &InVals) const; 145 146 SDValue 147 LowerCall(TargetLowering::CallLoweringInfo &CLI, 148 SmallVectorImpl<SDValue> &InVals) const override; 149 SDValue LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 150 SmallVectorImpl<SDValue> &InVals) const; 151 SDValue LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 152 SmallVectorImpl<SDValue> &InVals) const; 153 154 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 155 bool isVarArg, 156 const SmallVectorImpl<ISD::OutputArg> &Outs, 157 LLVMContext &Context) const override; 158 159 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 160 const SmallVectorImpl<ISD::OutputArg> &Outs, 161 const SmallVectorImpl<SDValue> &OutVals, 162 const SDLoc &dl, SelectionDAG &DAG) const override; 163 SDValue LowerReturn_32(SDValue Chain, CallingConv::ID CallConv, 164 bool IsVarArg, 165 const SmallVectorImpl<ISD::OutputArg> &Outs, 166 const SmallVectorImpl<SDValue> &OutVals, 167 const SDLoc &DL, SelectionDAG &DAG) const; 168 SDValue LowerReturn_64(SDValue Chain, CallingConv::ID CallConv, 169 bool IsVarArg, 170 const SmallVectorImpl<ISD::OutputArg> &Outs, 171 const SmallVectorImpl<SDValue> &OutVals, 172 const SDLoc &DL, SelectionDAG &DAG) const; 173 174 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 175 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 176 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 177 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 178 179 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 180 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 181 SelectionDAG &DAG) const; 182 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 183 184 SDValue LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, SDValue Arg, 185 const SDLoc &DL, SelectionDAG &DAG) const; 186 SDValue LowerF128Op(SDValue Op, SelectionDAG &DAG, 187 const char *LibFuncName, 188 unsigned numArgs) const; 189 SDValue LowerF128Compare(SDValue LHS, SDValue RHS, unsigned &SPCC, 190 const SDLoc &DL, SelectionDAG &DAG) const; 191 192 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 193 194 SDValue PerformBITCASTCombine(SDNode *N, DAGCombinerInfo &DCI) const; 195 196 SDValue bitcastConstantFPToInt(ConstantFPSDNode *C, const SDLoc &DL, 197 SelectionDAG &DAG) const; 198 199 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 200 201 bool IsEligibleForTailCallOptimization(CCState &CCInfo, 202 CallLoweringInfo &CLI, 203 MachineFunction &MF) const; 204 205 bool ShouldShrinkFPConstant(EVT VT) const override { 206 // Do not shrink FP constpool if VT == MVT::f128. 207 // (ldd, call _Q_fdtoq) is more expensive than two ldds. 208 return VT != MVT::f128; 209 } 210 211 bool shouldInsertFencesForAtomic(const Instruction *I) const override { 212 // FIXME: We insert fences for each atomics and generate 213 // sub-optimal code for PSO/TSO. (Approximately nobody uses any 214 // mode but TSO, which makes this even more silly) 215 return true; 216 } 217 218 AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 219 220 void ReplaceNodeResults(SDNode *N, 221 SmallVectorImpl<SDValue>& Results, 222 SelectionDAG &DAG) const override; 223 224 MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, 225 unsigned BROpcode) const; 226 }; 227 } // end namespace llvm 228 229 #endif // SPARC_ISELLOWERING_H 230