xref: /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/SparcFrameLowering.cpp (revision 85868e8a1daeaae7a0e48effb2ea2310ae3b02c6)
1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the Sparc implementation of TargetFrameLowering class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SparcFrameLowering.h"
14 #include "SparcInstrInfo.h"
15 #include "SparcMachineFunctionInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Target/TargetOptions.h"
26 
27 using namespace llvm;
28 
29 static cl::opt<bool>
30 DisableLeafProc("disable-sparc-leaf-proc",
31                 cl::init(false),
32                 cl::desc("Disable Sparc leaf procedure optimization."),
33                 cl::Hidden);
34 
35 SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
36     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
37                           ST.is64Bit() ? Align(16) : Align(8), 0,
38                           ST.is64Bit() ? Align(16) : Align(8)) {}
39 
40 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
41                                           MachineBasicBlock &MBB,
42                                           MachineBasicBlock::iterator MBBI,
43                                           int NumBytes,
44                                           unsigned ADDrr,
45                                           unsigned ADDri) const {
46 
47   DebugLoc dl;
48   const SparcInstrInfo &TII =
49       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
50 
51   if (NumBytes >= -4096 && NumBytes < 4096) {
52     BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53       .addReg(SP::O6).addImm(NumBytes);
54     return;
55   }
56 
57   // Emit this the hard way.  This clobbers G1 which we always know is
58   // available here.
59   if (NumBytes >= 0) {
60     // Emit nonnegative numbers with sethi + or.
61     // sethi %hi(NumBytes), %g1
62     // or %g1, %lo(NumBytes), %g1
63     // add %sp, %g1, %sp
64     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
65       .addImm(HI22(NumBytes));
66     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67       .addReg(SP::G1).addImm(LO10(NumBytes));
68     BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69       .addReg(SP::O6).addReg(SP::G1);
70     return ;
71   }
72 
73   // Emit negative numbers with sethi + xor.
74   // sethi %hix(NumBytes), %g1
75   // xor %g1, %lox(NumBytes), %g1
76   // add %sp, %g1, %sp
77   BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
78     .addImm(HIX22(NumBytes));
79   BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80     .addReg(SP::G1).addImm(LOX10(NumBytes));
81   BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82     .addReg(SP::O6).addReg(SP::G1);
83 }
84 
85 void SparcFrameLowering::emitPrologue(MachineFunction &MF,
86                                       MachineBasicBlock &MBB) const {
87   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
88 
89   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
90   MachineFrameInfo &MFI = MF.getFrameInfo();
91   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
92   const SparcInstrInfo &TII =
93       *static_cast<const SparcInstrInfo *>(Subtarget.getInstrInfo());
94   const SparcRegisterInfo &RegInfo =
95       *static_cast<const SparcRegisterInfo *>(Subtarget.getRegisterInfo());
96   MachineBasicBlock::iterator MBBI = MBB.begin();
97   // Debug location must be unknown since the first debug location is used
98   // to determine the end of the prologue.
99   DebugLoc dl;
100   bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
101 
102   // FIXME: unfortunately, returning false from canRealignStack
103   // actually just causes needsStackRealignment to return false,
104   // rather than reporting an error, as would be sensible. This is
105   // poor, but fixing that bogosity is going to be a large project.
106   // For now, just see if it's lied, and report an error here.
107   if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment())
108     report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
109                        "stack re-alignment, but LLVM couldn't handle it "
110                        "(probably because it has a dynamic alloca).");
111 
112   // Get the number of bytes to allocate from the FrameInfo
113   int NumBytes = (int) MFI.getStackSize();
114 
115   unsigned SAVEri = SP::SAVEri;
116   unsigned SAVErr = SP::SAVErr;
117   if (FuncInfo->isLeafProc()) {
118     if (NumBytes == 0)
119       return;
120     SAVEri = SP::ADDri;
121     SAVErr = SP::ADDrr;
122   }
123 
124   // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
125   // (128 in v9) area in the user's stack, starting at %sp. Thus, the
126   // first part of the stack that can actually be used is located at
127   // %sp + 92.
128   //
129   // We therefore need to add that offset to the total stack size
130   // after all the stack objects are placed by
131   // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
132   // aligned *after* the extra size is added, we need to disable
133   // calculateFrameObjectOffsets's built-in stack alignment, by having
134   // targetHandlesStackFrameRounding return true.
135 
136 
137   // Add the extra call frame stack size, if needed. (This is the same
138   // code as in PrologEpilogInserter, but also gets disabled by
139   // targetHandlesStackFrameRounding)
140   if (MFI.adjustsStack() && hasReservedCallFrame(MF))
141     NumBytes += MFI.getMaxCallFrameSize();
142 
143   // Adds the SPARC subtarget-specific spill area to the stack
144   // size. Also ensures target-required alignment.
145   NumBytes = Subtarget.getAdjustedFrameSize(NumBytes);
146 
147   // Finally, ensure that the size is sufficiently aligned for the
148   // data on the stack.
149   if (MFI.getMaxAlignment() > 0) {
150     NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());
151   }
152 
153   // Update stack size with corrected value.
154   MFI.setStackSize(NumBytes);
155 
156   emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
157 
158   unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
159 
160   // Emit ".cfi_def_cfa_register 30".
161   unsigned CFIIndex =
162       MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
163   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
164       .addCFIIndex(CFIIndex);
165 
166   // Emit ".cfi_window_save".
167   CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
168   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
169       .addCFIIndex(CFIIndex);
170 
171   unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
172   unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
173   // Emit ".cfi_register 15, 31".
174   CFIIndex = MF.addFrameInst(
175       MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
176   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
177       .addCFIIndex(CFIIndex);
178 
179   if (NeedsStackRealignment) {
180     int64_t Bias = Subtarget.getStackPointerBias();
181     unsigned regUnbiased;
182     if (Bias) {
183       // This clobbers G1 which we always know is available here.
184       regUnbiased = SP::G1;
185       // add %o6, BIAS, %g1
186       BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
187         .addReg(SP::O6).addImm(Bias);
188     } else
189       regUnbiased = SP::O6;
190 
191     // andn %regUnbiased, MaxAlign-1, %regUnbiased
192     int MaxAlign = MFI.getMaxAlignment();
193     BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
194       .addReg(regUnbiased).addImm(MaxAlign - 1);
195 
196     if (Bias) {
197       // add %g1, -BIAS, %o6
198       BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
199         .addReg(regUnbiased).addImm(-Bias);
200     }
201   }
202 }
203 
204 MachineBasicBlock::iterator SparcFrameLowering::
205 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
206                               MachineBasicBlock::iterator I) const {
207   if (!hasReservedCallFrame(MF)) {
208     MachineInstr &MI = *I;
209     int Size = MI.getOperand(0).getImm();
210     if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
211       Size = -Size;
212 
213     if (Size)
214       emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
215   }
216   return MBB.erase(I);
217 }
218 
219 
220 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
221                                   MachineBasicBlock &MBB) const {
222   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
223   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
224   const SparcInstrInfo &TII =
225       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
226   DebugLoc dl = MBBI->getDebugLoc();
227   assert(MBBI->getOpcode() == SP::RETL &&
228          "Can only put epilog before 'retl' instruction!");
229   if (!FuncInfo->isLeafProc()) {
230     BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
231       .addReg(SP::G0);
232     return;
233   }
234   MachineFrameInfo &MFI = MF.getFrameInfo();
235 
236   int NumBytes = (int) MFI.getStackSize();
237   if (NumBytes == 0)
238     return;
239 
240   emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
241 }
242 
243 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
244   // Reserve call frame if there are no variable sized objects on the stack.
245   return !MF.getFrameInfo().hasVarSizedObjects();
246 }
247 
248 // hasFP - Return true if the specified function should have a dedicated frame
249 // pointer register.  This is true if the function has variable sized allocas or
250 // if frame pointer elimination is disabled.
251 bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
252   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
253 
254   const MachineFrameInfo &MFI = MF.getFrameInfo();
255   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
256       RegInfo->needsStackRealignment(MF) ||
257       MFI.hasVarSizedObjects() ||
258       MFI.isFrameAddressTaken();
259 }
260 
261 
262 int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
263                                                unsigned &FrameReg) const {
264   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
265   const MachineFrameInfo &MFI = MF.getFrameInfo();
266   const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
267   const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
268   bool isFixed = MFI.isFixedObjectIndex(FI);
269 
270   // Addressable stack objects are accessed using neg. offsets from
271   // %fp, or positive offsets from %sp.
272   bool UseFP;
273 
274   // Sparc uses FP-based references in general, even when "hasFP" is
275   // false. That function is rather a misnomer, because %fp is
276   // actually always available, unless isLeafProc.
277   if (FuncInfo->isLeafProc()) {
278     // If there's a leaf proc, all offsets need to be %sp-based,
279     // because we haven't caused %fp to actually point to our frame.
280     UseFP = false;
281   } else if (isFixed) {
282     // Otherwise, argument access should always use %fp.
283     UseFP = true;
284   } else if (RegInfo->needsStackRealignment(MF)) {
285     // If there is dynamic stack realignment, all local object
286     // references need to be via %sp, to take account of the
287     // re-alignment.
288     UseFP = false;
289   } else {
290     // Finally, default to using %fp.
291     UseFP = true;
292   }
293 
294   int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) +
295       Subtarget.getStackPointerBias();
296 
297   if (UseFP) {
298     FrameReg = RegInfo->getFrameRegister(MF);
299     return FrameOffset;
300   } else {
301     FrameReg = SP::O6; // %sp
302     return FrameOffset + MF.getFrameInfo().getStackSize();
303   }
304 }
305 
306 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
307 {
308 
309   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
310     if (MRI->isPhysRegUsed(reg))
311       return false;
312 
313   for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
314     if (MRI->isPhysRegUsed(reg))
315       return false;
316 
317   return true;
318 }
319 
320 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
321 {
322 
323   MachineRegisterInfo &MRI = MF.getRegInfo();
324   MachineFrameInfo    &MFI = MF.getFrameInfo();
325 
326   return !(MFI.hasCalls()                  // has calls
327            || MRI.isPhysRegUsed(SP::L0)    // Too many registers needed
328            || MRI.isPhysRegUsed(SP::O6)    // %sp is used
329            || hasFP(MF));                  // need %fp
330 }
331 
332 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
333   MachineRegisterInfo &MRI = MF.getRegInfo();
334   // Remap %i[0-7] to %o[0-7].
335   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
336     if (!MRI.isPhysRegUsed(reg))
337       continue;
338 
339     unsigned mapped_reg = reg - SP::I0 + SP::O0;
340 
341     // Replace I register with O register.
342     MRI.replaceRegWith(reg, mapped_reg);
343 
344     // Also replace register pair super-registers.
345     if ((reg - SP::I0) % 2 == 0) {
346       unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
347       unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
348       MRI.replaceRegWith(preg, mapped_preg);
349     }
350   }
351 
352   // Rewrite MBB's Live-ins.
353   for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
354        MBB != E; ++MBB) {
355     for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
356       if (!MBB->isLiveIn(reg))
357         continue;
358       MBB->removeLiveIn(reg);
359       MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
360     }
361     for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
362       if (!MBB->isLiveIn(reg))
363         continue;
364       MBB->removeLiveIn(reg);
365       MBB->addLiveIn(reg - SP::I0 + SP::O0);
366     }
367   }
368 
369   assert(verifyLeafProcRegUse(&MRI));
370 #ifdef EXPENSIVE_CHECKS
371   MF.verify(0, "After LeafProc Remapping");
372 #endif
373 }
374 
375 void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
376                                               BitVector &SavedRegs,
377                                               RegScavenger *RS) const {
378   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
379   if (!DisableLeafProc && isLeafProc(MF)) {
380     SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
381     MFI->setLeafProc(true);
382 
383     remapRegsForLeafProc(MF);
384   }
385 
386 }
387