1//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// SPARC Subtarget features. 20// 21 22def FeatureSoftMulDiv 23 : SubtargetFeature<"soft-mul-div", "UseSoftMulDiv", "true", 24 "Use software emulation for integer multiply and divide">; 25 26def FeatureNoFSMULD 27 : SubtargetFeature<"no-fsmuld", "HasNoFSMULD", "true", 28 "Disable the fsmuld instruction.">; 29def FeatureNoFMULS 30 : SubtargetFeature<"no-fmuls", "HasNoFMULS", "true", 31 "Disable the fmuls instruction.">; 32 33def FeatureV9 34 : SubtargetFeature<"v9", "IsV9", "true", 35 "Enable SPARC-V9 instructions">; 36def FeatureV8Deprecated 37 : SubtargetFeature<"deprecated-v8", "UseV8DeprecatedInsts", "true", 38 "Enable deprecated V8 instructions in V9 mode">; 39def FeatureVIS 40 : SubtargetFeature<"vis", "IsVIS", "true", 41 "Enable UltraSPARC Visual Instruction Set extensions">; 42def FeatureVIS2 43 : SubtargetFeature<"vis2", "IsVIS2", "true", 44 "Enable Visual Instruction Set extensions II">; 45def FeatureVIS3 46 : SubtargetFeature<"vis3", "IsVIS3", "true", 47 "Enable Visual Instruction Set extensions III">; 48def FeatureLeon 49 : SubtargetFeature<"leon", "IsLeon", "true", 50 "Enable LEON extensions">; 51def FeaturePWRPSR 52 : SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true", 53 "Enable the PWRPSR instruction">; 54 55def FeatureHardQuad 56 : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", 57 "Enable quad-word floating point instructions">; 58 59def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", 60 "Use the popc (population count) instruction">; 61 62def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 63 "Use software emulation for floating point">; 64 65//===----------------------------------------------------------------------===// 66// SPARC Subtarget tuning features. 67// 68 69def TuneSlowRDPC : SubtargetFeature<"slow-rdpc", "HasSlowRDPC", "true", 70 "rd %pc, %XX is slow", [FeatureV9]>; 71 72//==== Features added predmoninantly for LEON subtarget support 73include "LeonFeatures.td" 74 75//==== Register allocation tweaks needed by some low-level software 76foreach i = 1 ... 7 in 77 def FeatureReserveG#i : SubtargetFeature<"reserve-g"#i, "ReserveRegister["#i#" + SP::G0]", "true", 78 "Reserve G"#i#", making it unavailable as a GPR">; 79foreach i = 0 ... 5 in 80 def FeatureReserveO#i : SubtargetFeature<"reserve-o"#i, "ReserveRegister["#i#" + SP::O0]", "true", 81 "Reserve O"#i#", making it unavailable as a GPR">; 82foreach i = 0 ... 7 in 83 def FeatureReserveL#i : SubtargetFeature<"reserve-l"#i, "ReserveRegister["#i#" + SP::L0]", "true", 84 "Reserve L"#i#", making it unavailable as a GPR">; 85foreach i = 0 ... 5 in 86 def FeatureReserveI#i : SubtargetFeature<"reserve-i"#i, "ReserveRegister["#i#" + SP::I0]", "true", 87 "Reserve I"#i#", making it unavailable as a GPR">; 88 89//===----------------------------------------------------------------------===// 90// Register File, Calling Conv, Instruction Descriptions 91//===----------------------------------------------------------------------===// 92 93include "SparcASITags.td" 94include "SparcRegisterInfo.td" 95include "SparcCallingConv.td" 96include "SparcSchedule.td" 97include "SparcInstrInfo.td" 98 99def SparcInstrInfo : InstrInfo; 100 101def SparcAsmParser : AsmParser { 102 bit ShouldEmitMatchRegisterName = 0; 103} 104 105def SparcAsmParserVariant : AsmParserVariant { 106 let RegisterPrefix = "%"; 107} 108 109//===----------------------------------------------------------------------===// 110// SPARC processors supported. 111//===----------------------------------------------------------------------===// 112 113class Proc<string Name, list<SubtargetFeature> Features, 114 list<SubtargetFeature> TuneFeatures = []> 115 : Processor<Name, NoItineraries, Features, TuneFeatures>; 116 117def : Proc<"generic", []>; 118def : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>; 119def : Proc<"v8", []>; 120def : Proc<"supersparc", []>; 121def : Proc<"sparclite", []>; 122def : Proc<"f934", []>; 123def : Proc<"hypersparc", []>; 124def : Proc<"sparclite86x", []>; 125def : Proc<"sparclet", []>; 126def : Proc<"tsc701", []>; 127def : Proc<"myriad2", [FeatureLeon, LeonCASA]>; 128def : Proc<"myriad2.1", [FeatureLeon, LeonCASA]>; 129def : Proc<"myriad2.2", [FeatureLeon, LeonCASA]>; 130def : Proc<"myriad2.3", [FeatureLeon, LeonCASA]>; 131def : Proc<"ma2100", [FeatureLeon, LeonCASA]>; 132def : Proc<"ma2150", [FeatureLeon, LeonCASA]>; 133def : Proc<"ma2155", [FeatureLeon, LeonCASA]>; 134def : Proc<"ma2450", [FeatureLeon, LeonCASA]>; 135def : Proc<"ma2455", [FeatureLeon, LeonCASA]>; 136def : Proc<"ma2x5x", [FeatureLeon, LeonCASA]>; 137def : Proc<"ma2080", [FeatureLeon, LeonCASA]>; 138def : Proc<"ma2085", [FeatureLeon, LeonCASA]>; 139def : Proc<"ma2480", [FeatureLeon, LeonCASA]>; 140def : Proc<"ma2485", [FeatureLeon, LeonCASA]>; 141def : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; 142def : Proc<"v9", [FeatureV9]>; 143def : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS], 144 [TuneSlowRDPC]>; 145def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, 146 FeatureVIS2], 147 [TuneSlowRDPC]>; 148def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, 149 FeatureVIS2]>; 150def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, 151 FeatureVIS, FeatureVIS2]>; 152def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, 153 FeatureVIS, FeatureVIS2]>; 154def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, 155 FeatureVIS, FeatureVIS2, FeatureVIS3]>; 156 157// LEON 2 FT generic 158def : Processor<"leon2", LEON2Itineraries, 159 [FeatureLeon]>; 160 161// LEON 2 FT (AT697E) 162// TO DO: Place-holder: Processor specific features will be added *very* soon here. 163def : Processor<"at697e", LEON2Itineraries, 164 [FeatureLeon, InsertNOPLoad]>; 165 166// LEON 2 FT (AT697F) 167// TO DO: Place-holder: Processor specific features will be added *very* soon here. 168def : Processor<"at697f", LEON2Itineraries, 169 [FeatureLeon, InsertNOPLoad]>; 170 171 172// LEON 3 FT generic 173def : Processor<"leon3", LEON3Itineraries, 174 [FeatureLeon, UMACSMACSupport]>; 175 176// LEON 3 FT (UT699). Provides features for the UT699 processor 177// - covers all the erratum fixes for LEON3, but does not support the CASA instruction. 178def : Processor<"ut699", LEON3Itineraries, 179 [FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>; 180 181// LEON3 FT (GR712RC). Provides features for the GR712RC processor. 182// - covers all the erratum fixed for LEON3 and support for the CASA instruction. 183def : Processor<"gr712rc", LEON3Itineraries, 184 [FeatureLeon, LeonCASA]>; 185 186// LEON 4 FT generic 187def : Processor<"leon4", LEON4Itineraries, 188 [FeatureLeon, UMACSMACSupport, LeonCASA]>; 189 190// LEON 4 FT (GR740) 191// TO DO: Place-holder: Processor specific features will be added *very* soon here. 192def : Processor<"gr740", LEON4Itineraries, 193 [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter, 194 FeaturePWRPSR]>; 195 196//===----------------------------------------------------------------------===// 197// Declare the target which we are implementing 198//===----------------------------------------------------------------------===// 199 200def SparcAsmWriter : AsmWriter { 201 string AsmWriterClassName = "InstPrinter"; 202 int PassSubtarget = 1; 203 int Variant = 0; 204} 205 206def Sparc : Target { 207 // Pull in Instruction Info: 208 let InstructionSet = SparcInstrInfo; 209 let AssemblyParsers = [SparcAsmParser]; 210 let AssemblyParserVariants = [SparcAsmParserVariant]; 211 let AssemblyWriters = [SparcAsmWriter]; 212 let AllowRegisterRenaming = 1; 213} 214