1*0b57cec5SDimitry Andric//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// 10*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 11*0b57cec5SDimitry Andric 12*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13*0b57cec5SDimitry Andric// Target-independent interfaces which we are implementing 14*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 15*0b57cec5SDimitry Andric 16*0b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 19*0b57cec5SDimitry Andric// SPARC Subtarget features. 20*0b57cec5SDimitry Andric// 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andricdef FeatureSoftMulDiv 23*0b57cec5SDimitry Andric : SubtargetFeature<"soft-mul-div", "UseSoftMulDiv", "true", 24*0b57cec5SDimitry Andric "Use software emulation for integer multiply and divide">; 25*0b57cec5SDimitry Andric 26*0b57cec5SDimitry Andricdef FeatureNoFSMULD 27*0b57cec5SDimitry Andric : SubtargetFeature<"no-fsmuld", "HasNoFSMULD", "true", 28*0b57cec5SDimitry Andric "Disable the fsmuld instruction.">; 29*0b57cec5SDimitry Andricdef FeatureNoFMULS 30*0b57cec5SDimitry Andric : SubtargetFeature<"no-fmuls", "HasNoFMULS", "true", 31*0b57cec5SDimitry Andric "Disable the fmuls instruction.">; 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andricdef FeatureV9 34*0b57cec5SDimitry Andric : SubtargetFeature<"v9", "IsV9", "true", 35*0b57cec5SDimitry Andric "Enable SPARC-V9 instructions">; 36*0b57cec5SDimitry Andricdef FeatureV8Deprecated 37*0b57cec5SDimitry Andric : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true", 38*0b57cec5SDimitry Andric "Enable deprecated V8 instructions in V9 mode">; 39*0b57cec5SDimitry Andricdef FeatureVIS 40*0b57cec5SDimitry Andric : SubtargetFeature<"vis", "IsVIS", "true", 41*0b57cec5SDimitry Andric "Enable UltraSPARC Visual Instruction Set extensions">; 42*0b57cec5SDimitry Andricdef FeatureVIS2 43*0b57cec5SDimitry Andric : SubtargetFeature<"vis2", "IsVIS2", "true", 44*0b57cec5SDimitry Andric "Enable Visual Instruction Set extensions II">; 45*0b57cec5SDimitry Andricdef FeatureVIS3 46*0b57cec5SDimitry Andric : SubtargetFeature<"vis3", "IsVIS3", "true", 47*0b57cec5SDimitry Andric "Enable Visual Instruction Set extensions III">; 48*0b57cec5SDimitry Andricdef FeatureLeon 49*0b57cec5SDimitry Andric : SubtargetFeature<"leon", "IsLeon", "true", 50*0b57cec5SDimitry Andric "Enable LEON extensions">; 51*0b57cec5SDimitry Andricdef FeaturePWRPSR 52*0b57cec5SDimitry Andric : SubtargetFeature<"leonpwrpsr", "HasPWRPSR", "true", 53*0b57cec5SDimitry Andric "Enable the PWRPSR instruction">; 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andricdef FeatureHardQuad 56*0b57cec5SDimitry Andric : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true", 57*0b57cec5SDimitry Andric "Enable quad-word floating point instructions">; 58*0b57cec5SDimitry Andric 59*0b57cec5SDimitry Andricdef UsePopc : SubtargetFeature<"popc", "UsePopc", "true", 60*0b57cec5SDimitry Andric "Use the popc (population count) instruction">; 61*0b57cec5SDimitry Andric 62*0b57cec5SDimitry Andricdef FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 63*0b57cec5SDimitry Andric "Use software emulation for floating point">; 64*0b57cec5SDimitry Andric 65*0b57cec5SDimitry Andric//==== Features added predmoninantly for LEON subtarget support 66*0b57cec5SDimitry Andricinclude "LeonFeatures.td" 67*0b57cec5SDimitry Andric 68*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 69*0b57cec5SDimitry Andric// Register File, Calling Conv, Instruction Descriptions 70*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 71*0b57cec5SDimitry Andric 72*0b57cec5SDimitry Andricinclude "SparcRegisterInfo.td" 73*0b57cec5SDimitry Andricinclude "SparcCallingConv.td" 74*0b57cec5SDimitry Andricinclude "SparcSchedule.td" 75*0b57cec5SDimitry Andricinclude "SparcInstrInfo.td" 76*0b57cec5SDimitry Andric 77*0b57cec5SDimitry Andricdef SparcInstrInfo : InstrInfo; 78*0b57cec5SDimitry Andric 79*0b57cec5SDimitry Andricdef SparcAsmParser : AsmParser { 80*0b57cec5SDimitry Andric bit ShouldEmitMatchRegisterName = 0; 81*0b57cec5SDimitry Andric} 82*0b57cec5SDimitry Andric 83*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 84*0b57cec5SDimitry Andric// SPARC processors supported. 85*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 86*0b57cec5SDimitry Andric 87*0b57cec5SDimitry Andricclass Proc<string Name, list<SubtargetFeature> Features> 88*0b57cec5SDimitry Andric : Processor<Name, NoItineraries, Features>; 89*0b57cec5SDimitry Andric 90*0b57cec5SDimitry Andricdef : Proc<"generic", []>; 91*0b57cec5SDimitry Andricdef : Proc<"v7", [FeatureSoftMulDiv, FeatureNoFSMULD]>; 92*0b57cec5SDimitry Andricdef : Proc<"v8", []>; 93*0b57cec5SDimitry Andricdef : Proc<"supersparc", []>; 94*0b57cec5SDimitry Andricdef : Proc<"sparclite", []>; 95*0b57cec5SDimitry Andricdef : Proc<"f934", []>; 96*0b57cec5SDimitry Andricdef : Proc<"hypersparc", []>; 97*0b57cec5SDimitry Andricdef : Proc<"sparclite86x", []>; 98*0b57cec5SDimitry Andricdef : Proc<"sparclet", []>; 99*0b57cec5SDimitry Andricdef : Proc<"tsc701", []>; 100*0b57cec5SDimitry Andricdef : Proc<"myriad2", [FeatureLeon, LeonCASA]>; 101*0b57cec5SDimitry Andricdef : Proc<"myriad2.1", [FeatureLeon, LeonCASA]>; 102*0b57cec5SDimitry Andricdef : Proc<"myriad2.2", [FeatureLeon, LeonCASA]>; 103*0b57cec5SDimitry Andricdef : Proc<"myriad2.3", [FeatureLeon, LeonCASA]>; 104*0b57cec5SDimitry Andricdef : Proc<"ma2100", [FeatureLeon, LeonCASA]>; 105*0b57cec5SDimitry Andricdef : Proc<"ma2150", [FeatureLeon, LeonCASA]>; 106*0b57cec5SDimitry Andricdef : Proc<"ma2155", [FeatureLeon, LeonCASA]>; 107*0b57cec5SDimitry Andricdef : Proc<"ma2450", [FeatureLeon, LeonCASA]>; 108*0b57cec5SDimitry Andricdef : Proc<"ma2455", [FeatureLeon, LeonCASA]>; 109*0b57cec5SDimitry Andricdef : Proc<"ma2x5x", [FeatureLeon, LeonCASA]>; 110*0b57cec5SDimitry Andricdef : Proc<"ma2080", [FeatureLeon, LeonCASA]>; 111*0b57cec5SDimitry Andricdef : Proc<"ma2085", [FeatureLeon, LeonCASA]>; 112*0b57cec5SDimitry Andricdef : Proc<"ma2480", [FeatureLeon, LeonCASA]>; 113*0b57cec5SDimitry Andricdef : Proc<"ma2485", [FeatureLeon, LeonCASA]>; 114*0b57cec5SDimitry Andricdef : Proc<"ma2x8x", [FeatureLeon, LeonCASA]>; 115*0b57cec5SDimitry Andricdef : Proc<"v9", [FeatureV9]>; 116*0b57cec5SDimitry Andricdef : Proc<"ultrasparc", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>; 117*0b57cec5SDimitry Andricdef : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS, 118*0b57cec5SDimitry Andric FeatureVIS2]>; 119*0b57cec5SDimitry Andricdef : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS, 120*0b57cec5SDimitry Andric FeatureVIS2]>; 121*0b57cec5SDimitry Andricdef : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc, 122*0b57cec5SDimitry Andric FeatureVIS, FeatureVIS2]>; 123*0b57cec5SDimitry Andricdef : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc, 124*0b57cec5SDimitry Andric FeatureVIS, FeatureVIS2]>; 125*0b57cec5SDimitry Andricdef : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc, 126*0b57cec5SDimitry Andric FeatureVIS, FeatureVIS2, FeatureVIS3]>; 127*0b57cec5SDimitry Andric 128*0b57cec5SDimitry Andric// LEON 2 FT generic 129*0b57cec5SDimitry Andricdef : Processor<"leon2", LEON2Itineraries, 130*0b57cec5SDimitry Andric [FeatureLeon]>; 131*0b57cec5SDimitry Andric 132*0b57cec5SDimitry Andric// LEON 2 FT (AT697E) 133*0b57cec5SDimitry Andric// TO DO: Place-holder: Processor specific features will be added *very* soon here. 134*0b57cec5SDimitry Andricdef : Processor<"at697e", LEON2Itineraries, 135*0b57cec5SDimitry Andric [FeatureLeon, InsertNOPLoad]>; 136*0b57cec5SDimitry Andric 137*0b57cec5SDimitry Andric// LEON 2 FT (AT697F) 138*0b57cec5SDimitry Andric// TO DO: Place-holder: Processor specific features will be added *very* soon here. 139*0b57cec5SDimitry Andricdef : Processor<"at697f", LEON2Itineraries, 140*0b57cec5SDimitry Andric [FeatureLeon, InsertNOPLoad]>; 141*0b57cec5SDimitry Andric 142*0b57cec5SDimitry Andric 143*0b57cec5SDimitry Andric// LEON 3 FT generic 144*0b57cec5SDimitry Andricdef : Processor<"leon3", LEON3Itineraries, 145*0b57cec5SDimitry Andric [FeatureLeon, UMACSMACSupport]>; 146*0b57cec5SDimitry Andric 147*0b57cec5SDimitry Andric// LEON 3 FT (UT699). Provides features for the UT699 processor 148*0b57cec5SDimitry Andric// - covers all the erratum fixes for LEON3, but does not support the CASA instruction. 149*0b57cec5SDimitry Andricdef : Processor<"ut699", LEON3Itineraries, 150*0b57cec5SDimitry Andric [FeatureLeon, InsertNOPLoad, FeatureNoFSMULD, FeatureNoFMULS, FixAllFDIVSQRT]>; 151*0b57cec5SDimitry Andric 152*0b57cec5SDimitry Andric// LEON3 FT (GR712RC). Provides features for the GR712RC processor. 153*0b57cec5SDimitry Andric// - covers all the erratum fixed for LEON3 and support for the CASA instruction. 154*0b57cec5SDimitry Andricdef : Processor<"gr712rc", LEON3Itineraries, 155*0b57cec5SDimitry Andric [FeatureLeon, LeonCASA]>; 156*0b57cec5SDimitry Andric 157*0b57cec5SDimitry Andric// LEON 4 FT generic 158*0b57cec5SDimitry Andricdef : Processor<"leon4", LEON4Itineraries, 159*0b57cec5SDimitry Andric [FeatureLeon, UMACSMACSupport, LeonCASA]>; 160*0b57cec5SDimitry Andric 161*0b57cec5SDimitry Andric// LEON 4 FT (GR740) 162*0b57cec5SDimitry Andric// TO DO: Place-holder: Processor specific features will be added *very* soon here. 163*0b57cec5SDimitry Andricdef : Processor<"gr740", LEON4Itineraries, 164*0b57cec5SDimitry Andric [FeatureLeon, UMACSMACSupport, LeonCASA, LeonCycleCounter, 165*0b57cec5SDimitry Andric FeaturePWRPSR]>; 166*0b57cec5SDimitry Andric 167*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 168*0b57cec5SDimitry Andric// Declare the target which we are implementing 169*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 170*0b57cec5SDimitry Andric 171*0b57cec5SDimitry Andricdef SparcAsmWriter : AsmWriter { 172*0b57cec5SDimitry Andric string AsmWriterClassName = "InstPrinter"; 173*0b57cec5SDimitry Andric int PassSubtarget = 1; 174*0b57cec5SDimitry Andric int Variant = 0; 175*0b57cec5SDimitry Andric} 176*0b57cec5SDimitry Andric 177*0b57cec5SDimitry Andricdef Sparc : Target { 178*0b57cec5SDimitry Andric // Pull in Instruction Info: 179*0b57cec5SDimitry Andric let InstructionSet = SparcInstrInfo; 180*0b57cec5SDimitry Andric let AssemblyParsers = [SparcAsmParser]; 181*0b57cec5SDimitry Andric let AssemblyWriters = [SparcAsmWriter]; 182*0b57cec5SDimitry Andric let AllowRegisterRenaming = 1; 183*0b57cec5SDimitry Andric} 184