1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/SparcFixupKinds.h" 10 #include "MCTargetDesc/SparcMCTargetDesc.h" 11 #include "llvm/MC/MCAsmBackend.h" 12 #include "llvm/MC/MCELFObjectWriter.h" 13 #include "llvm/MC/MCExpr.h" 14 #include "llvm/MC/MCFixupKindInfo.h" 15 #include "llvm/MC/MCObjectWriter.h" 16 #include "llvm/MC/MCSubtargetInfo.h" 17 #include "llvm/MC/MCValue.h" 18 #include "llvm/Support/EndianStream.h" 19 #include "llvm/Support/TargetRegistry.h" 20 21 using namespace llvm; 22 23 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 24 switch (Kind) { 25 default: 26 llvm_unreachable("Unknown fixup kind!"); 27 case FK_Data_1: 28 case FK_Data_2: 29 case FK_Data_4: 30 case FK_Data_8: 31 return Value; 32 33 case Sparc::fixup_sparc_wplt30: 34 case Sparc::fixup_sparc_call30: 35 return (Value >> 2) & 0x3fffffff; 36 37 case Sparc::fixup_sparc_br22: 38 return (Value >> 2) & 0x3fffff; 39 40 case Sparc::fixup_sparc_br19: 41 return (Value >> 2) & 0x7ffff; 42 43 case Sparc::fixup_sparc_br16_2: 44 return (Value >> 2) & 0xc000; 45 46 case Sparc::fixup_sparc_br16_14: 47 return (Value >> 2) & 0x3fff; 48 49 case Sparc::fixup_sparc_pc22: 50 case Sparc::fixup_sparc_got22: 51 case Sparc::fixup_sparc_tls_gd_hi22: 52 case Sparc::fixup_sparc_tls_ldm_hi22: 53 case Sparc::fixup_sparc_tls_ie_hi22: 54 case Sparc::fixup_sparc_hi22: 55 return (Value >> 10) & 0x3fffff; 56 57 case Sparc::fixup_sparc_got13: 58 case Sparc::fixup_sparc_13: 59 return Value & 0x1fff; 60 61 case Sparc::fixup_sparc_pc10: 62 case Sparc::fixup_sparc_got10: 63 case Sparc::fixup_sparc_tls_gd_lo10: 64 case Sparc::fixup_sparc_tls_ldm_lo10: 65 case Sparc::fixup_sparc_tls_ie_lo10: 66 case Sparc::fixup_sparc_lo10: 67 return Value & 0x3ff; 68 69 case Sparc::fixup_sparc_h44: 70 return (Value >> 22) & 0x3fffff; 71 72 case Sparc::fixup_sparc_m44: 73 return (Value >> 12) & 0x3ff; 74 75 case Sparc::fixup_sparc_l44: 76 return Value & 0xfff; 77 78 case Sparc::fixup_sparc_hh: 79 return (Value >> 42) & 0x3fffff; 80 81 case Sparc::fixup_sparc_hm: 82 return (Value >> 32) & 0x3ff; 83 84 case Sparc::fixup_sparc_tls_ldo_hix22: 85 case Sparc::fixup_sparc_tls_le_hix22: 86 case Sparc::fixup_sparc_tls_ldo_lox10: 87 case Sparc::fixup_sparc_tls_le_lox10: 88 assert(Value == 0 && "Sparc TLS relocs expect zero Value"); 89 return 0; 90 91 case Sparc::fixup_sparc_tls_gd_add: 92 case Sparc::fixup_sparc_tls_gd_call: 93 case Sparc::fixup_sparc_tls_ldm_add: 94 case Sparc::fixup_sparc_tls_ldm_call: 95 case Sparc::fixup_sparc_tls_ldo_add: 96 case Sparc::fixup_sparc_tls_ie_ld: 97 case Sparc::fixup_sparc_tls_ie_ldx: 98 case Sparc::fixup_sparc_tls_ie_add: 99 return 0; 100 } 101 } 102 103 /// getFixupKindNumBytes - The number of bytes the fixup may change. 104 static unsigned getFixupKindNumBytes(unsigned Kind) { 105 switch (Kind) { 106 default: 107 return 4; 108 case FK_Data_1: 109 return 1; 110 case FK_Data_2: 111 return 2; 112 case FK_Data_8: 113 return 8; 114 } 115 } 116 117 namespace { 118 class SparcAsmBackend : public MCAsmBackend { 119 protected: 120 const Target &TheTarget; 121 bool Is64Bit; 122 123 public: 124 SparcAsmBackend(const Target &T) 125 : MCAsmBackend(StringRef(T.getName()) == "sparcel" ? support::little 126 : support::big), 127 TheTarget(T), Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {} 128 129 unsigned getNumFixupKinds() const override { 130 return Sparc::NumTargetFixupKinds; 131 } 132 133 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 134 const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = { 135 // name offset bits flags 136 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 137 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 138 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 139 { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel }, 140 { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel }, 141 { "fixup_sparc_13", 19, 13, 0 }, 142 { "fixup_sparc_hi22", 10, 22, 0 }, 143 { "fixup_sparc_lo10", 22, 10, 0 }, 144 { "fixup_sparc_h44", 10, 22, 0 }, 145 { "fixup_sparc_m44", 22, 10, 0 }, 146 { "fixup_sparc_l44", 20, 12, 0 }, 147 { "fixup_sparc_hh", 10, 22, 0 }, 148 { "fixup_sparc_hm", 22, 10, 0 }, 149 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 150 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel }, 151 { "fixup_sparc_got22", 10, 22, 0 }, 152 { "fixup_sparc_got10", 22, 10, 0 }, 153 { "fixup_sparc_got13", 19, 13, 0 }, 154 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 155 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 }, 156 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 }, 157 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 158 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 159 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 }, 160 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 }, 161 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 162 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 163 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 }, 164 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 }, 165 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 166 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 }, 167 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 }, 168 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 169 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 170 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 171 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 172 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 173 }; 174 175 const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = { 176 // name offset bits flags 177 { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 178 { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 179 { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 180 { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel }, 181 { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel }, 182 { "fixup_sparc_13", 0, 13, 0 }, 183 { "fixup_sparc_hi22", 0, 22, 0 }, 184 { "fixup_sparc_lo10", 0, 10, 0 }, 185 { "fixup_sparc_h44", 0, 22, 0 }, 186 { "fixup_sparc_m44", 0, 10, 0 }, 187 { "fixup_sparc_l44", 0, 12, 0 }, 188 { "fixup_sparc_hh", 0, 22, 0 }, 189 { "fixup_sparc_hm", 0, 10, 0 }, 190 { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 191 { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 192 { "fixup_sparc_got22", 0, 22, 0 }, 193 { "fixup_sparc_got10", 0, 10, 0 }, 194 { "fixup_sparc_got13", 0, 13, 0 }, 195 { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 196 { "fixup_sparc_tls_gd_hi22", 0, 22, 0 }, 197 { "fixup_sparc_tls_gd_lo10", 0, 10, 0 }, 198 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 199 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 200 { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 }, 201 { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 }, 202 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 203 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 204 { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 }, 205 { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 }, 206 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 207 { "fixup_sparc_tls_ie_hi22", 0, 22, 0 }, 208 { "fixup_sparc_tls_ie_lo10", 0, 10, 0 }, 209 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 210 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 211 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 212 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 213 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 214 }; 215 216 if (Kind < FirstTargetFixupKind) 217 return MCAsmBackend::getFixupKindInfo(Kind); 218 219 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 220 "Invalid kind!"); 221 if (Endian == support::little) 222 return InfosLE[Kind - FirstTargetFixupKind]; 223 224 return InfosBE[Kind - FirstTargetFixupKind]; 225 } 226 227 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 228 const MCValue &Target) override { 229 switch ((Sparc::Fixups)Fixup.getKind()) { 230 default: 231 return false; 232 case Sparc::fixup_sparc_wplt30: 233 if (Target.getSymA()->getSymbol().isTemporary()) 234 return false; 235 LLVM_FALLTHROUGH; 236 case Sparc::fixup_sparc_tls_gd_hi22: 237 case Sparc::fixup_sparc_tls_gd_lo10: 238 case Sparc::fixup_sparc_tls_gd_add: 239 case Sparc::fixup_sparc_tls_gd_call: 240 case Sparc::fixup_sparc_tls_ldm_hi22: 241 case Sparc::fixup_sparc_tls_ldm_lo10: 242 case Sparc::fixup_sparc_tls_ldm_add: 243 case Sparc::fixup_sparc_tls_ldm_call: 244 case Sparc::fixup_sparc_tls_ldo_hix22: 245 case Sparc::fixup_sparc_tls_ldo_lox10: 246 case Sparc::fixup_sparc_tls_ldo_add: 247 case Sparc::fixup_sparc_tls_ie_hi22: 248 case Sparc::fixup_sparc_tls_ie_lo10: 249 case Sparc::fixup_sparc_tls_ie_ld: 250 case Sparc::fixup_sparc_tls_ie_ldx: 251 case Sparc::fixup_sparc_tls_ie_add: 252 case Sparc::fixup_sparc_tls_le_hix22: 253 case Sparc::fixup_sparc_tls_le_lox10: 254 return true; 255 } 256 } 257 258 bool mayNeedRelaxation(const MCInst &Inst, 259 const MCSubtargetInfo &STI) const override { 260 // FIXME. 261 return false; 262 } 263 264 /// fixupNeedsRelaxation - Target specific predicate for whether a given 265 /// fixup requires the associated instruction to be relaxed. 266 bool fixupNeedsRelaxation(const MCFixup &Fixup, 267 uint64_t Value, 268 const MCRelaxableFragment *DF, 269 const MCAsmLayout &Layout) const override { 270 // FIXME. 271 llvm_unreachable("fixupNeedsRelaxation() unimplemented"); 272 return false; 273 } 274 void relaxInstruction(MCInst &Inst, 275 const MCSubtargetInfo &STI) const override { 276 // FIXME. 277 llvm_unreachable("relaxInstruction() unimplemented"); 278 } 279 280 bool writeNopData(raw_ostream &OS, uint64_t Count) const override { 281 // Cannot emit NOP with size not multiple of 32 bits. 282 if (Count % 4 != 0) 283 return false; 284 285 uint64_t NumNops = Count / 4; 286 for (uint64_t i = 0; i != NumNops; ++i) 287 support::endian::write<uint32_t>(OS, 0x01000000, Endian); 288 289 return true; 290 } 291 }; 292 293 class ELFSparcAsmBackend : public SparcAsmBackend { 294 Triple::OSType OSType; 295 public: 296 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) : 297 SparcAsmBackend(T), OSType(OSType) { } 298 299 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 300 const MCValue &Target, MutableArrayRef<char> Data, 301 uint64_t Value, bool IsResolved, 302 const MCSubtargetInfo *STI) const override { 303 304 Value = adjustFixupValue(Fixup.getKind(), Value); 305 if (!Value) return; // Doesn't change encoding. 306 307 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 308 unsigned Offset = Fixup.getOffset(); 309 // For each byte of the fragment that the fixup touches, mask in the bits 310 // from the fixup value. The Value has been "split up" into the 311 // appropriate bitfields above. 312 for (unsigned i = 0; i != NumBytes; ++i) { 313 unsigned Idx = Endian == support::little ? i : (NumBytes - 1) - i; 314 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 315 } 316 } 317 318 std::unique_ptr<MCObjectTargetWriter> 319 createObjectTargetWriter() const override { 320 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); 321 return createSparcELFObjectWriter(Is64Bit, OSABI); 322 } 323 }; 324 325 } // end anonymous namespace 326 327 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, 328 const MCSubtargetInfo &STI, 329 const MCRegisterInfo &MRI, 330 const MCTargetOptions &Options) { 331 return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS()); 332 } 333