1 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This is a simple local pass that attempts to fill delay slots with useful 10 // instructions. If no instructions can be moved into the delay slot, then a 11 // NOP is placed. 12 //===----------------------------------------------------------------------===// 13 14 #include "Sparc.h" 15 #include "SparcSubtarget.h" 16 #include "llvm/ADT/SmallSet.h" 17 #include "llvm/ADT/Statistic.h" 18 #include "llvm/CodeGen/MachineFunctionPass.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/TargetInstrInfo.h" 22 #include "llvm/CodeGen/TargetRegisterInfo.h" 23 #include "llvm/Support/CommandLine.h" 24 #include "llvm/Target/TargetMachine.h" 25 26 using namespace llvm; 27 28 #define DEBUG_TYPE "delay-slot-filler" 29 30 STATISTIC(FilledSlots, "Number of delay slots filled"); 31 32 static cl::opt<bool> DisableDelaySlotFiller( 33 "disable-sparc-delay-filler", 34 cl::init(false), 35 cl::desc("Disable the Sparc delay slot filler."), 36 cl::Hidden); 37 38 namespace { 39 struct Filler : public MachineFunctionPass { 40 const SparcSubtarget *Subtarget = nullptr; 41 42 static char ID; 43 Filler() : MachineFunctionPass(ID) {} 44 45 StringRef getPassName() const override { return "SPARC Delay Slot Filler"; } 46 47 bool runOnMachineBasicBlock(MachineBasicBlock &MBB); 48 bool runOnMachineFunction(MachineFunction &F) override { 49 bool Changed = false; 50 Subtarget = &F.getSubtarget<SparcSubtarget>(); 51 52 // This pass invalidates liveness information when it reorders 53 // instructions to fill delay slot. 54 F.getRegInfo().invalidateLiveness(); 55 56 for (MachineBasicBlock &MBB : F) 57 Changed |= runOnMachineBasicBlock(MBB); 58 return Changed; 59 } 60 61 MachineFunctionProperties getRequiredProperties() const override { 62 return MachineFunctionProperties().set( 63 MachineFunctionProperties::Property::NoVRegs); 64 } 65 66 void insertCallDefsUses(MachineBasicBlock::iterator MI, 67 SmallSet<unsigned, 32>& RegDefs, 68 SmallSet<unsigned, 32>& RegUses); 69 70 void insertDefsUses(MachineBasicBlock::iterator MI, 71 SmallSet<unsigned, 32>& RegDefs, 72 SmallSet<unsigned, 32>& RegUses); 73 74 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet, 75 unsigned Reg); 76 77 bool delayHasHazard(MachineBasicBlock::iterator candidate, 78 bool &sawLoad, bool &sawStore, 79 SmallSet<unsigned, 32> &RegDefs, 80 SmallSet<unsigned, 32> &RegUses); 81 82 MachineBasicBlock::iterator 83 findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot); 84 85 bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize); 86 87 bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, 88 MachineBasicBlock::iterator MBBI); 89 90 }; 91 char Filler::ID = 0; 92 } // end of anonymous namespace 93 94 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay 95 /// slots in Sparc MachineFunctions 96 /// 97 FunctionPass *llvm::createSparcDelaySlotFillerPass() { 98 return new Filler; 99 } 100 101 102 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block. 103 /// We assume there is only one delay slot per delayed instruction. 104 /// 105 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { 106 bool Changed = false; 107 Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>(); 108 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); 109 110 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { 111 MachineBasicBlock::iterator MI = I; 112 ++I; 113 114 // If MI is restore, try combining it with previous inst. 115 if (!DisableDelaySlotFiller && 116 (MI->getOpcode() == SP::RESTORErr 117 || MI->getOpcode() == SP::RESTOREri)) { 118 Changed |= tryCombineRestoreWithPrevInst(MBB, MI); 119 continue; 120 } 121 122 // TODO: If we ever want to support v7, this needs to be extended 123 // to cover all floating point operations. 124 if (!Subtarget->isV9() && 125 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD 126 || MI->getOpcode() == SP::FCMPQ)) { 127 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); 128 Changed = true; 129 continue; 130 } 131 132 // If MI has no delay slot, skip. 133 if (!MI->hasDelaySlot()) 134 continue; 135 136 MachineBasicBlock::iterator D = MBB.end(); 137 138 if (!DisableDelaySlotFiller) 139 D = findDelayInstr(MBB, MI); 140 141 ++FilledSlots; 142 Changed = true; 143 144 if (D == MBB.end()) 145 BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP)); 146 else 147 MBB.splice(I, &MBB, D); 148 149 unsigned structSize = 0; 150 if (needsUnimp(MI, structSize)) { 151 MachineBasicBlock::iterator J = MI; 152 ++J; // skip the delay filler. 153 assert (J != MBB.end() && "MI needs a delay instruction."); 154 BuildMI(MBB, ++J, MI->getDebugLoc(), 155 TII->get(SP::UNIMP)).addImm(structSize); 156 // Bundle the delay filler and unimp with the instruction. 157 MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), J); 158 } else { 159 MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), I); 160 } 161 } 162 return Changed; 163 } 164 165 MachineBasicBlock::iterator 166 Filler::findDelayInstr(MachineBasicBlock &MBB, 167 MachineBasicBlock::iterator slot) 168 { 169 SmallSet<unsigned, 32> RegDefs; 170 SmallSet<unsigned, 32> RegUses; 171 bool sawLoad = false; 172 bool sawStore = false; 173 174 if (slot == MBB.begin()) 175 return MBB.end(); 176 177 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) 178 return MBB.end(); 179 180 if (slot->getOpcode() == SP::RETL) { 181 MachineBasicBlock::iterator J = slot; 182 --J; 183 184 if (J->getOpcode() == SP::RESTORErr 185 || J->getOpcode() == SP::RESTOREri) { 186 // change retl to ret. 187 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); 188 return J; 189 } 190 } 191 192 // Call's delay filler can def some of call's uses. 193 if (slot->isCall()) 194 insertCallDefsUses(slot, RegDefs, RegUses); 195 else 196 insertDefsUses(slot, RegDefs, RegUses); 197 198 bool done = false; 199 200 MachineBasicBlock::iterator I = slot; 201 202 while (!done) { 203 done = (I == MBB.begin()); 204 205 if (!done) 206 --I; 207 208 // skip debug instruction 209 if (I->isDebugInstr()) 210 continue; 211 212 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() || 213 I->hasDelaySlot() || I->isBundledWithSucc()) 214 break; 215 216 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) { 217 insertDefsUses(I, RegDefs, RegUses); 218 continue; 219 } 220 221 return I; 222 } 223 return MBB.end(); 224 } 225 226 bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate, 227 bool &sawLoad, 228 bool &sawStore, 229 SmallSet<unsigned, 32> &RegDefs, 230 SmallSet<unsigned, 32> &RegUses) 231 { 232 233 if (candidate->isImplicitDef() || candidate->isKill()) 234 return true; 235 236 if (candidate->mayLoad()) { 237 sawLoad = true; 238 if (sawStore) 239 return true; 240 } 241 242 if (candidate->mayStore()) { 243 if (sawStore) 244 return true; 245 sawStore = true; 246 if (sawLoad) 247 return true; 248 } 249 250 for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) { 251 const MachineOperand &MO = candidate->getOperand(i); 252 if (!MO.isReg()) 253 continue; // skip 254 255 Register Reg = MO.getReg(); 256 257 if (MO.isDef()) { 258 // check whether Reg is defined or used before delay slot. 259 if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg)) 260 return true; 261 } 262 if (MO.isUse()) { 263 // check whether Reg is defined before delay slot. 264 if (IsRegInSet(RegDefs, Reg)) 265 return true; 266 } 267 } 268 269 unsigned Opcode = candidate->getOpcode(); 270 // LD and LDD may have NOPs inserted afterwards in the case of some LEON 271 // processors, so we can't use the delay slot if this feature is switched-on. 272 if (Subtarget->insertNOPLoad() 273 && 274 Opcode >= SP::LDDArr && Opcode <= SP::LDrr) 275 return true; 276 277 // Same as above for FDIV and FSQRT on some LEON processors. 278 if (Subtarget->fixAllFDIVSQRT() 279 && 280 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD) 281 return true; 282 283 284 return false; 285 } 286 287 288 void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI, 289 SmallSet<unsigned, 32>& RegDefs, 290 SmallSet<unsigned, 32>& RegUses) 291 { 292 // Call defines o7, which is visible to the instruction in delay slot. 293 RegDefs.insert(SP::O7); 294 295 switch(MI->getOpcode()) { 296 default: llvm_unreachable("Unknown opcode."); 297 case SP::CALL: break; 298 case SP::CALLrr: 299 case SP::CALLri: 300 assert(MI->getNumOperands() >= 2); 301 const MachineOperand &Reg = MI->getOperand(0); 302 assert(Reg.isReg() && "CALL first operand is not a register."); 303 assert(Reg.isUse() && "CALL first operand is not a use."); 304 RegUses.insert(Reg.getReg()); 305 306 const MachineOperand &Operand1 = MI->getOperand(1); 307 if (Operand1.isImm() || Operand1.isGlobal()) 308 break; 309 assert(Operand1.isReg() && "CALLrr second operand is not a register."); 310 assert(Operand1.isUse() && "CALLrr second operand is not a use."); 311 RegUses.insert(Operand1.getReg()); 312 break; 313 } 314 } 315 316 // Insert Defs and Uses of MI into the sets RegDefs and RegUses. 317 void Filler::insertDefsUses(MachineBasicBlock::iterator MI, 318 SmallSet<unsigned, 32>& RegDefs, 319 SmallSet<unsigned, 32>& RegUses) 320 { 321 for (const MachineOperand &MO : MI->operands()) { 322 if (!MO.isReg()) 323 continue; 324 325 Register Reg = MO.getReg(); 326 if (Reg == 0) 327 continue; 328 if (MO.isDef()) 329 RegDefs.insert(Reg); 330 if (MO.isUse()) { 331 // Implicit register uses of retl are return values and 332 // retl does not use them. 333 if (MO.isImplicit() && MI->getOpcode() == SP::RETL) 334 continue; 335 RegUses.insert(Reg); 336 } 337 } 338 } 339 340 // returns true if the Reg or its alias is in the RegSet. 341 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) 342 { 343 // Check Reg and all aliased Registers. 344 for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true); 345 AI.isValid(); ++AI) 346 if (RegSet.count(*AI)) 347 return true; 348 return false; 349 } 350 351 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize) 352 { 353 if (!I->isCall()) 354 return false; 355 356 unsigned structSizeOpNum = 0; 357 switch (I->getOpcode()) { 358 default: llvm_unreachable("Unknown call opcode."); 359 case SP::CALL: structSizeOpNum = 1; break; 360 case SP::CALLrr: 361 case SP::CALLri: structSizeOpNum = 2; break; 362 case SP::TLS_CALL: return false; 363 } 364 365 const MachineOperand &MO = I->getOperand(structSizeOpNum); 366 if (!MO.isImm()) 367 return false; 368 StructSize = MO.getImm(); 369 return true; 370 } 371 372 static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI, 373 MachineBasicBlock::iterator AddMI, 374 const TargetInstrInfo *TII) 375 { 376 // Before: add <op0>, <op1>, %i[0-7] 377 // restore %g0, %g0, %i[0-7] 378 // 379 // After : restore <op0>, <op1>, %o[0-7] 380 381 Register reg = AddMI->getOperand(0).getReg(); 382 if (reg < SP::I0 || reg > SP::I7) 383 return false; 384 385 // Erase RESTORE. 386 RestoreMI->eraseFromParent(); 387 388 // Change ADD to RESTORE. 389 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) 390 ? SP::RESTORErr 391 : SP::RESTOREri)); 392 393 // Map the destination register. 394 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); 395 396 return true; 397 } 398 399 static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI, 400 MachineBasicBlock::iterator OrMI, 401 const TargetInstrInfo *TII) 402 { 403 // Before: or <op0>, <op1>, %i[0-7] 404 // restore %g0, %g0, %i[0-7] 405 // and <op0> or <op1> is zero, 406 // 407 // After : restore <op0>, <op1>, %o[0-7] 408 409 Register reg = OrMI->getOperand(0).getReg(); 410 if (reg < SP::I0 || reg > SP::I7) 411 return false; 412 413 // check whether it is a copy. 414 if (OrMI->getOpcode() == SP::ORrr 415 && OrMI->getOperand(1).getReg() != SP::G0 416 && OrMI->getOperand(2).getReg() != SP::G0) 417 return false; 418 419 if (OrMI->getOpcode() == SP::ORri 420 && OrMI->getOperand(1).getReg() != SP::G0 421 && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0)) 422 return false; 423 424 // Erase RESTORE. 425 RestoreMI->eraseFromParent(); 426 427 // Change OR to RESTORE. 428 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) 429 ? SP::RESTORErr 430 : SP::RESTOREri)); 431 432 // Map the destination register. 433 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); 434 435 return true; 436 } 437 438 static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI, 439 MachineBasicBlock::iterator SetHiMI, 440 const TargetInstrInfo *TII) 441 { 442 // Before: sethi imm3, %i[0-7] 443 // restore %g0, %g0, %g0 444 // 445 // After : restore %g0, (imm3<<10), %o[0-7] 446 447 Register reg = SetHiMI->getOperand(0).getReg(); 448 if (reg < SP::I0 || reg > SP::I7) 449 return false; 450 451 if (!SetHiMI->getOperand(1).isImm()) 452 return false; 453 454 int64_t imm = SetHiMI->getOperand(1).getImm(); 455 456 // Is it a 3 bit immediate? 457 if (!isInt<3>(imm)) 458 return false; 459 460 // Make it a 13 bit immediate. 461 imm = (imm << 10) & 0x1FFF; 462 463 assert(RestoreMI->getOpcode() == SP::RESTORErr); 464 465 RestoreMI->setDesc(TII->get(SP::RESTOREri)); 466 467 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); 468 RestoreMI->getOperand(1).setReg(SP::G0); 469 RestoreMI->getOperand(2).ChangeToImmediate(imm); 470 471 472 // Erase the original SETHI. 473 SetHiMI->eraseFromParent(); 474 475 return true; 476 } 477 478 bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, 479 MachineBasicBlock::iterator MBBI) 480 { 481 // No previous instruction. 482 if (MBBI == MBB.begin()) 483 return false; 484 485 // assert that MBBI is a "restore %g0, %g0, %g0". 486 assert(MBBI->getOpcode() == SP::RESTORErr 487 && MBBI->getOperand(0).getReg() == SP::G0 488 && MBBI->getOperand(1).getReg() == SP::G0 489 && MBBI->getOperand(2).getReg() == SP::G0); 490 491 MachineBasicBlock::iterator PrevInst = std::prev(MBBI); 492 493 // It cannot be combined with a bundled instruction. 494 if (PrevInst->isBundledWithSucc()) 495 return false; 496 497 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); 498 499 switch (PrevInst->getOpcode()) { 500 default: break; 501 case SP::ADDrr: 502 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break; 503 case SP::ORrr: 504 case SP::ORri: return combineRestoreOR(MBBI, PrevInst, TII); break; 505 case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break; 506 } 507 // It cannot combine with the previous instruction. 508 return false; 509 } 510