181ad6265SDimitry Andric //===--- SPIRVUtils.h ---- SPIR-V Utility Functions -------------*- C++ -*-===// 281ad6265SDimitry Andric // 381ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric // 781ad6265SDimitry Andric //===----------------------------------------------------------------------===// 881ad6265SDimitry Andric // 981ad6265SDimitry Andric // This file contains miscellaneous utility functions. 1081ad6265SDimitry Andric // 1181ad6265SDimitry Andric //===----------------------------------------------------------------------===// 1281ad6265SDimitry Andric 1381ad6265SDimitry Andric #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H 1481ad6265SDimitry Andric #define LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H 1581ad6265SDimitry Andric 1681ad6265SDimitry Andric #include "MCTargetDesc/SPIRVBaseInfo.h" 1781ad6265SDimitry Andric #include "llvm/IR/IRBuilder.h" 1881ad6265SDimitry Andric #include <string> 1981ad6265SDimitry Andric 2081ad6265SDimitry Andric namespace llvm { 2181ad6265SDimitry Andric class MCInst; 2281ad6265SDimitry Andric class MachineFunction; 2381ad6265SDimitry Andric class MachineInstr; 2481ad6265SDimitry Andric class MachineInstrBuilder; 2581ad6265SDimitry Andric class MachineIRBuilder; 2681ad6265SDimitry Andric class MachineRegisterInfo; 2781ad6265SDimitry Andric class Register; 2881ad6265SDimitry Andric class StringRef; 2981ad6265SDimitry Andric class SPIRVInstrInfo; 3081ad6265SDimitry Andric } // namespace llvm 3181ad6265SDimitry Andric 3281ad6265SDimitry Andric // Add the given string as a series of integer operand, inserting null 3381ad6265SDimitry Andric // terminators and padding to make sure the operands all have 32-bit 3481ad6265SDimitry Andric // little-endian words. 35*fcaf7f86SDimitry Andric void addStringImm(const llvm::StringRef &Str, llvm::MCInst &Inst); 3681ad6265SDimitry Andric void addStringImm(const llvm::StringRef &Str, llvm::MachineInstrBuilder &MIB); 3781ad6265SDimitry Andric void addStringImm(const llvm::StringRef &Str, llvm::IRBuilder<> &B, 3881ad6265SDimitry Andric std::vector<llvm::Value *> &Args); 3981ad6265SDimitry Andric 4081ad6265SDimitry Andric // Read the series of integer operands back as a null-terminated string using 4181ad6265SDimitry Andric // the reverse of the logic in addStringImm. 4281ad6265SDimitry Andric std::string getStringImm(const llvm::MachineInstr &MI, unsigned StartIndex); 4381ad6265SDimitry Andric 4481ad6265SDimitry Andric // Add the given numerical immediate to MIB. 4581ad6265SDimitry Andric void addNumImm(const llvm::APInt &Imm, llvm::MachineInstrBuilder &MIB); 4681ad6265SDimitry Andric 4781ad6265SDimitry Andric // Add an OpName instruction for the given target register. 4881ad6265SDimitry Andric void buildOpName(llvm::Register Target, const llvm::StringRef &Name, 4981ad6265SDimitry Andric llvm::MachineIRBuilder &MIRBuilder); 5081ad6265SDimitry Andric 5181ad6265SDimitry Andric // Add an OpDecorate instruction for the given Reg. 5281ad6265SDimitry Andric void buildOpDecorate(llvm::Register Reg, llvm::MachineIRBuilder &MIRBuilder, 5381ad6265SDimitry Andric llvm::SPIRV::Decoration Dec, 5481ad6265SDimitry Andric const std::vector<uint32_t> &DecArgs, 5581ad6265SDimitry Andric llvm::StringRef StrImm = ""); 5681ad6265SDimitry Andric void buildOpDecorate(llvm::Register Reg, llvm::MachineInstr &I, 5781ad6265SDimitry Andric const llvm::SPIRVInstrInfo &TII, 5881ad6265SDimitry Andric llvm::SPIRV::Decoration Dec, 5981ad6265SDimitry Andric const std::vector<uint32_t> &DecArgs, 6081ad6265SDimitry Andric llvm::StringRef StrImm = ""); 6181ad6265SDimitry Andric 6281ad6265SDimitry Andric // Convert a SPIR-V storage class to the corresponding LLVM IR address space. 6381ad6265SDimitry Andric unsigned storageClassToAddressSpace(llvm::SPIRV::StorageClass SC); 6481ad6265SDimitry Andric 6581ad6265SDimitry Andric // Convert an LLVM IR address space to a SPIR-V storage class. 6681ad6265SDimitry Andric llvm::SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace); 6781ad6265SDimitry Andric 6881ad6265SDimitry Andric llvm::SPIRV::MemorySemantics 6981ad6265SDimitry Andric getMemSemanticsForStorageClass(llvm::SPIRV::StorageClass SC); 7081ad6265SDimitry Andric 71*fcaf7f86SDimitry Andric llvm::SPIRV::MemorySemantics getMemSemantics(llvm::AtomicOrdering Ord); 72*fcaf7f86SDimitry Andric 7381ad6265SDimitry Andric // Find def instruction for the given ConstReg, walking through 7481ad6265SDimitry Andric // spv_track_constant and ASSIGN_TYPE instructions. Updates ConstReg by def 7581ad6265SDimitry Andric // of OpConstant instruction. 7681ad6265SDimitry Andric llvm::MachineInstr * 7781ad6265SDimitry Andric getDefInstrMaybeConstant(llvm::Register &ConstReg, 7881ad6265SDimitry Andric const llvm::MachineRegisterInfo *MRI); 7981ad6265SDimitry Andric 8081ad6265SDimitry Andric // Get constant integer value of the given ConstReg. 8181ad6265SDimitry Andric uint64_t getIConstVal(llvm::Register ConstReg, 8281ad6265SDimitry Andric const llvm::MachineRegisterInfo *MRI); 8381ad6265SDimitry Andric 84*fcaf7f86SDimitry Andric // Check if MI is a SPIR-V specific intrinsic call. 85*fcaf7f86SDimitry Andric bool isSpvIntrinsic(llvm::MachineInstr &MI, llvm::Intrinsic::ID IntrinsicID); 86*fcaf7f86SDimitry Andric 8781ad6265SDimitry Andric // Get type of i-th operand of the metadata node. 8881ad6265SDimitry Andric llvm::Type *getMDOperandAsType(const llvm::MDNode *N, unsigned I); 8981ad6265SDimitry Andric #endif // LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H 90