1*81ad6265SDimitry Andric //===--- SPIRVUtils.h ---- SPIR-V Utility Functions -------------*- C++ -*-===// 2*81ad6265SDimitry Andric // 3*81ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*81ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*81ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*81ad6265SDimitry Andric // 7*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 8*81ad6265SDimitry Andric // 9*81ad6265SDimitry Andric // This file contains miscellaneous utility functions. 10*81ad6265SDimitry Andric // 11*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 12*81ad6265SDimitry Andric 13*81ad6265SDimitry Andric #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H 14*81ad6265SDimitry Andric #define LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H 15*81ad6265SDimitry Andric 16*81ad6265SDimitry Andric #include "MCTargetDesc/SPIRVBaseInfo.h" 17*81ad6265SDimitry Andric #include "llvm/IR/IRBuilder.h" 18*81ad6265SDimitry Andric #include <string> 19*81ad6265SDimitry Andric 20*81ad6265SDimitry Andric namespace llvm { 21*81ad6265SDimitry Andric class MCInst; 22*81ad6265SDimitry Andric class MachineFunction; 23*81ad6265SDimitry Andric class MachineInstr; 24*81ad6265SDimitry Andric class MachineInstrBuilder; 25*81ad6265SDimitry Andric class MachineIRBuilder; 26*81ad6265SDimitry Andric class MachineRegisterInfo; 27*81ad6265SDimitry Andric class Register; 28*81ad6265SDimitry Andric class StringRef; 29*81ad6265SDimitry Andric class SPIRVInstrInfo; 30*81ad6265SDimitry Andric } // namespace llvm 31*81ad6265SDimitry Andric 32*81ad6265SDimitry Andric // Add the given string as a series of integer operand, inserting null 33*81ad6265SDimitry Andric // terminators and padding to make sure the operands all have 32-bit 34*81ad6265SDimitry Andric // little-endian words. 35*81ad6265SDimitry Andric void addStringImm(const llvm::StringRef &Str, llvm::MachineInstrBuilder &MIB); 36*81ad6265SDimitry Andric void addStringImm(const llvm::StringRef &Str, llvm::IRBuilder<> &B, 37*81ad6265SDimitry Andric std::vector<llvm::Value *> &Args); 38*81ad6265SDimitry Andric 39*81ad6265SDimitry Andric // Read the series of integer operands back as a null-terminated string using 40*81ad6265SDimitry Andric // the reverse of the logic in addStringImm. 41*81ad6265SDimitry Andric std::string getStringImm(const llvm::MachineInstr &MI, unsigned StartIndex); 42*81ad6265SDimitry Andric 43*81ad6265SDimitry Andric // Add the given numerical immediate to MIB. 44*81ad6265SDimitry Andric void addNumImm(const llvm::APInt &Imm, llvm::MachineInstrBuilder &MIB); 45*81ad6265SDimitry Andric 46*81ad6265SDimitry Andric // Add an OpName instruction for the given target register. 47*81ad6265SDimitry Andric void buildOpName(llvm::Register Target, const llvm::StringRef &Name, 48*81ad6265SDimitry Andric llvm::MachineIRBuilder &MIRBuilder); 49*81ad6265SDimitry Andric 50*81ad6265SDimitry Andric // Add an OpDecorate instruction for the given Reg. 51*81ad6265SDimitry Andric void buildOpDecorate(llvm::Register Reg, llvm::MachineIRBuilder &MIRBuilder, 52*81ad6265SDimitry Andric llvm::SPIRV::Decoration Dec, 53*81ad6265SDimitry Andric const std::vector<uint32_t> &DecArgs, 54*81ad6265SDimitry Andric llvm::StringRef StrImm = ""); 55*81ad6265SDimitry Andric void buildOpDecorate(llvm::Register Reg, llvm::MachineInstr &I, 56*81ad6265SDimitry Andric const llvm::SPIRVInstrInfo &TII, 57*81ad6265SDimitry Andric llvm::SPIRV::Decoration Dec, 58*81ad6265SDimitry Andric const std::vector<uint32_t> &DecArgs, 59*81ad6265SDimitry Andric llvm::StringRef StrImm = ""); 60*81ad6265SDimitry Andric 61*81ad6265SDimitry Andric // Convert a SPIR-V storage class to the corresponding LLVM IR address space. 62*81ad6265SDimitry Andric unsigned storageClassToAddressSpace(llvm::SPIRV::StorageClass SC); 63*81ad6265SDimitry Andric 64*81ad6265SDimitry Andric // Convert an LLVM IR address space to a SPIR-V storage class. 65*81ad6265SDimitry Andric llvm::SPIRV::StorageClass addressSpaceToStorageClass(unsigned AddrSpace); 66*81ad6265SDimitry Andric 67*81ad6265SDimitry Andric llvm::SPIRV::MemorySemantics 68*81ad6265SDimitry Andric getMemSemanticsForStorageClass(llvm::SPIRV::StorageClass SC); 69*81ad6265SDimitry Andric 70*81ad6265SDimitry Andric // Find def instruction for the given ConstReg, walking through 71*81ad6265SDimitry Andric // spv_track_constant and ASSIGN_TYPE instructions. Updates ConstReg by def 72*81ad6265SDimitry Andric // of OpConstant instruction. 73*81ad6265SDimitry Andric llvm::MachineInstr * 74*81ad6265SDimitry Andric getDefInstrMaybeConstant(llvm::Register &ConstReg, 75*81ad6265SDimitry Andric const llvm::MachineRegisterInfo *MRI); 76*81ad6265SDimitry Andric 77*81ad6265SDimitry Andric // Get constant integer value of the given ConstReg. 78*81ad6265SDimitry Andric uint64_t getIConstVal(llvm::Register ConstReg, 79*81ad6265SDimitry Andric const llvm::MachineRegisterInfo *MRI); 80*81ad6265SDimitry Andric 81*81ad6265SDimitry Andric // Get type of i-th operand of the metadata node. 82*81ad6265SDimitry Andric llvm::Type *getMDOperandAsType(const llvm::MDNode *N, unsigned I); 83*81ad6265SDimitry Andric #endif // LLVM_LIB_TARGET_SPIRV_SPIRVUTILS_H 84