1*81ad6265SDimitry Andric //===- SPIRVRegisterBankInfo.cpp ------------------------------*- C++ -*---===// 2*81ad6265SDimitry Andric // 3*81ad6265SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*81ad6265SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*81ad6265SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*81ad6265SDimitry Andric // 7*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 8*81ad6265SDimitry Andric // 9*81ad6265SDimitry Andric // This file implements the targeting of the RegisterBankInfo class for SPIR-V. 10*81ad6265SDimitry Andric // 11*81ad6265SDimitry Andric //===----------------------------------------------------------------------===// 12*81ad6265SDimitry Andric 13*81ad6265SDimitry Andric #include "SPIRVRegisterBankInfo.h" 14*81ad6265SDimitry Andric #include "SPIRVRegisterInfo.h" 15*81ad6265SDimitry Andric #include "llvm/CodeGen/RegisterBank.h" 16*81ad6265SDimitry Andric 17*81ad6265SDimitry Andric #define GET_REGINFO_ENUM 18*81ad6265SDimitry Andric #include "SPIRVGenRegisterInfo.inc" 19*81ad6265SDimitry Andric 20*81ad6265SDimitry Andric #define GET_TARGET_REGBANK_IMPL 21*81ad6265SDimitry Andric #include "SPIRVGenRegisterBank.inc" 22*81ad6265SDimitry Andric 23*81ad6265SDimitry Andric using namespace llvm; 24*81ad6265SDimitry Andric 25*81ad6265SDimitry Andric // This required for .td selection patterns to work or we'd end up with RegClass 26*81ad6265SDimitry Andric // checks being redundant as all the classes would be mapped to the same bank. 27*81ad6265SDimitry Andric const RegisterBank & 28*81ad6265SDimitry Andric SPIRVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC, 29*81ad6265SDimitry Andric LLT Ty) const { 30*81ad6265SDimitry Andric switch (RC.getID()) { 31*81ad6265SDimitry Andric case SPIRV::TYPERegClassID: 32*81ad6265SDimitry Andric return SPIRV::TYPERegBank; 33*81ad6265SDimitry Andric case SPIRV::pIDRegClassID: 34*81ad6265SDimitry Andric case SPIRV::IDRegClassID: 35*81ad6265SDimitry Andric return SPIRV::IDRegBank; 36*81ad6265SDimitry Andric case SPIRV::fIDRegClassID: 37*81ad6265SDimitry Andric return SPIRV::fIDRegBank; 38*81ad6265SDimitry Andric case SPIRV::vIDRegClassID: 39*81ad6265SDimitry Andric return SPIRV::vIDRegBank; 40*81ad6265SDimitry Andric case SPIRV::vfIDRegClassID: 41*81ad6265SDimitry Andric return SPIRV::vfIDRegBank; 42*81ad6265SDimitry Andric case SPIRV::ANYIDRegClassID: 43*81ad6265SDimitry Andric case SPIRV::ANYRegClassID: 44*81ad6265SDimitry Andric return SPIRV::IDRegBank; 45*81ad6265SDimitry Andric } 46*81ad6265SDimitry Andric llvm_unreachable("Unknown register class"); 47*81ad6265SDimitry Andric } 48