1 //===-- SPIRVISelLowering.h - SPIR-V DAG Lowering Interface -----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that SPIR-V uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H 15 #define LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H 16 17 #include "llvm/CodeGen/TargetLowering.h" 18 19 namespace llvm { 20 class SPIRVSubtarget; 21 22 class SPIRVTargetLowering : public TargetLowering { 23 public: 24 explicit SPIRVTargetLowering(const TargetMachine &TM, 25 const SPIRVSubtarget &STI) 26 : TargetLowering(TM) {} 27 28 // Stop IRTranslator breaking up FMA instrs to preserve types information. 29 bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, 30 EVT) const override { 31 return true; 32 } 33 34 // This is to prevent sexts of non-i64 vector indices which are generated 35 // within general IRTranslator hence type generation for it is omitted. 36 MVT getVectorIdxTy(const DataLayout &DL) const override { 37 return MVT::getIntegerVT(32); 38 } 39 unsigned getNumRegistersForCallingConv(LLVMContext &Context, 40 CallingConv::ID CC, 41 EVT VT) const override; 42 MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, 43 EVT VT) const override; 44 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 45 MachineFunction &MF, 46 unsigned Intrinsic) const override; 47 }; 48 } // namespace llvm 49 50 #endif // LLVM_LIB_TARGET_SPIRV_SPIRVISELLOWERING_H 51