181ad6265SDimitry Andric//===-- SPIRV.td - Describe the SPIR-V Target Machine ------*- tablegen -*-===// 281ad6265SDimitry Andric// 381ad6265SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 481ad6265SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 581ad6265SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 681ad6265SDimitry Andric// 781ad6265SDimitry Andric//===----------------------------------------------------------------------===// 881ad6265SDimitry Andric 981ad6265SDimitry Andricinclude "llvm/Target/Target.td" 1081ad6265SDimitry Andric 1181ad6265SDimitry Andricinclude "SPIRVRegisterInfo.td" 1281ad6265SDimitry Andricinclude "SPIRVRegisterBanks.td" 1381ad6265SDimitry Andricinclude "SPIRVInstrInfo.td" 14*bdd1243dSDimitry Andricinclude "SPIRVBuiltins.td" 1581ad6265SDimitry Andric 1681ad6265SDimitry Andricdef SPIRVInstrInfo : InstrInfo; 1781ad6265SDimitry Andric 1881ad6265SDimitry Andricclass Proc<string Name, list<SubtargetFeature> Features> 1981ad6265SDimitry Andric : Processor<Name, NoItineraries, Features>; 2081ad6265SDimitry Andric 2181ad6265SDimitry Andricdef : Proc<"generic", []>; 2281ad6265SDimitry Andric 2381ad6265SDimitry Andricdef SPIRVInstPrinter : AsmWriter { 2481ad6265SDimitry Andric string AsmWriterClassName = "InstPrinter"; 2581ad6265SDimitry Andric bit isMCAsmWriter = 1; 2681ad6265SDimitry Andric} 2781ad6265SDimitry Andric 2881ad6265SDimitry Andricdef SPIRV : Target { 2981ad6265SDimitry Andric let InstructionSet = SPIRVInstrInfo; 3081ad6265SDimitry Andric let AssemblyWriters = [SPIRVInstPrinter]; 3181ad6265SDimitry Andric} 32