1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "RISCVTargetTransformInfo.h" 10 #include "MCTargetDesc/RISCVMatInt.h" 11 #include "llvm/Analysis/TargetTransformInfo.h" 12 #include "llvm/CodeGen/BasicTTIImpl.h" 13 #include "llvm/CodeGen/TargetLowering.h" 14 using namespace llvm; 15 16 #define DEBUG_TYPE "riscvtti" 17 18 static cl::opt<unsigned> RVVRegisterWidthLMUL( 19 "riscv-v-register-bit-width-lmul", 20 cl::desc( 21 "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used " 22 "by autovectorized code. Fractional LMULs are not supported."), 23 cl::init(1), cl::Hidden); 24 25 InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty, 26 TTI::TargetCostKind CostKind) { 27 assert(Ty->isIntegerTy() && 28 "getIntImmCost can only estimate cost of materialising integers"); 29 30 // We have a Zero register, so 0 is always free. 31 if (Imm == 0) 32 return TTI::TCC_Free; 33 34 // Otherwise, we check how many instructions it will take to materialise. 35 const DataLayout &DL = getDataLayout(); 36 return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty), 37 getST()->getFeatureBits()); 38 } 39 40 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx, 41 const APInt &Imm, Type *Ty, 42 TTI::TargetCostKind CostKind, 43 Instruction *Inst) { 44 assert(Ty->isIntegerTy() && 45 "getIntImmCost can only estimate cost of materialising integers"); 46 47 // We have a Zero register, so 0 is always free. 48 if (Imm == 0) 49 return TTI::TCC_Free; 50 51 // Some instructions in RISC-V can take a 12-bit immediate. Some of these are 52 // commutative, in others the immediate comes from a specific argument index. 53 bool Takes12BitImm = false; 54 unsigned ImmArgIdx = ~0U; 55 56 switch (Opcode) { 57 case Instruction::GetElementPtr: 58 // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will 59 // split up large offsets in GEP into better parts than ConstantHoisting 60 // can. 61 return TTI::TCC_Free; 62 case Instruction::And: 63 // zext.h 64 if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb()) 65 return TTI::TCC_Free; 66 // zext.w 67 if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb()) 68 return TTI::TCC_Free; 69 LLVM_FALLTHROUGH; 70 case Instruction::Add: 71 case Instruction::Or: 72 case Instruction::Xor: 73 case Instruction::Mul: 74 Takes12BitImm = true; 75 break; 76 case Instruction::Sub: 77 case Instruction::Shl: 78 case Instruction::LShr: 79 case Instruction::AShr: 80 Takes12BitImm = true; 81 ImmArgIdx = 1; 82 break; 83 default: 84 break; 85 } 86 87 if (Takes12BitImm) { 88 // Check immediate is the correct argument... 89 if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) { 90 // ... and fits into the 12-bit immediate. 91 if (Imm.getMinSignedBits() <= 64 && 92 getTLI()->isLegalAddImmediate(Imm.getSExtValue())) { 93 return TTI::TCC_Free; 94 } 95 } 96 97 // Otherwise, use the full materialisation cost. 98 return getIntImmCost(Imm, Ty, CostKind); 99 } 100 101 // By default, prevent hoisting. 102 return TTI::TCC_Free; 103 } 104 105 InstructionCost 106 RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, 107 const APInt &Imm, Type *Ty, 108 TTI::TargetCostKind CostKind) { 109 // Prevent hoisting in unknown cases. 110 return TTI::TCC_Free; 111 } 112 113 TargetTransformInfo::PopcntSupportKind 114 RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) { 115 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); 116 return ST->hasStdExtZbb() ? TTI::PSK_FastHardware : TTI::PSK_Software; 117 } 118 119 bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const { 120 // Currently, the ExpandReductions pass can't expand scalable-vector 121 // reductions, but we still request expansion as RVV doesn't support certain 122 // reductions and the SelectionDAG can't legalize them either. 123 switch (II->getIntrinsicID()) { 124 default: 125 return false; 126 // These reductions have no equivalent in RVV 127 case Intrinsic::vector_reduce_mul: 128 case Intrinsic::vector_reduce_fmul: 129 return true; 130 } 131 } 132 133 Optional<unsigned> RISCVTTIImpl::getMaxVScale() const { 134 // There is no assumption of the maximum vector length in V specification. 135 // We use the value specified by users as the maximum vector length. 136 // This function will use the assumed maximum vector length to get the 137 // maximum vscale for LoopVectorizer. 138 // If users do not specify the maximum vector length, we have no way to 139 // know whether the LoopVectorizer is safe to do or not. 140 // We only consider to use single vector register (LMUL = 1) to vectorize. 141 unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits(); 142 if (ST->hasVInstructions() && MaxVectorSizeInBits != 0) 143 return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock; 144 return BaseT::getMaxVScale(); 145 } 146 147 TypeSize 148 RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { 149 unsigned LMUL = PowerOf2Floor( 150 std::max<unsigned>(std::min<unsigned>(RVVRegisterWidthLMUL, 8), 1)); 151 switch (K) { 152 case TargetTransformInfo::RGK_Scalar: 153 return TypeSize::getFixed(ST->getXLen()); 154 case TargetTransformInfo::RGK_FixedWidthVector: 155 return TypeSize::getFixed( 156 ST->hasVInstructions() ? LMUL * ST->getMinRVVVectorSizeInBits() : 0); 157 case TargetTransformInfo::RGK_ScalableVector: 158 return TypeSize::getScalable( 159 ST->hasVInstructions() ? LMUL * RISCV::RVVBitsPerBlock : 0); 160 } 161 162 llvm_unreachable("Unsupported register kind"); 163 } 164 165 InstructionCost RISCVTTIImpl::getGatherScatterOpCost( 166 unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask, 167 Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) { 168 if (CostKind != TTI::TCK_RecipThroughput) 169 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, 170 Alignment, CostKind, I); 171 172 if ((Opcode == Instruction::Load && 173 !isLegalMaskedGather(DataTy, Align(Alignment))) || 174 (Opcode == Instruction::Store && 175 !isLegalMaskedScatter(DataTy, Align(Alignment)))) 176 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, 177 Alignment, CostKind, I); 178 179 // FIXME: Only supporting fixed vectors for now. 180 if (!isa<FixedVectorType>(DataTy)) 181 return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask, 182 Alignment, CostKind, I); 183 184 auto *VTy = cast<FixedVectorType>(DataTy); 185 unsigned NumLoads = VTy->getNumElements(); 186 InstructionCost MemOpCost = 187 getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I); 188 return NumLoads * MemOpCost; 189 } 190 191 void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE, 192 TTI::UnrollingPreferences &UP, 193 OptimizationRemarkEmitter *ORE) { 194 // TODO: More tuning on benchmarks and metrics with changes as needed 195 // would apply to all settings below to enable performance. 196 197 // Support explicit targets enabled for SiFive with the unrolling preferences 198 // below 199 bool UseDefaultPreferences = true; 200 if (ST->getProcFamily() == RISCVSubtarget::SiFive7) 201 UseDefaultPreferences = false; 202 203 if (UseDefaultPreferences) 204 return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP, ORE); 205 206 // Enable Upper bound unrolling universally, not dependant upon the conditions 207 // below. 208 UP.UpperBound = true; 209 210 // Disable loop unrolling for Oz and Os. 211 UP.OptSizeThreshold = 0; 212 UP.PartialOptSizeThreshold = 0; 213 if (L->getHeader()->getParent()->hasOptSize()) 214 return; 215 216 SmallVector<BasicBlock *, 4> ExitingBlocks; 217 L->getExitingBlocks(ExitingBlocks); 218 LLVM_DEBUG(dbgs() << "Loop has:\n" 219 << "Blocks: " << L->getNumBlocks() << "\n" 220 << "Exit blocks: " << ExitingBlocks.size() << "\n"); 221 222 // Only allow another exit other than the latch. This acts as an early exit 223 // as it mirrors the profitability calculation of the runtime unroller. 224 if (ExitingBlocks.size() > 2) 225 return; 226 227 // Limit the CFG of the loop body for targets with a branch predictor. 228 // Allowing 4 blocks permits if-then-else diamonds in the body. 229 if (L->getNumBlocks() > 4) 230 return; 231 232 // Don't unroll vectorized loops, including the remainder loop 233 if (getBooleanLoopAttribute(L, "llvm.loop.isvectorized")) 234 return; 235 236 // Scan the loop: don't unroll loops with calls as this could prevent 237 // inlining. 238 InstructionCost Cost = 0; 239 for (auto *BB : L->getBlocks()) { 240 for (auto &I : *BB) { 241 // Initial setting - Don't unroll loops containing vectorized 242 // instructions. 243 if (I.getType()->isVectorTy()) 244 return; 245 246 if (isa<CallInst>(I) || isa<InvokeInst>(I)) { 247 if (const Function *F = cast<CallBase>(I).getCalledFunction()) { 248 if (!isLoweredToCall(F)) 249 continue; 250 } 251 return; 252 } 253 254 SmallVector<const Value *> Operands(I.operand_values()); 255 Cost += 256 getUserCost(&I, Operands, TargetTransformInfo::TCK_SizeAndLatency); 257 } 258 } 259 260 LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n"); 261 262 UP.Partial = true; 263 UP.Runtime = true; 264 UP.UnrollRemainder = true; 265 UP.UnrollAndJam = true; 266 UP.UnrollAndJamInnerLoopThreshold = 60; 267 268 // Force unrolling small loops can be very useful because of the branch 269 // taken cost of the backedge. 270 if (Cost < 12) 271 UP.Force = true; 272 } 273 274 void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE, 275 TTI::PeelingPreferences &PP) { 276 BaseT::getPeelingPreferences(L, SE, PP); 277 } 278 279 InstructionCost RISCVTTIImpl::getRegUsageForType(Type *Ty) { 280 TypeSize Size = Ty->getPrimitiveSizeInBits(); 281 if (Ty->isVectorTy()) { 282 if (Size.isScalable() && ST->hasVInstructions()) 283 return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock); 284 285 if (ST->useRVVForFixedLengthVectors()) 286 return divideCeil(Size, ST->getMinRVVVectorSizeInBits()); 287 } 288 289 return BaseT::getRegUsageForType(Ty); 290 } 291