1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about RISCV target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVTargetMachine.h" 14 #include "MCTargetDesc/RISCVBaseInfo.h" 15 #include "RISCV.h" 16 #include "RISCVMachineFunctionInfo.h" 17 #include "RISCVMacroFusion.h" 18 #include "RISCVTargetObjectFile.h" 19 #include "RISCVTargetTransformInfo.h" 20 #include "TargetInfo/RISCVTargetInfo.h" 21 #include "llvm/ADT/STLExtras.h" 22 #include "llvm/Analysis/TargetTransformInfo.h" 23 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 25 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 26 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 27 #include "llvm/CodeGen/MIRParser/MIParser.h" 28 #include "llvm/CodeGen/MIRYamlMapping.h" 29 #include "llvm/CodeGen/Passes.h" 30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 31 #include "llvm/CodeGen/TargetPassConfig.h" 32 #include "llvm/IR/LegacyPassManager.h" 33 #include "llvm/InitializePasses.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/FormattedStream.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Transforms/IPO.h" 38 using namespace llvm; 39 40 static cl::opt<bool> EnableRedundantCopyElimination( 41 "riscv-enable-copyelim", 42 cl::desc("Enable the redundant copy elimination pass"), cl::init(true), 43 cl::Hidden); 44 45 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { 46 RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target()); 47 RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target()); 48 auto *PR = PassRegistry::getPassRegistry(); 49 initializeGlobalISel(*PR); 50 initializeRISCVMakeCompressibleOptPass(*PR); 51 initializeRISCVGatherScatterLoweringPass(*PR); 52 initializeRISCVCodeGenPreparePass(*PR); 53 initializeRISCVMergeBaseOffsetOptPass(*PR); 54 initializeRISCVSExtWRemovalPass(*PR); 55 initializeRISCVExpandPseudoPass(*PR); 56 initializeRISCVInsertVSETVLIPass(*PR); 57 } 58 59 static StringRef computeDataLayout(const Triple &TT) { 60 if (TT.isArch64Bit()) 61 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; 62 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); 63 return "e-m:e-p:32:32-i64:64-n32-S128"; 64 } 65 66 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 67 Optional<Reloc::Model> RM) { 68 return RM.value_or(Reloc::Static); 69 } 70 71 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, 72 StringRef CPU, StringRef FS, 73 const TargetOptions &Options, 74 Optional<Reloc::Model> RM, 75 Optional<CodeModel::Model> CM, 76 CodeGenOpt::Level OL, bool JIT) 77 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, 78 getEffectiveRelocModel(TT, RM), 79 getEffectiveCodeModel(CM, CodeModel::Small), OL), 80 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) { 81 initAsmInfo(); 82 83 // RISC-V supports the MachineOutliner. 84 setMachineOutliner(true); 85 setSupportsDefaultOutlining(true); 86 } 87 88 const RISCVSubtarget * 89 RISCVTargetMachine::getSubtargetImpl(const Function &F) const { 90 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 91 Attribute TuneAttr = F.getFnAttribute("tune-cpu"); 92 Attribute FSAttr = F.getFnAttribute("target-features"); 93 94 std::string CPU = 95 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 96 std::string TuneCPU = 97 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; 98 std::string FS = 99 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 100 std::string Key = CPU + TuneCPU + FS; 101 auto &I = SubtargetMap[Key]; 102 if (!I) { 103 // This needs to be done before we create a new subtarget since any 104 // creation will depend on the TM and the code generation flags on the 105 // function that reside in TargetOptions. 106 resetTargetOptions(F); 107 auto ABIName = Options.MCOptions.getABIName(); 108 if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>( 109 F.getParent()->getModuleFlag("target-abi"))) { 110 auto TargetABI = RISCVABI::getTargetABI(ABIName); 111 if (TargetABI != RISCVABI::ABI_Unknown && 112 ModuleTargetABI->getString() != ABIName) { 113 report_fatal_error("-target-abi option != target-abi module flag"); 114 } 115 ABIName = ModuleTargetABI->getString(); 116 } 117 I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this); 118 } 119 return I.get(); 120 } 121 122 TargetTransformInfo 123 RISCVTargetMachine::getTargetTransformInfo(const Function &F) const { 124 return TargetTransformInfo(RISCVTTIImpl(this, F)); 125 } 126 127 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes 128 // for all memory accesses, so it is reasonable to assume that an 129 // implementation has no-op address space casts. If an implementation makes a 130 // change to this, they can override it here. 131 bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS, 132 unsigned DstAS) const { 133 return true; 134 } 135 136 namespace { 137 class RISCVPassConfig : public TargetPassConfig { 138 public: 139 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) 140 : TargetPassConfig(TM, PM) {} 141 142 RISCVTargetMachine &getRISCVTargetMachine() const { 143 return getTM<RISCVTargetMachine>(); 144 } 145 146 ScheduleDAGInstrs * 147 createMachineScheduler(MachineSchedContext *C) const override { 148 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); 149 if (ST.hasMacroFusion()) { 150 ScheduleDAGMILive *DAG = createGenericSchedLive(C); 151 DAG->addMutation(createRISCVMacroFusionDAGMutation()); 152 return DAG; 153 } 154 return nullptr; 155 } 156 157 ScheduleDAGInstrs * 158 createPostMachineScheduler(MachineSchedContext *C) const override { 159 const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>(); 160 if (ST.hasMacroFusion()) { 161 ScheduleDAGMI *DAG = createGenericSchedPostRA(C); 162 DAG->addMutation(createRISCVMacroFusionDAGMutation()); 163 return DAG; 164 } 165 return nullptr; 166 } 167 168 void addIRPasses() override; 169 bool addPreISel() override; 170 bool addInstSelector() override; 171 bool addIRTranslator() override; 172 bool addLegalizeMachineIR() override; 173 bool addRegBankSelect() override; 174 bool addGlobalInstructionSelect() override; 175 void addPreEmitPass() override; 176 void addPreEmitPass2() override; 177 void addPreSched2() override; 178 void addMachineSSAOptimization() override; 179 void addPreRegAlloc() override; 180 void addPostRegAlloc() override; 181 }; 182 } // namespace 183 184 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { 185 return new RISCVPassConfig(*this, PM); 186 } 187 188 void RISCVPassConfig::addIRPasses() { 189 addPass(createAtomicExpandPass()); 190 191 if (getOptLevel() != CodeGenOpt::None) 192 addPass(createRISCVGatherScatterLoweringPass()); 193 194 if (getOptLevel() != CodeGenOpt::None) 195 addPass(createRISCVCodeGenPreparePass()); 196 197 TargetPassConfig::addIRPasses(); 198 } 199 200 bool RISCVPassConfig::addPreISel() { 201 if (TM->getOptLevel() != CodeGenOpt::None) { 202 // Add a barrier before instruction selection so that we will not get 203 // deleted block address after enabling default outlining. See D99707 for 204 // more details. 205 addPass(createBarrierNoopPass()); 206 } 207 return false; 208 } 209 210 bool RISCVPassConfig::addInstSelector() { 211 addPass(createRISCVISelDag(getRISCVTargetMachine(), getOptLevel())); 212 213 return false; 214 } 215 216 bool RISCVPassConfig::addIRTranslator() { 217 addPass(new IRTranslator(getOptLevel())); 218 return false; 219 } 220 221 bool RISCVPassConfig::addLegalizeMachineIR() { 222 addPass(new Legalizer()); 223 return false; 224 } 225 226 bool RISCVPassConfig::addRegBankSelect() { 227 addPass(new RegBankSelect()); 228 return false; 229 } 230 231 bool RISCVPassConfig::addGlobalInstructionSelect() { 232 addPass(new InstructionSelect(getOptLevel())); 233 return false; 234 } 235 236 void RISCVPassConfig::addPreSched2() {} 237 238 void RISCVPassConfig::addPreEmitPass() { 239 addPass(&BranchRelaxationPassID); 240 addPass(createRISCVMakeCompressibleOptPass()); 241 } 242 243 void RISCVPassConfig::addPreEmitPass2() { 244 addPass(createRISCVExpandPseudoPass()); 245 // Schedule the expansion of AMOs at the last possible moment, avoiding the 246 // possibility for other passes to break the requirements for forward 247 // progress in the LR/SC block. 248 addPass(createRISCVExpandAtomicPseudoPass()); 249 } 250 251 void RISCVPassConfig::addMachineSSAOptimization() { 252 TargetPassConfig::addMachineSSAOptimization(); 253 254 if (TM->getTargetTriple().getArch() == Triple::riscv64) 255 addPass(createRISCVSExtWRemovalPass()); 256 } 257 258 void RISCVPassConfig::addPreRegAlloc() { 259 if (TM->getOptLevel() != CodeGenOpt::None) 260 addPass(createRISCVMergeBaseOffsetOptPass()); 261 addPass(createRISCVInsertVSETVLIPass()); 262 } 263 264 void RISCVPassConfig::addPostRegAlloc() { 265 if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination) 266 addPass(createRISCVRedundantCopyEliminationPass()); 267 } 268 269 yaml::MachineFunctionInfo * 270 RISCVTargetMachine::createDefaultFuncInfoYAML() const { 271 return new yaml::RISCVMachineFunctionInfo(); 272 } 273 274 yaml::MachineFunctionInfo * 275 RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const { 276 const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>(); 277 return new yaml::RISCVMachineFunctionInfo(*MFI); 278 } 279 280 bool RISCVTargetMachine::parseMachineFunctionInfo( 281 const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS, 282 SMDiagnostic &Error, SMRange &SourceRange) const { 283 const auto &YamlMFI = 284 static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI); 285 PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI); 286 return false; 287 } 288