1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Implements the info about RISCV target spec. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVTargetMachine.h" 14 #include "RISCV.h" 15 #include "RISCVTargetObjectFile.h" 16 #include "RISCVTargetTransformInfo.h" 17 #include "TargetInfo/RISCVTargetInfo.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 22 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 23 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 24 #include "llvm/CodeGen/Passes.h" 25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26 #include "llvm/CodeGen/TargetPassConfig.h" 27 #include "llvm/IR/LegacyPassManager.h" 28 #include "llvm/InitializePasses.h" 29 #include "llvm/Support/FormattedStream.h" 30 #include "llvm/Support/TargetRegistry.h" 31 #include "llvm/Target/TargetOptions.h" 32 using namespace llvm; 33 34 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { 35 RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target()); 36 RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target()); 37 auto PR = PassRegistry::getPassRegistry(); 38 initializeGlobalISel(*PR); 39 initializeRISCVExpandPseudoPass(*PR); 40 } 41 42 static StringRef computeDataLayout(const Triple &TT) { 43 if (TT.isArch64Bit()) { 44 return "e-m:e-p:64:64-i64:64-i128:128-n64-S128"; 45 } else { 46 assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported"); 47 return "e-m:e-p:32:32-i64:64-n32-S128"; 48 } 49 } 50 51 static Reloc::Model getEffectiveRelocModel(const Triple &TT, 52 Optional<Reloc::Model> RM) { 53 if (!RM.hasValue()) 54 return Reloc::Static; 55 return *RM; 56 } 57 58 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, 59 StringRef CPU, StringRef FS, 60 const TargetOptions &Options, 61 Optional<Reloc::Model> RM, 62 Optional<CodeModel::Model> CM, 63 CodeGenOpt::Level OL, bool JIT) 64 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, 65 getEffectiveRelocModel(TT, RM), 66 getEffectiveCodeModel(CM, CodeModel::Small), OL), 67 TLOF(std::make_unique<RISCVELFTargetObjectFile>()) { 68 initAsmInfo(); 69 70 // RISC-V supports the MachineOutliner. 71 setMachineOutliner(true); 72 } 73 74 const RISCVSubtarget * 75 RISCVTargetMachine::getSubtargetImpl(const Function &F) const { 76 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 77 Attribute FSAttr = F.getFnAttribute("target-features"); 78 79 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 80 ? CPUAttr.getValueAsString().str() 81 : TargetCPU; 82 std::string FS = !FSAttr.hasAttribute(Attribute::None) 83 ? FSAttr.getValueAsString().str() 84 : TargetFS; 85 std::string Key = CPU + FS; 86 auto &I = SubtargetMap[Key]; 87 if (!I) { 88 // This needs to be done before we create a new subtarget since any 89 // creation will depend on the TM and the code generation flags on the 90 // function that reside in TargetOptions. 91 resetTargetOptions(F); 92 I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, FS, 93 Options.MCOptions.getABIName(), *this); 94 } 95 return I.get(); 96 } 97 98 TargetTransformInfo 99 RISCVTargetMachine::getTargetTransformInfo(const Function &F) { 100 return TargetTransformInfo(RISCVTTIImpl(this, F)); 101 } 102 103 namespace { 104 class RISCVPassConfig : public TargetPassConfig { 105 public: 106 RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM) 107 : TargetPassConfig(TM, PM) {} 108 109 RISCVTargetMachine &getRISCVTargetMachine() const { 110 return getTM<RISCVTargetMachine>(); 111 } 112 113 void addIRPasses() override; 114 bool addInstSelector() override; 115 bool addIRTranslator() override; 116 bool addLegalizeMachineIR() override; 117 bool addRegBankSelect() override; 118 bool addGlobalInstructionSelect() override; 119 void addPreEmitPass() override; 120 void addPreEmitPass2() override; 121 void addPreRegAlloc() override; 122 }; 123 } 124 125 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { 126 return new RISCVPassConfig(*this, PM); 127 } 128 129 void RISCVPassConfig::addIRPasses() { 130 addPass(createAtomicExpandPass()); 131 TargetPassConfig::addIRPasses(); 132 } 133 134 bool RISCVPassConfig::addInstSelector() { 135 addPass(createRISCVISelDag(getRISCVTargetMachine())); 136 137 return false; 138 } 139 140 bool RISCVPassConfig::addIRTranslator() { 141 addPass(new IRTranslator()); 142 return false; 143 } 144 145 bool RISCVPassConfig::addLegalizeMachineIR() { 146 addPass(new Legalizer()); 147 return false; 148 } 149 150 bool RISCVPassConfig::addRegBankSelect() { 151 addPass(new RegBankSelect()); 152 return false; 153 } 154 155 bool RISCVPassConfig::addGlobalInstructionSelect() { 156 addPass(new InstructionSelect()); 157 return false; 158 } 159 160 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); } 161 162 void RISCVPassConfig::addPreEmitPass2() { 163 // Schedule the expansion of AMOs at the last possible moment, avoiding the 164 // possibility for other passes to break the requirements for forward 165 // progress in the LR/SC block. 166 addPass(createRISCVExpandPseudoPass()); 167 } 168 169 void RISCVPassConfig::addPreRegAlloc() { 170 addPass(createRISCVMergeBaseOffsetOptPass()); 171 } 172