1//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the symbolic operands permitted for various kinds of 10// RISC-V system instruction. 11// 12//===----------------------------------------------------------------------===// 13 14include "llvm/TableGen/SearchableTable.td" 15 16//===----------------------------------------------------------------------===// 17// CSR (control and status register read/write) instruction options. 18//===----------------------------------------------------------------------===// 19 20class SysReg<string name, bits<12> op> { 21 string Name = name; 22 // A maximum of one alias is supported right now. 23 string AltName = name; 24 // A maximum of one deprecated name is supported right now. Unlike the 25 // `AltName` alias, a `DeprecatedName` generates a diagnostic when the name is 26 // used to encourage software to migrate away from the name. 27 string DeprecatedName = ""; 28 bits<12> Encoding = op; 29 // FIXME: add these additional fields when needed. 30 // Privilege Access: Read and Write = 0, 1, 2; Read-Only = 3. 31 // Privilege Mode: User = 0, System = 1 or Machine = 3. 32 // bits<2> ReadWrite = op{11 - 10}; 33 // bits<2> XMode = op{9 - 8}; 34 // Check Extra field name and what bits 7-6 correspond to. 35 // bits<2> Extra = op{7 - 6}; 36 // Register number without the privilege bits. 37 // bits<6> Number = op{5 - 0}; 38 code FeaturesRequired = [{ {} }]; 39 bit isRV32Only = 0; 40} 41 42def SysRegsList : GenericTable { 43 let FilterClass = "SysReg"; 44 // FIXME: add "ReadWrite", "Mode", "Extra", "Number" fields when needed. 45 let Fields = [ 46 "Name", "AltName", "DeprecatedName", "Encoding", "FeaturesRequired", 47 "isRV32Only", 48 ]; 49 50 let PrimaryKey = [ "Encoding" ]; 51 let PrimaryKeyName = "lookupSysRegByEncoding"; 52} 53 54def lookupSysRegByName : SearchIndex { 55 let Table = SysRegsList; 56 let Key = [ "Name" ]; 57} 58 59def lookupSysRegByAltName : SearchIndex { 60 let Table = SysRegsList; 61 let Key = [ "AltName" ]; 62} 63 64def lookupSysRegByDeprecatedName : SearchIndex { 65 let Table = SysRegsList; 66 let Key = [ "DeprecatedName" ]; 67} 68 69// The following CSR encodings match those given in Tables 2.2, 70// 2.3, 2.4 and 2.5 in the RISC-V Instruction Set Manual 71// Volume II: Privileged Architecture. 72 73//===----------------------------------------------------------------------===// 74// User Trap Setup 75//===----------------------------------------------------------------------===// 76def : SysReg<"ustatus", 0x000>; 77def : SysReg<"uie", 0x004>; 78def : SysReg<"utvec", 0x005>; 79 80//===----------------------------------------------------------------------===// 81// User Trap Handling 82//===----------------------------------------------------------------------===// 83def : SysReg<"uscratch", 0x040>; 84def : SysReg<"uepc", 0x041>; 85def : SysReg<"ucause", 0x042>; 86let DeprecatedName = "ubadaddr" in 87def : SysReg<"utval", 0x043>; 88def : SysReg<"uip", 0x044>; 89 90//===----------------------------------------------------------------------===// 91// User Floating-Point CSRs 92//===----------------------------------------------------------------------===// 93 94def SysRegFFLAGS : SysReg<"fflags", 0x001>; 95def SysRegFRM : SysReg<"frm", 0x002>; 96def SysRegFCSR : SysReg<"fcsr", 0x003>; 97 98//===----------------------------------------------------------------------===// 99// User Counter/Timers 100//===----------------------------------------------------------------------===// 101def CYCLE : SysReg<"cycle", 0xC00>; 102def TIME : SysReg<"time", 0xC01>; 103def INSTRET : SysReg<"instret", 0xC02>; 104 105// hpmcounter3-hpmcounter31 at 0xC03-0xC1F. 106foreach i = 3...31 in 107 def : SysReg<"hpmcounter"#i, !add(0xC03, !sub(i, 3))>; 108 109let isRV32Only = 1 in { 110def CYCLEH : SysReg<"cycleh", 0xC80>; 111def TIMEH : SysReg<"timeh", 0xC81>; 112def INSTRETH : SysReg<"instreth", 0xC82>; 113 114// hpmcounter3h-hpmcounter31h at 0xC83-0xC9F. 115foreach i = 3...31 in 116 def : SysReg<"hpmcounter"#i#"h", !add(0xC83, !sub(i, 3))>; 117} 118 119//===----------------------------------------------------------------------===// 120// Supervisor Trap Setup 121//===----------------------------------------------------------------------===// 122def : SysReg<"sstatus", 0x100>; 123def : SysReg<"sedeleg", 0x102>; 124def : SysReg<"sideleg", 0x103>; 125def : SysReg<"sie", 0x104>; 126def : SysReg<"stvec", 0x105>; 127def : SysReg<"scounteren", 0x106>; 128def : SysReg<"stimecmp", 0x14D>; 129let isRV32Only = 1 in 130def : SysReg<"stimecmph", 0x15D>; 131 132//===----------------------------------------------------------------------===// 133// Supervisor Configuration 134//===----------------------------------------------------------------------===// 135 136def : SysReg<"senvcfg", 0x10A>; 137 138//===----------------------------------------------------------------------===// 139// Supervisor Trap Handling 140//===----------------------------------------------------------------------===// 141def : SysReg<"sscratch", 0x140>; 142def : SysReg<"sepc", 0x141>; 143def : SysReg<"scause", 0x142>; 144let DeprecatedName = "sbadaddr" in 145def : SysReg<"stval", 0x143>; 146def : SysReg<"sip", 0x144>; 147 148//===----------------------------------------------------------------------===// 149// Supervisor Protection and Translation 150//===----------------------------------------------------------------------===// 151let DeprecatedName = "sptbr" in 152def : SysReg<"satp", 0x180>; 153 154//===----------------------------------------------------------------------===// 155// Debug/Trace Registers 156//===----------------------------------------------------------------------===// 157 158def : SysReg<"scontext", 0x5A8>; 159 160//===----------------------------------------------------------------------===// 161// Supervisor Count Overflow (defined in Sscofpmf) 162//===----------------------------------------------------------------------===// 163 164def : SysReg<"scountovf", 0xDA0>; 165 166//===----------------------------------------------------------------------===// 167// Hypervisor Trap Setup 168//===----------------------------------------------------------------------===// 169 170def : SysReg<"hstatus", 0x600>; 171def : SysReg<"hedeleg", 0x602>; 172def : SysReg<"hideleg", 0x603>; 173def : SysReg<"hie", 0x604>; 174def : SysReg<"hcounteren", 0x606>; 175def : SysReg<"hgeie", 0x607>; 176 177//===----------------------------------------------------------------------===// 178// Hypervisor Trap Handling 179//===----------------------------------------------------------------------===// 180 181def : SysReg<"htval", 0x643>; 182def : SysReg<"hip", 0x644>; 183def : SysReg<"hvip", 0x645>; 184def : SysReg<"htinst", 0x64A>; 185def : SysReg<"hgeip", 0xE12>; 186 187//===----------------------------------------------------------------------===// 188// Hypervisor Configuration 189//===----------------------------------------------------------------------===// 190 191def : SysReg<"henvcfg", 0x60A>; 192let isRV32Only = 1 in 193def : SysReg<"henvcfgh", 0x61A>; 194 195//===----------------------------------------------------------------------===// 196// Hypervisor Protection and Translation 197//===----------------------------------------------------------------------===// 198 199def : SysReg<"hgatp", 0x680>; 200 201//===----------------------------------------------------------------------===// 202// Debug/Trace Registers 203//===----------------------------------------------------------------------===// 204 205def : SysReg<"hcontext", 0x6A8>; 206 207//===----------------------------------------------------------------------===// 208// Hypervisor Counter/Timer Virtualization Registers 209//===----------------------------------------------------------------------===// 210 211def : SysReg<"htimedelta", 0x605>; 212let isRV32Only = 1 in 213def : SysReg<"htimedeltah", 0x615>; 214 215//===----------------------------------------------------------------------===// 216// Virtual Supervisor Registers 217//===----------------------------------------------------------------------===// 218 219def : SysReg<"vsstatus", 0x200>; 220def : SysReg<"vsie", 0x204>; 221def : SysReg<"vstvec", 0x205>; 222def : SysReg<"vsscratch", 0x240>; 223def : SysReg<"vsepc", 0x241>; 224def : SysReg<"vscause", 0x242>; 225def : SysReg<"vstval", 0x243>; 226def : SysReg<"vsip", 0x244>; 227def : SysReg<"vstimecmp", 0x24D>; 228let isRV32Only = 1 in 229def : SysReg<"vstimecmph", 0x25D>; 230def : SysReg<"vsatp", 0x280>; 231 232//===----------------------------------------------------------------------===// 233// Machine Information Registers 234//===----------------------------------------------------------------------===// 235 236def : SysReg<"mvendorid", 0xF11>; 237def : SysReg<"marchid", 0xF12>; 238def : SysReg<"mimpid", 0xF13>; 239def : SysReg<"mhartid", 0xF14>; 240def : SysReg<"mconfigptr", 0xF15>; 241 242//===----------------------------------------------------------------------===// 243// Machine Trap Setup 244//===----------------------------------------------------------------------===// 245def : SysReg<"mstatus", 0x300>; 246def : SysReg<"misa", 0x301>; 247def : SysReg<"medeleg", 0x302>; 248def : SysReg<"mideleg", 0x303>; 249def : SysReg<"mie", 0x304>; 250def : SysReg<"mtvec", 0x305>; 251def : SysReg<"mcounteren", 0x306>; 252let isRV32Only = 1 in 253def : SysReg<"mstatush", 0x310>; 254 255//===----------------------------------------------------------------------===// 256// Machine Trap Handling 257//===----------------------------------------------------------------------===// 258def : SysReg<"mscratch", 0x340>; 259def : SysReg<"mepc", 0x341>; 260def : SysReg<"mcause", 0x342>; 261let DeprecatedName = "mbadaddr" in 262def : SysReg<"mtval", 0x343>; 263def : SysReg<"mip", 0x344>; 264def : SysReg<"mtinst", 0x34A>; 265def : SysReg<"mtval2", 0x34B>; 266 267//===----------------------------------------------------------------------===// 268// Machine Configuration 269//===----------------------------------------------------------------------===// 270 271def : SysReg<"menvcfg", 0x30A>; 272let isRV32Only = 1 in 273def : SysReg<"menvcfgh", 0x31A>; 274def : SysReg<"mseccfg", 0x747>; 275let isRV32Only = 1 in 276def : SysReg<"mseccfgh", 0x757>; 277 278//===----------------------------------------------------------------------===// 279// Machine Protection and Translation 280//===----------------------------------------------------------------------===// 281 282// pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only. 283foreach i = 0...15 in { 284 let isRV32Only = !and(i, 1) in 285 def : SysReg<"pmpcfg"#i, !add(0x3A0, i)>; 286} 287 288// pmpaddr0-pmpaddr63 at 0x3B0-0x3EF. 289foreach i = 0...63 in 290 def : SysReg<"pmpaddr"#i, !add(0x3B0, i)>; 291 292//===----------------------------------------------------------------------===// 293// Machine Counter and Timers 294//===----------------------------------------------------------------------===// 295def : SysReg<"mcycle", 0xB00>; 296def : SysReg<"minstret", 0xB02>; 297 298// mhpmcounter3-mhpmcounter31 at 0xB03-0xB1F. 299foreach i = 3...31 in 300 def : SysReg<"mhpmcounter"#i, !add(0xB03, !sub(i, 3))>; 301 302let isRV32Only = 1 in { 303def: SysReg<"mcycleh", 0xB80>; 304def: SysReg<"minstreth", 0xB82>; 305 306// mhpmcounter3h-mhpmcounter31h at 0xB83-0xB9F. 307foreach i = 3...31 in 308 def : SysReg<"mhpmcounter"#i#"h", !add(0xB83, !sub(i, 3))>; 309} 310 311//===----------------------------------------------------------------------===// 312// Machine Counter Setup 313//===----------------------------------------------------------------------===// 314let AltName = "mucounteren" in // Privileged spec v1.9.1 Name 315def : SysReg<"mcountinhibit", 0x320>; 316 317// mhpmevent3-mhpmevent31 at 0x323-0x33F. 318foreach i = 3...31 in 319 def : SysReg<"mhpmevent"#i, !add(0x323, !sub(i, 3))>; 320 321// mhpmevent3h-mhpmevent31h at 0x723-0x73F 322foreach i = 3...31 in { 323 let isRV32Only = 1 in 324 def : SysReg<"mhpmevent"#i#"h", !add(0x723, !sub(i, 3))>; 325} 326 327//===----------------------------------------------------------------------===// 328// Debug/ Trace Registers (shared with Debug Mode) 329//===----------------------------------------------------------------------===// 330def : SysReg<"tselect", 0x7A0>; 331def : SysReg<"tdata1", 0x7A1>; 332def : SysReg<"tdata2", 0x7A2>; 333def : SysReg<"tdata3", 0x7A3>; 334def : SysReg<"mcontext", 0x7A8>; 335 336//===----------------------------------------------------------------------===// 337// Debug Mode Registers 338//===----------------------------------------------------------------------===// 339def : SysReg<"dcsr", 0x7B0>; 340def : SysReg<"dpc", 0x7B1>; 341 342// "dscratch" is an alternative name for "dscratch0" which appeared in earlier 343// drafts of the RISC-V debug spec 344let AltName = "dscratch" in 345def : SysReg<"dscratch0", 0x7B2>; 346def : SysReg<"dscratch1", 0x7B3>; 347 348//===----------------------------------------------------------------------===// 349// User Vector CSRs 350//===----------------------------------------------------------------------===// 351def : SysReg<"vstart", 0x008>; 352def : SysReg<"vxsat", 0x009>; 353def : SysReg<"vxrm", 0x00A>; 354def : SysReg<"vcsr", 0x00F>; 355def : SysReg<"vl", 0xC20>; 356def : SysReg<"vtype", 0xC21>; 357def SysRegVLENB: SysReg<"vlenb", 0xC22>; 358 359//===----------------------------------------------------------------------===// 360// State Enable Extension (Smstateen) 361//===----------------------------------------------------------------------===// 362 363// sstateen0-sstateen3 at 0x10C-0x10F, mstateen0-mstateen3 at 0x30C-0x30F, 364// mstateen0h-mstateen3h at 0x31C-0x31F, hstateen0-hstateen3 at 0x60C-0x60F, 365// and hstateen0h-hstateen3h at 0x61C-0x61F. 366foreach i = 0...3 in { 367 def : SysReg<"sstateen"#i, !add(0x10C, i)>; 368 def : SysReg<"mstateen"#i, !add(0x30C, i)>; 369 let isRV32Only = 1 in 370 def : SysReg<"mstateen"#i#"h", !add(0x31C, i)>; 371 def : SysReg<"hstateen"#i, !add(0x60C, i)>; 372 let isRV32Only = 1 in 373 def : SysReg<"hstateen"#i#"h", !add(0x61C, i)>; 374} 375 376//===----------------------------------------------- 377// Entropy Source CSR 378//===----------------------------------------------- 379 380def SEED : SysReg<"seed", 0x015>; 381