1 //===-- RISCVSubtarget.h - Define Subtarget for the RISCV -------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the RISCV specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H 14 #define LLVM_LIB_TARGET_RISCV_RISCVSUBTARGET_H 15 16 #include "MCTargetDesc/RISCVBaseInfo.h" 17 #include "RISCVFrameLowering.h" 18 #include "RISCVISelLowering.h" 19 #include "RISCVInstrInfo.h" 20 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 21 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 22 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 23 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" 24 #include "llvm/CodeGen/SelectionDAGTargetInfo.h" 25 #include "llvm/CodeGen/TargetSubtargetInfo.h" 26 #include "llvm/IR/DataLayout.h" 27 #include "llvm/Target/TargetMachine.h" 28 29 #define GET_SUBTARGETINFO_HEADER 30 #include "RISCVGenSubtargetInfo.inc" 31 32 namespace llvm { 33 class StringRef; 34 35 class RISCVSubtarget : public RISCVGenSubtargetInfo { 36 public: 37 enum ExtZvl : unsigned { 38 NotSet = 0, 39 Zvl32b = 32, 40 Zvl64b = 64, 41 Zvl128b = 128, 42 Zvl256b = 256, 43 Zvl512b = 512, 44 Zvl1024b = 1024, 45 Zvl2048b = 2048, 46 Zvl4096b = 4096, 47 Zvl8192b = 8192, 48 Zvl16384b = 16384, 49 Zvl32768b = 32768, 50 Zvl65536b = 65536 51 }; 52 53 enum RISCVProcFamilyEnum : uint8_t { 54 Others, 55 SiFive7, 56 }; 57 58 private: 59 virtual void anchor(); 60 61 RISCVProcFamilyEnum RISCVProcFamily = Others; 62 63 bool HasStdExtM = false; 64 bool HasStdExtA = false; 65 bool HasStdExtF = false; 66 bool HasStdExtD = false; 67 bool HasStdExtC = false; 68 bool HasStdExtZba = false; 69 bool HasStdExtZbb = false; 70 bool HasStdExtZbc = false; 71 bool HasStdExtZbe = false; 72 bool HasStdExtZbf = false; 73 bool HasStdExtZbm = false; 74 bool HasStdExtZbp = false; 75 bool HasStdExtZbr = false; 76 bool HasStdExtZbs = false; 77 bool HasStdExtZbt = false; 78 bool HasStdExtV = false; 79 bool HasStdExtZve32x = false; 80 bool HasStdExtZve32f = false; 81 bool HasStdExtZve64x = false; 82 bool HasStdExtZve64f = false; 83 bool HasStdExtZve64d = false; 84 bool HasStdExtZfhmin = false; 85 bool HasStdExtZfh = false; 86 bool HasStdExtZfinx = false; 87 bool HasStdExtZdinx = false; 88 bool HasStdExtZhinxmin = false; 89 bool HasStdExtZhinx = false; 90 bool HasStdExtZbkb = false; 91 bool HasStdExtZbkc = false; 92 bool HasStdExtZbkx = false; 93 bool HasStdExtZknd = false; 94 bool HasStdExtZkne = false; 95 bool HasStdExtZknh = false; 96 bool HasStdExtZksed = false; 97 bool HasStdExtZksh = false; 98 bool HasStdExtZkr = false; 99 bool HasStdExtZkn = false; 100 bool HasStdExtZks = false; 101 bool HasStdExtZkt = false; 102 bool HasStdExtZk = false; 103 bool HasRV64 = false; 104 bool IsRV32E = false; 105 bool EnableLinkerRelax = false; 106 bool EnableRVCHintInstrs = true; 107 bool EnableSaveRestore = false; 108 unsigned XLen = 32; 109 ExtZvl ZvlLen = ExtZvl::NotSet; 110 MVT XLenVT = MVT::i32; 111 uint8_t MaxInterleaveFactor = 2; 112 RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; 113 BitVector UserReservedRegister; 114 RISCVFrameLowering FrameLowering; 115 RISCVInstrInfo InstrInfo; 116 RISCVRegisterInfo RegInfo; 117 RISCVTargetLowering TLInfo; 118 SelectionDAGTargetInfo TSInfo; 119 120 /// Initializes using the passed in CPU and feature strings so that we can 121 /// use initializer lists for subtarget initialization. 122 RISCVSubtarget &initializeSubtargetDependencies(const Triple &TT, 123 StringRef CPU, 124 StringRef TuneCPU, 125 StringRef FS, 126 StringRef ABIName); 127 128 public: 129 // Initializes the data members to match that of the specified triple. 130 RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, 131 StringRef FS, StringRef ABIName, const TargetMachine &TM); 132 133 // Parses features string setting specified subtarget options. The 134 // definition of this function is auto-generated by tblgen. 135 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 136 137 const RISCVFrameLowering *getFrameLowering() const override { 138 return &FrameLowering; 139 } 140 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; } 141 const RISCVRegisterInfo *getRegisterInfo() const override { 142 return &RegInfo; 143 } 144 const RISCVTargetLowering *getTargetLowering() const override { 145 return &TLInfo; 146 } 147 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { 148 return &TSInfo; 149 } 150 bool enableMachineScheduler() const override { return true; } 151 152 /// Returns RISCV processor family. 153 /// Avoid this function! CPU specifics should be kept local to this class 154 /// and preferably modeled with SubtargetFeatures or properties in 155 /// initializeProperties(). 156 RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } 157 158 bool hasStdExtM() const { return HasStdExtM; } 159 bool hasStdExtA() const { return HasStdExtA; } 160 bool hasStdExtF() const { return HasStdExtF; } 161 bool hasStdExtD() const { return HasStdExtD; } 162 bool hasStdExtC() const { return HasStdExtC; } 163 bool hasStdExtV() const { return HasStdExtV; } 164 bool hasStdExtZba() const { return HasStdExtZba; } 165 bool hasStdExtZbb() const { return HasStdExtZbb; } 166 bool hasStdExtZbc() const { return HasStdExtZbc; } 167 bool hasStdExtZbe() const { return HasStdExtZbe; } 168 bool hasStdExtZbf() const { return HasStdExtZbf; } 169 bool hasStdExtZbm() const { return HasStdExtZbm; } 170 bool hasStdExtZbp() const { return HasStdExtZbp; } 171 bool hasStdExtZbr() const { return HasStdExtZbr; } 172 bool hasStdExtZbs() const { return HasStdExtZbs; } 173 bool hasStdExtZbt() const { return HasStdExtZbt; } 174 bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; } 175 bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } 176 bool hasStdExtZfh() const { return HasStdExtZfh; } 177 bool hasStdExtZfinx() const { return HasStdExtZfinx; } 178 bool hasStdExtZdinx() const { return HasStdExtZdinx; } 179 bool hasStdExtZhinxmin() const { return HasStdExtZhinxmin; } 180 bool hasStdExtZhinx() const { return HasStdExtZhinx; } 181 bool hasStdExtZbkb() const { return HasStdExtZbkb; } 182 bool hasStdExtZbkc() const { return HasStdExtZbkc; } 183 bool hasStdExtZbkx() const { return HasStdExtZbkx; } 184 bool hasStdExtZknd() const { return HasStdExtZknd; } 185 bool hasStdExtZkne() const { return HasStdExtZkne; } 186 bool hasStdExtZknh() const { return HasStdExtZknh; } 187 bool hasStdExtZksed() const { return HasStdExtZksed; } 188 bool hasStdExtZksh() const { return HasStdExtZksh; } 189 bool hasStdExtZkr() const { return HasStdExtZkr; } 190 bool is64Bit() const { return HasRV64; } 191 bool isRV32E() const { return IsRV32E; } 192 bool enableLinkerRelax() const { return EnableLinkerRelax; } 193 bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; } 194 bool enableSaveRestore() const { return EnableSaveRestore; } 195 MVT getXLenVT() const { return XLenVT; } 196 unsigned getXLen() const { return XLen; } 197 unsigned getFLen() const { 198 if (HasStdExtD) 199 return 64; 200 201 if (HasStdExtF) 202 return 32; 203 204 return 0; 205 } 206 unsigned getMinVLen() const { return ZvlLen; } 207 RISCVABI::ABI getTargetABI() const { return TargetABI; } 208 bool isRegisterReservedByUser(Register i) const { 209 assert(i < RISCV::NUM_TARGET_REGS && "Register out of range"); 210 return UserReservedRegister[i]; 211 } 212 213 // Vector codegen related methods. 214 bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; } 215 bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; } 216 bool hasVInstructionsF16() const { 217 return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh; 218 } 219 // FIXME: Consider Zfinx in the future 220 bool hasVInstructionsF32() const { 221 return HasStdExtV || (HasStdExtZve32f && HasStdExtF); 222 } 223 // FIXME: Consider Zdinx in the future 224 bool hasVInstructionsF64() const { 225 return HasStdExtV || (HasStdExtZve64d && HasStdExtD); 226 } 227 // F16 and F64 both require F32. 228 bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } 229 unsigned getMaxInterleaveFactor() const { 230 return hasVInstructions() ? MaxInterleaveFactor : 1; 231 } 232 233 protected: 234 // GlobalISel related APIs. 235 std::unique_ptr<CallLowering> CallLoweringInfo; 236 std::unique_ptr<InstructionSelector> InstSelector; 237 std::unique_ptr<LegalizerInfo> Legalizer; 238 std::unique_ptr<RegisterBankInfo> RegBankInfo; 239 240 public: 241 const CallLowering *getCallLowering() const override; 242 InstructionSelector *getInstructionSelector() const override; 243 const LegalizerInfo *getLegalizerInfo() const override; 244 const RegisterBankInfo *getRegBankInfo() const override; 245 246 bool useConstantPoolForLargeInts() const; 247 248 // Maximum cost used for building integers, integers will be put into constant 249 // pool if exceeded. 250 unsigned getMaxBuildIntsCost() const; 251 252 // Return the known range for the bit length of RVV data registers. A value 253 // of 0 means nothing is known about that particular limit beyond what's 254 // implied by the architecture. 255 unsigned getMaxRVVVectorSizeInBits() const; 256 unsigned getMinRVVVectorSizeInBits() const; 257 unsigned getMaxLMULForFixedLengthVectors() const; 258 unsigned getMaxELENForFixedLengthVectors() const; 259 bool useRVVForFixedLengthVectors() const; 260 }; 261 } // End llvm namespace 262 263 #endif 264