1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCV specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVSubtarget.h" 14 #include "RISCV.h" 15 #include "RISCVCallLowering.h" 16 #include "RISCVFrameLowering.h" 17 #include "RISCVLegalizerInfo.h" 18 #include "RISCVMacroFusion.h" 19 #include "RISCVRegisterBankInfo.h" 20 #include "RISCVTargetMachine.h" 21 #include "llvm/MC/TargetRegistry.h" 22 #include "llvm/Support/ErrorHandling.h" 23 24 using namespace llvm; 25 26 #define DEBUG_TYPE "riscv-subtarget" 27 28 #define GET_SUBTARGETINFO_TARGET_DESC 29 #define GET_SUBTARGETINFO_CTOR 30 #include "RISCVGenSubtargetInfo.inc" 31 32 static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness", 33 cl::init(false), cl::Hidden); 34 35 static cl::opt<int> RVVVectorBitsMax( 36 "riscv-v-vector-bits-max", 37 cl::desc("Assume V extension vector registers are at most this big, " 38 "with zero meaning no maximum size is assumed."), 39 cl::init(0), cl::Hidden); 40 41 static cl::opt<int> RVVVectorBitsMin( 42 "riscv-v-vector-bits-min", 43 cl::desc("Assume V extension vector registers are at least this big, " 44 "with zero meaning no minimum size is assumed. A value of -1 " 45 "means use Zvl*b extension. This is primarily used to enable " 46 "autovectorization with fixed width vectors."), 47 cl::init(0), cl::Hidden); 48 49 static cl::opt<unsigned> RVVVectorLMULMax( 50 "riscv-v-fixed-length-vector-lmul-max", 51 cl::desc("The maximum LMUL value to use for fixed length vectors. " 52 "Fractional LMUL values are not supported."), 53 cl::init(8), cl::Hidden); 54 55 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts( 56 "riscv-disable-using-constant-pool-for-large-ints", 57 cl::desc("Disable using constant pool for large integers."), 58 cl::init(false), cl::Hidden); 59 60 static cl::opt<unsigned> RISCVMaxBuildIntsCost( 61 "riscv-max-build-ints-cost", 62 cl::desc("The maximum cost used for building integers."), cl::init(0), 63 cl::Hidden); 64 65 void RISCVSubtarget::anchor() {} 66 67 RISCVSubtarget & 68 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, 69 StringRef TuneCPU, StringRef FS, 70 StringRef ABIName) { 71 // Determine default and user-specified characteristics 72 bool Is64Bit = TT.isArch64Bit(); 73 if (CPU.empty() || CPU == "generic") 74 CPU = Is64Bit ? "generic-rv64" : "generic-rv32"; 75 76 if (TuneCPU.empty()) 77 TuneCPU = CPU; 78 79 ParseSubtargetFeatures(CPU, TuneCPU, FS); 80 if (Is64Bit) { 81 XLenVT = MVT::i64; 82 XLen = 64; 83 } 84 85 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); 86 RISCVFeatures::validate(TT, getFeatureBits()); 87 return *this; 88 } 89 90 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, 91 StringRef TuneCPU, StringRef FS, 92 StringRef ABIName, const TargetMachine &TM) 93 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS), 94 UserReservedRegister(RISCV::NUM_TARGET_REGS), 95 FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), 96 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { 97 CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); 98 Legalizer.reset(new RISCVLegalizerInfo(*this)); 99 100 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); 101 RegBankInfo.reset(RBI); 102 InstSelector.reset(createRISCVInstructionSelector( 103 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); 104 } 105 106 const CallLowering *RISCVSubtarget::getCallLowering() const { 107 return CallLoweringInfo.get(); 108 } 109 110 InstructionSelector *RISCVSubtarget::getInstructionSelector() const { 111 return InstSelector.get(); 112 } 113 114 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const { 115 return Legalizer.get(); 116 } 117 118 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const { 119 return RegBankInfo.get(); 120 } 121 122 bool RISCVSubtarget::useConstantPoolForLargeInts() const { 123 return !RISCVDisableUsingConstantPoolForLargeInts; 124 } 125 126 unsigned RISCVSubtarget::getMaxBuildIntsCost() const { 127 // Loading integer from constant pool needs two instructions (the reason why 128 // the minimum cost is 2): an address calculation instruction and a load 129 // instruction. Usually, address calculation and instructions used for 130 // building integers (addi, slli, etc.) can be done in one cycle, so here we 131 // set the default cost to (LoadLatency + 1) if no threshold is provided. 132 return RISCVMaxBuildIntsCost == 0 133 ? getSchedModel().LoadLatency + 1 134 : std::max<unsigned>(2, RISCVMaxBuildIntsCost); 135 } 136 137 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const { 138 assert(hasVInstructions() && 139 "Tried to get vector length without Zve or V extension support!"); 140 if (RVVVectorBitsMax == 0) 141 return 0; 142 143 // ZvlLen specifies the minimum required vlen. The upper bound provided by 144 // riscv-v-vector-bits-max should be no less than it. 145 if (RVVVectorBitsMax < (int)ZvlLen) 146 report_fatal_error("riscv-v-vector-bits-max specified is lower " 147 "than the Zvl*b limitation"); 148 149 // FIXME: Change to >= 32 when VLEN = 32 is supported 150 assert( 151 RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 && 152 isPowerOf2_32(RVVVectorBitsMax) && 153 "V or Zve* extension requires vector length to be in the range of 64 to " 154 "65536 and a power of 2!"); 155 assert(RVVVectorBitsMax >= RVVVectorBitsMin && 156 "Minimum V extension vector length should not be larger than its " 157 "maximum!"); 158 unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax); 159 return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max); 160 } 161 162 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const { 163 assert(hasVInstructions() && 164 "Tried to get vector length without Zve or V extension support!"); 165 166 if (RVVVectorBitsMin == -1) 167 return ZvlLen; 168 169 // ZvlLen specifies the minimum required vlen. The lower bound provided by 170 // riscv-v-vector-bits-min should be no less than it. 171 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < (int)ZvlLen) 172 report_fatal_error("riscv-v-vector-bits-min specified is lower " 173 "than the Zvl*b limitation"); 174 175 // FIXME: Change to >= 32 when VLEN = 32 is supported 176 assert( 177 (RVVVectorBitsMin == 0 || 178 (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 && 179 isPowerOf2_32(RVVVectorBitsMin))) && 180 "V or Zve* extension requires vector length to be in the range of 64 to " 181 "65536 and a power of 2!"); 182 assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) && 183 "Minimum V extension vector length should not be larger than its " 184 "maximum!"); 185 unsigned Min = RVVVectorBitsMin; 186 if (RVVVectorBitsMax != 0) 187 Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax); 188 return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min); 189 } 190 191 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const { 192 assert(hasVInstructions() && 193 "Tried to get vector length without Zve or V extension support!"); 194 assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) && 195 "V extension requires a LMUL to be at most 8 and a power of 2!"); 196 return PowerOf2Floor( 197 std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1)); 198 } 199 200 bool RISCVSubtarget::useRVVForFixedLengthVectors() const { 201 return hasVInstructions() && getMinRVVVectorSizeInBits() != 0; 202 } 203 204 bool RISCVSubtarget::enableSubRegLiveness() const { 205 // FIXME: Enable subregister liveness by default for RVV to better handle 206 // LMUL>1 and segment load/store. 207 return EnableSubRegLiveness; 208 } 209 210 void RISCVSubtarget::getPostRAMutations( 211 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { 212 Mutations.push_back(createRISCVMacroFusionDAGMutation()); 213 } 214