1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCV specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVSubtarget.h" 14 #include "RISCV.h" 15 #include "RISCVCallLowering.h" 16 #include "RISCVFrameLowering.h" 17 #include "RISCVLegalizerInfo.h" 18 #include "RISCVRegisterBankInfo.h" 19 #include "RISCVTargetMachine.h" 20 #include "llvm/MC/TargetRegistry.h" 21 #include "llvm/Support/ErrorHandling.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "riscv-subtarget" 26 27 #define GET_SUBTARGETINFO_TARGET_DESC 28 #define GET_SUBTARGETINFO_CTOR 29 #include "RISCVGenSubtargetInfo.inc" 30 31 static cl::opt<unsigned> RVVVectorBitsMax( 32 "riscv-v-vector-bits-max", 33 cl::desc("Assume V extension vector registers are at most this big, " 34 "with zero meaning no maximum size is assumed."), 35 cl::init(0), cl::Hidden); 36 37 static cl::opt<unsigned> RVVVectorBitsMin( 38 "riscv-v-vector-bits-min", 39 cl::desc("Assume V extension vector registers are at least this big, " 40 "with zero meaning no minimum size is assumed."), 41 cl::init(0), cl::Hidden); 42 43 static cl::opt<unsigned> RVVVectorLMULMax( 44 "riscv-v-fixed-length-vector-lmul-max", 45 cl::desc("The maximum LMUL value to use for fixed length vectors. " 46 "Fractional LMUL values are not supported."), 47 cl::init(8), cl::Hidden); 48 49 static cl::opt<unsigned> RVVVectorELENMax( 50 "riscv-v-fixed-length-vector-elen-max", 51 cl::desc("The maximum ELEN value to use for fixed length vectors."), 52 cl::init(64), cl::Hidden); 53 54 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts( 55 "riscv-disable-using-constant-pool-for-large-ints", 56 cl::desc("Disable using constant pool for large integers."), 57 cl::init(false), cl::Hidden); 58 59 static cl::opt<unsigned> RISCVMaxBuildIntsCost( 60 "riscv-max-build-ints-cost", 61 cl::desc("The maximum cost used for building integers."), cl::init(0), 62 cl::Hidden); 63 64 void RISCVSubtarget::anchor() {} 65 66 RISCVSubtarget & 67 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU, 68 StringRef TuneCPU, StringRef FS, 69 StringRef ABIName) { 70 // Determine default and user-specified characteristics 71 bool Is64Bit = TT.isArch64Bit(); 72 if (CPU.empty()) 73 CPU = Is64Bit ? "generic-rv64" : "generic-rv32"; 74 if (CPU == "generic") 75 report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + 76 (Is64Bit ? "generic-rv64" : "generic-rv32")); 77 78 if (TuneCPU.empty()) 79 TuneCPU = CPU; 80 81 ParseSubtargetFeatures(CPU, TuneCPU, FS); 82 if (Is64Bit) { 83 XLenVT = MVT::i64; 84 XLen = 64; 85 } 86 87 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); 88 RISCVFeatures::validate(TT, getFeatureBits()); 89 return *this; 90 } 91 92 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, 93 StringRef TuneCPU, StringRef FS, 94 StringRef ABIName, const TargetMachine &TM) 95 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS), 96 UserReservedRegister(RISCV::NUM_TARGET_REGS), 97 FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), 98 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { 99 CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); 100 Legalizer.reset(new RISCVLegalizerInfo(*this)); 101 102 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); 103 RegBankInfo.reset(RBI); 104 InstSelector.reset(createRISCVInstructionSelector( 105 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); 106 } 107 108 const CallLowering *RISCVSubtarget::getCallLowering() const { 109 return CallLoweringInfo.get(); 110 } 111 112 InstructionSelector *RISCVSubtarget::getInstructionSelector() const { 113 return InstSelector.get(); 114 } 115 116 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const { 117 return Legalizer.get(); 118 } 119 120 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const { 121 return RegBankInfo.get(); 122 } 123 124 bool RISCVSubtarget::useConstantPoolForLargeInts() const { 125 return !RISCVDisableUsingConstantPoolForLargeInts; 126 } 127 128 unsigned RISCVSubtarget::getMaxBuildIntsCost() const { 129 // Loading integer from constant pool needs two instructions (the reason why 130 // the minimum cost is 2): an address calculation instruction and a load 131 // instruction. Usually, address calculation and instructions used for 132 // building integers (addi, slli, etc.) can be done in one cycle, so here we 133 // set the default cost to (LoadLatency + 1) if no threshold is provided. 134 return RISCVMaxBuildIntsCost == 0 135 ? getSchedModel().LoadLatency + 1 136 : std::max<unsigned>(2, RISCVMaxBuildIntsCost); 137 } 138 139 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const { 140 assert(hasVInstructions() && 141 "Tried to get vector length without Zve or V extension support!"); 142 if (RVVVectorBitsMax == 0) 143 return 0; 144 145 // ZvlLen specifies the minimum required vlen. The upper bound provided by 146 // riscv-v-vector-bits-max should be no less than it. 147 if (RVVVectorBitsMax < ZvlLen) 148 report_fatal_error("riscv-v-vector-bits-max specified is lower " 149 "than the Zvl*b limitation"); 150 151 // FIXME: Change to >= 32 when VLEN = 32 is supported 152 assert( 153 RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 && 154 isPowerOf2_32(RVVVectorBitsMax) && 155 "V or Zve* extension requires vector length to be in the range of 64 to " 156 "65536 and a power of 2!"); 157 assert(RVVVectorBitsMax >= RVVVectorBitsMin && 158 "Minimum V extension vector length should not be larger than its " 159 "maximum!"); 160 unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax); 161 return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max); 162 } 163 164 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const { 165 // ZvlLen specifies the minimum required vlen. The lower bound provided by 166 // riscv-v-vector-bits-min should be no less than it. 167 if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen) 168 report_fatal_error("riscv-v-vector-bits-min specified is lower " 169 "than the Zvl*b limitation"); 170 171 assert(hasVInstructions() && 172 "Tried to get vector length without Zve or V extension support!"); 173 // FIXME: Change to >= 32 when VLEN = 32 is supported 174 assert( 175 (RVVVectorBitsMin == 0 || 176 (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 && 177 isPowerOf2_32(RVVVectorBitsMin))) && 178 "V or Zve* extension requires vector length to be in the range of 64 to " 179 "65536 and a power of 2!"); 180 assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) && 181 "Minimum V extension vector length should not be larger than its " 182 "maximum!"); 183 unsigned Min = RVVVectorBitsMin; 184 if (RVVVectorBitsMax != 0) 185 Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax); 186 return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min); 187 } 188 189 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const { 190 assert(hasVInstructions() && 191 "Tried to get vector length without Zve or V extension support!"); 192 assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) && 193 "V extension requires a LMUL to be at most 8 and a power of 2!"); 194 return PowerOf2Floor( 195 std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1)); 196 } 197 198 unsigned RISCVSubtarget::getMaxELENForFixedLengthVectors() const { 199 assert(hasVInstructions() && 200 "Tried to get maximum ELEN without Zve or V extension support!"); 201 assert(RVVVectorELENMax <= 64 && RVVVectorELENMax >= 8 && 202 isPowerOf2_32(RVVVectorELENMax) && 203 "V extension requires a ELEN to be a power of 2 between 8 and 64!"); 204 unsigned ELEN = hasVInstructionsI64() ? 64 : 32; 205 return PowerOf2Floor( 206 std::max<unsigned>(std::min<unsigned>(RVVVectorELENMax, ELEN), 8)); 207 } 208 209 bool RISCVSubtarget::useRVVForFixedLengthVectors() const { 210 return hasVInstructions() && getMinRVVVectorSizeInBits() != 0; 211 } 212