1*700637cbSDimitry Andric //===----------------------------------------------------------------------===// 2*700637cbSDimitry Andric // 3*700637cbSDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*700637cbSDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*700637cbSDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*700637cbSDimitry Andric // 7*700637cbSDimitry Andric //===----------------------------------------------------------------------===// 8*700637cbSDimitry Andric 9*700637cbSDimitry Andric #include "RISCVSelectionDAGInfo.h" 10*700637cbSDimitry Andric 11*700637cbSDimitry Andric #define GET_SDNODE_DESC 12*700637cbSDimitry Andric #include "RISCVGenSDNodeInfo.inc" 13*700637cbSDimitry Andric 14*700637cbSDimitry Andric using namespace llvm; 15*700637cbSDimitry Andric RISCVSelectionDAGInfo()16*700637cbSDimitry AndricRISCVSelectionDAGInfo::RISCVSelectionDAGInfo() 17*700637cbSDimitry Andric : SelectionDAGGenTargetInfo(RISCVGenSDNodeInfo) {} 18*700637cbSDimitry Andric 19*700637cbSDimitry Andric RISCVSelectionDAGInfo::~RISCVSelectionDAGInfo() = default; 20*700637cbSDimitry Andric verifyTargetNode(const SelectionDAG & DAG,const SDNode * N) const21*700637cbSDimitry Andricvoid RISCVSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG, 22*700637cbSDimitry Andric const SDNode *N) const { 23*700637cbSDimitry Andric #ifndef NDEBUG 24*700637cbSDimitry Andric switch (N->getOpcode()) { 25*700637cbSDimitry Andric default: 26*700637cbSDimitry Andric return SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N); 27*700637cbSDimitry Andric case RISCVISD::VQDOT_VL: 28*700637cbSDimitry Andric case RISCVISD::VQDOTU_VL: 29*700637cbSDimitry Andric case RISCVISD::VQDOTSU_VL: { 30*700637cbSDimitry Andric assert(N->getNumValues() == 1 && "Expected one result!"); 31*700637cbSDimitry Andric assert(N->getNumOperands() == 5 && "Expected five operands!"); 32*700637cbSDimitry Andric EVT VT = N->getValueType(0); 33*700637cbSDimitry Andric assert(VT.isScalableVector() && VT.getVectorElementType() == MVT::i32 && 34*700637cbSDimitry Andric "Expected result to be an i32 scalable vector"); 35*700637cbSDimitry Andric assert(N->getOperand(0).getValueType() == VT && 36*700637cbSDimitry Andric N->getOperand(1).getValueType() == VT && 37*700637cbSDimitry Andric N->getOperand(2).getValueType() == VT && 38*700637cbSDimitry Andric "Expected result and first 3 operands to have the same type!"); 39*700637cbSDimitry Andric EVT MaskVT = N->getOperand(3).getValueType(); 40*700637cbSDimitry Andric assert(MaskVT.isScalableVector() && 41*700637cbSDimitry Andric MaskVT.getVectorElementType() == MVT::i1 && 42*700637cbSDimitry Andric MaskVT.getVectorElementCount() == VT.getVectorElementCount() && 43*700637cbSDimitry Andric "Expected mask VT to be an i1 scalable vector with same number of " 44*700637cbSDimitry Andric "elements as the result"); 45*700637cbSDimitry Andric assert((N->getOperand(4).getValueType() == MVT::i32 || 46*700637cbSDimitry Andric N->getOperand(4).getValueType() == MVT::i64) && 47*700637cbSDimitry Andric "Expect VL operand to be i32 or i64"); 48*700637cbSDimitry Andric break; 49*700637cbSDimitry Andric } 50*700637cbSDimitry Andric } 51*700637cbSDimitry Andric #endif 52*700637cbSDimitry Andric } 53