1//===-- RISCVScheduleV.td - RISCV Scheduling Definitions V -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10/// Define scheduler resources associated with def operands. 11 12// 7. Vector Loads and Stores 13// 7.4. Vector Unit-Stride Instructions 14def WriteVLDE8 : SchedWrite; 15def WriteVLDE16 : SchedWrite; 16def WriteVLDE32 : SchedWrite; 17def WriteVLDE64 : SchedWrite; 18def WriteVSTE8 : SchedWrite; 19def WriteVSTE16 : SchedWrite; 20def WriteVSTE32 : SchedWrite; 21def WriteVSTE64 : SchedWrite; 22// 7.4.1. Vector Unit-Strided Mask 23def WriteVLDM : SchedWrite; 24def WriteVSTM : SchedWrite; 25// 7.5. Vector Strided Instructions 26def WriteVLDS8 : SchedWrite; 27def WriteVLDS16 : SchedWrite; 28def WriteVLDS32 : SchedWrite; 29def WriteVLDS64 : SchedWrite; 30def WriteVSTS8 : SchedWrite; 31def WriteVSTS16 : SchedWrite; 32def WriteVSTS32 : SchedWrite; 33def WriteVSTS64 : SchedWrite; 34// 7.6. Vector Indexed Instructions 35def WriteVLDUX8 : SchedWrite; 36def WriteVLDUX16 : SchedWrite; 37def WriteVLDUX32 : SchedWrite; 38def WriteVLDUX64 : SchedWrite; 39def WriteVLDOX8 : SchedWrite; 40def WriteVLDOX16 : SchedWrite; 41def WriteVLDOX32 : SchedWrite; 42def WriteVLDOX64 : SchedWrite; 43def WriteVSTUX8 : SchedWrite; 44def WriteVSTUX16 : SchedWrite; 45def WriteVSTUX32 : SchedWrite; 46def WriteVSTUX64 : SchedWrite; 47def WriteVSTOX8 : SchedWrite; 48def WriteVSTOX16 : SchedWrite; 49def WriteVSTOX32 : SchedWrite; 50def WriteVSTOX64 : SchedWrite; 51// 7.7. Vector Unit-stride Fault-Only-First Loads 52def WriteVLDFF8 : SchedWrite; 53def WriteVLDFF16 : SchedWrite; 54def WriteVLDFF32 : SchedWrite; 55def WriteVLDFF64 : SchedWrite; 56// 7.8. Vector Segment Instructions 57foreach nf=2-8 in { 58 foreach eew = [8, 16, 32, 64] in { 59 def WriteVLSEG # nf # e # eew : SchedWrite; 60 def WriteVSSEG # nf # e # eew : SchedWrite; 61 def WriteVLSEGFF # nf # e # eew : SchedWrite; 62 def WriteVLSSEG # nf # e # eew : SchedWrite; 63 def WriteVSSSEG # nf # e # eew : SchedWrite; 64 def WriteVLUXSEG # nf # e # eew : SchedWrite; 65 def WriteVLOXSEG # nf # e # eew : SchedWrite; 66 def WriteVSUXSEG # nf # e # eew : SchedWrite; 67 def WriteVSOXSEG # nf # e # eew : SchedWrite; 68 } 69} 70// 7.9. Vector Whole Register Instructions 71def WriteVLD1R8 : SchedWrite; 72def WriteVLD1R16 : SchedWrite; 73def WriteVLD1R32 : SchedWrite; 74def WriteVLD1R64 : SchedWrite; 75def WriteVLD2R8 : SchedWrite; 76def WriteVLD2R16 : SchedWrite; 77def WriteVLD2R32 : SchedWrite; 78def WriteVLD2R64 : SchedWrite; 79def WriteVLD4R8 : SchedWrite; 80def WriteVLD4R16 : SchedWrite; 81def WriteVLD4R32 : SchedWrite; 82def WriteVLD4R64 : SchedWrite; 83def WriteVLD8R8 : SchedWrite; 84def WriteVLD8R16 : SchedWrite; 85def WriteVLD8R32 : SchedWrite; 86def WriteVLD8R64 : SchedWrite; 87def WriteVST1R : SchedWrite; 88def WriteVST2R : SchedWrite; 89def WriteVST4R : SchedWrite; 90def WriteVST8R : SchedWrite; 91 92// 11. Vector Integer Arithmetic Instructions 93// 11.1. Vector Single-Width Integer Add and Subtract 94// 11.5. Vector Bitwise Logical Instructions 95def WriteVIALUV : SchedWrite; 96def WriteVIALUX : SchedWrite; 97def WriteVIALUI : SchedWrite; 98// 11.2. Vector Widening Integer Add/Subtract 99def WriteVIWALUV : SchedWrite; 100def WriteVIWALUX : SchedWrite; 101def WriteVIWALUI : SchedWrite; 102// 11.3. Vector Integer Extension 103def WriteVExtV : SchedWrite; 104// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions 105def WriteVICALUV : SchedWrite; 106def WriteVICALUX : SchedWrite; 107def WriteVICALUI : SchedWrite; 108// 11.6. Vector Single-Width Bit Shift Instructions 109def WriteVShiftV : SchedWrite; 110def WriteVShiftX : SchedWrite; 111def WriteVShiftI : SchedWrite; 112// 11.7. Vector Narrowing Integer Right Shift Instructions 113def WriteVNShiftV : SchedWrite; 114def WriteVNShiftX : SchedWrite; 115def WriteVNShiftI : SchedWrite; 116// 11.8. Vector Integer Comparison Instructions 117// 11.9. Vector Integer Min/Max Instructions 118def WriteVICmpV : SchedWrite; 119def WriteVICmpX : SchedWrite; 120def WriteVICmpI : SchedWrite; 121// 11.10. Vector Single-Width Integer Multiply Instructions 122def WriteVIMulV : SchedWrite; 123def WriteVIMulX : SchedWrite; 124// 11.11. Vector Integer Divide Instructions 125def WriteVIDivV : SchedWrite; 126def WriteVIDivX : SchedWrite; 127// 11.12. Vector Widening Integer Multiply Instructions 128def WriteVIWMulV : SchedWrite; 129def WriteVIWMulX : SchedWrite; 130// 11.13. Vector Single-Width Integer Multiply-Add Instructions 131def WriteVIMulAddV : SchedWrite; 132def WriteVIMulAddX : SchedWrite; 133// 11.14. Vector Widening Integer Multiply-Add Instructions 134def WriteVIWMulAddV : SchedWrite; 135def WriteVIWMulAddX : SchedWrite; 136// 11.15. Vector Integer Merge Instructions 137def WriteVIMergeV : SchedWrite; 138def WriteVIMergeX : SchedWrite; 139def WriteVIMergeI : SchedWrite; 140// 11.16. Vector Integer Move Instructions 141def WriteVIMovV : SchedWrite; 142def WriteVIMovX : SchedWrite; 143def WriteVIMovI : SchedWrite; 144 145// 12. Vector Fixed-Point Arithmetic Instructions 146// 12.1. Vector Single-Width Saturating Add and Subtract 147def WriteVSALUV : SchedWrite; 148def WriteVSALUX : SchedWrite; 149def WriteVSALUI : SchedWrite; 150// 12.2. Vector Single-Width Averaging Add and Subtract 151def WriteVAALUV : SchedWrite; 152def WriteVAALUX : SchedWrite; 153// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 154def WriteVSMulV : SchedWrite; 155def WriteVSMulX : SchedWrite; 156// 12.4. Vector Single-Width Scaling Shift Instructions 157def WriteVSShiftV : SchedWrite; 158def WriteVSShiftX : SchedWrite; 159def WriteVSShiftI : SchedWrite; 160// 12.5. Vector Narrowing Fixed-Point Clip Instructions 161def WriteVNClipV : SchedWrite; 162def WriteVNClipX : SchedWrite; 163def WriteVNClipI : SchedWrite; 164 165// 13. Vector Floating-Point Instructions 166// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 167def WriteVFALUV : SchedWrite; 168def WriteVFALUF : SchedWrite; 169// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 170def WriteVFWALUV : SchedWrite; 171def WriteVFWALUF : SchedWrite; 172// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 173def WriteVFMulV : SchedWrite; 174def WriteVFMulF : SchedWrite; 175def WriteVFDivV : SchedWrite; 176def WriteVFDivF : SchedWrite; 177// 13.5. Vector Widening Floating-Point Multiply 178def WriteVFWMulV : SchedWrite; 179def WriteVFWMulF : SchedWrite; 180// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 181def WriteVFMulAddV : SchedWrite; 182def WriteVFMulAddF : SchedWrite; 183// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 184def WriteVFWMulAddV : SchedWrite; 185def WriteVFWMulAddF : SchedWrite; 186// 13.8. Vector Floating-Point Square-Root Instruction 187def WriteVFSqrtV : SchedWrite; 188// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 189// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 190def WriteVFRecpV : SchedWrite; 191// 13.11. Vector Floating-Point MIN/MAX Instructions 192// 13.13. Vector Floating-Point Compare Instructions 193def WriteVFCmpV : SchedWrite; 194def WriteVFCmpF : SchedWrite; 195// 13.12. Vector Floating-Point Sign-Injection Instructions 196def WriteVFSgnjV : SchedWrite; 197def WriteVFSgnjF : SchedWrite; 198// 13.14. Vector Floating-Point Classify Instruction 199def WriteVFClassV : SchedWrite; 200// 13.15. Vector Floating-Point Merge Instruction 201def WriteVFMergeV : SchedWrite; 202// 13.16. Vector Floating-Point Move Instruction 203def WriteVFMovV : SchedWrite; 204// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 205def WriteVFCvtIToFV : SchedWrite; 206def WriteVFCvtFToIV : SchedWrite; 207def WriteVFCvtFToFV : SchedWrite; 208// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 209def WriteVFWCvtIToFV : SchedWrite; 210def WriteVFWCvtFToIV : SchedWrite; 211def WriteVFWCvtFToFV : SchedWrite; 212// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 213def WriteVFNCvtIToFV : SchedWrite; 214def WriteVFNCvtFToIV : SchedWrite; 215def WriteVFNCvtFToFV : SchedWrite; 216 217// 14. Vector Reduction Operations 218// 14.1. Vector Single-Width Integer Reduction Instructions 219def WriteVIRedV : SchedWrite; 220// 14.2. Vector Widening Integer Reduction Instructions 221def WriteVIWRedV : SchedWrite; 222// 14.3. Vector Single-Width Floating-Point Reduction Instructions 223def WriteVFRedV : SchedWrite; 224def WriteVFRedOV : SchedWrite; 225// 14.4. Vector Widening Floating-Point Reduction Instructions 226def WriteVFWRedV : SchedWrite; 227def WriteVFWRedOV : SchedWrite; 228 229// 15. Vector Mask Instructions 230// 15.1. Vector Mask-Register Logical Instructions 231def WriteVMALUV : SchedWrite; 232// 15.2. Vector Mask Population Count 233def WriteVMPopV : SchedWrite; 234// 15.3. Vector Find-First-Set Mask Bit 235def WriteVMFFSV : SchedWrite; 236// 15.4. Vector Set-Before-First Mask Bit 237// 15.5. Vector Set-Including-First Mask Bit 238// 15.6. Vector Set-only-First Mask Bit 239def WriteVMSFSV : SchedWrite; 240// 15.8. Vector Iota Instruction 241def WriteVMIotV : SchedWrite; 242// 15.9. Vector Element Index Instruction 243def WriteVMIdxV : SchedWrite; 244 245// 16. Vector Permutation Instructions 246// 16.1. Integer Scalar Move Instructions 247def WriteVIMovVX : SchedWrite; 248def WriteVIMovXV : SchedWrite; 249// 16.2. Floating-Point Scalar Move Instructions 250def WriteVFMovVF : SchedWrite; 251def WriteVFMovFV : SchedWrite; 252// 16.3. Vector Slide Instructions 253def WriteVISlideX : SchedWrite; 254def WriteVISlideI : SchedWrite; 255def WriteVISlide1X : SchedWrite; 256def WriteVFSlide1F : SchedWrite; 257// 16.4. Vector Register Gather Instructions 258def WriteVGatherV : SchedWrite; 259def WriteVGatherX : SchedWrite; 260def WriteVGatherI : SchedWrite; 261// 16.5. Vector Compress Instruction 262def WriteVCompressV : SchedWrite; 263// 16.6. Whole Vector Register Move 264def WriteVMov1V : SchedWrite; 265def WriteVMov2V : SchedWrite; 266def WriteVMov4V : SchedWrite; 267def WriteVMov8V : SchedWrite; 268 269//===----------------------------------------------------------------------===// 270/// Define scheduler resources associated with use operands. 271 272// 7. Vector Loads and Stores 273def ReadVLDX : SchedRead; 274def ReadVSTX : SchedRead; 275// 7.4. Vector Unit-Stride Instructions 276def ReadVSTE8V : SchedRead; 277def ReadVSTE16V : SchedRead; 278def ReadVSTE32V : SchedRead; 279def ReadVSTE64V : SchedRead; 280// 7.4.1. Vector Unit-Strided Mask 281def ReadVSTM : SchedRead; 282// 7.5. Vector Strided Instructions 283def ReadVLDSX : SchedRead; 284def ReadVSTSX : SchedRead; 285def ReadVSTS8V : SchedRead; 286def ReadVSTS16V : SchedRead; 287def ReadVSTS32V : SchedRead; 288def ReadVSTS64V : SchedRead; 289// 7.6. Vector Indexed Instructions 290def ReadVLDUXV : SchedRead; 291def ReadVLDOXV : SchedRead; 292def ReadVSTUX8 : SchedRead; 293def ReadVSTUX16 : SchedRead; 294def ReadVSTUX32 : SchedRead; 295def ReadVSTUX64 : SchedRead; 296def ReadVSTUXV : SchedRead; 297def ReadVSTUX8V : SchedRead; 298def ReadVSTUX16V : SchedRead; 299def ReadVSTUX32V : SchedRead; 300def ReadVSTUX64V : SchedRead; 301def ReadVSTOX8 : SchedRead; 302def ReadVSTOX16 : SchedRead; 303def ReadVSTOX32 : SchedRead; 304def ReadVSTOX64 : SchedRead; 305def ReadVSTOXV : SchedRead; 306def ReadVSTOX8V : SchedRead; 307def ReadVSTOX16V : SchedRead; 308def ReadVSTOX32V : SchedRead; 309def ReadVSTOX64V : SchedRead; 310// 7.9. Vector Whole Register Instructions 311def ReadVST1R : SchedRead; 312def ReadVST2R : SchedRead; 313def ReadVST4R : SchedRead; 314def ReadVST8R : SchedRead; 315 316// 11. Vector Integer Arithmetic Instructions 317// 11.1. Vector Single-Width Integer Add and Subtract 318// 11.5. Vector Bitwise Logical Instructions 319def ReadVIALUV : SchedRead; 320def ReadVIALUX : SchedRead; 321// 11.2. Vector Widening Integer Add/Subtract 322def ReadVIWALUV : SchedRead; 323def ReadVIWALUX : SchedRead; 324// 11.3. Vector Integer Extension 325def ReadVExtV : SchedRead; 326// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions 327def ReadVIALUCV : SchedRead; 328def ReadVIALUCX : SchedRead; 329// 11.6. Vector Single-Width Bit Shift Instructions 330def ReadVShiftV : SchedRead; 331def ReadVShiftX : SchedRead; 332// 11.7. Vector Narrowing Integer Right Shift Instructions 333def ReadVNShiftV : SchedRead; 334def ReadVNShiftX : SchedRead; 335// 11.8. Vector Integer Comparison Instructions 336// 11.9. Vector Integer Min/Max Instructions 337def ReadVICmpV : SchedRead; 338def ReadVICmpX : SchedRead; 339// 11.10. Vector Single-Width Integer Multiply Instructions 340def ReadVIMulV : SchedRead; 341def ReadVIMulX : SchedRead; 342// 11.11. Vector Integer Divide Instructions 343def ReadVIDivV : SchedRead; 344def ReadVIDivX : SchedRead; 345// 11.12. Vector Widening Integer Multiply Instructions 346def ReadVIWMulV : SchedRead; 347def ReadVIWMulX : SchedRead; 348// 11.13. Vector Single-Width Integer Multiply-Add Instructions 349def ReadVIMulAddV : SchedRead; 350def ReadVIMulAddX : SchedRead; 351// 11.14. Vector Widening Integer Multiply-Add Instructions 352def ReadVIWMulAddV : SchedRead; 353def ReadVIWMulAddX : SchedRead; 354// 11.15. Vector Integer Merge Instructions 355def ReadVIMergeV : SchedRead; 356def ReadVIMergeX : SchedRead; 357// 11.16. Vector Integer Move Instructions 358def ReadVIMovV : SchedRead; 359def ReadVIMovX : SchedRead; 360 361// 12. Vector Fixed-Point Arithmetic Instructions 362// 12.1. Vector Single-Width Saturating Add and Subtract 363def ReadVSALUV : SchedRead; 364def ReadVSALUX : SchedRead; 365// 12.2. Vector Single-Width Averaging Add and Subtract 366def ReadVAALUV : SchedRead; 367def ReadVAALUX : SchedRead; 368// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 369def ReadVSMulV : SchedRead; 370def ReadVSMulX : SchedRead; 371// 12.4. Vector Single-Width Scaling Shift Instructions 372def ReadVSShiftV : SchedRead; 373def ReadVSShiftX : SchedRead; 374// 12.5. Vector Narrowing Fixed-Point Clip Instructions 375def ReadVNClipV : SchedRead; 376def ReadVNClipX : SchedRead; 377 378// 13. Vector Floating-Point Instructions 379// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 380def ReadVFALUV : SchedRead; 381def ReadVFALUF : SchedRead; 382// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 383def ReadVFWALUV : SchedRead; 384def ReadVFWALUF : SchedRead; 385// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 386def ReadVFMulV : SchedRead; 387def ReadVFMulF : SchedRead; 388def ReadVFDivV : SchedRead; 389def ReadVFDivF : SchedRead; 390// 13.5. Vector Widening Floating-Point Multiply 391def ReadVFWMulV : SchedRead; 392def ReadVFWMulF : SchedRead; 393// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 394def ReadVFMulAddV : SchedRead; 395def ReadVFMulAddF : SchedRead; 396// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 397def ReadVFWMulAddV : SchedRead; 398def ReadVFWMulAddF : SchedRead; 399// 13.8. Vector Floating-Point Square-Root Instruction 400def ReadVFSqrtV : SchedRead; 401// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 402// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 403def ReadVFRecpV : SchedRead; 404// 13.11. Vector Floating-Point MIN/MAX Instructions 405// 13.13. Vector Floating-Point Compare Instructions 406def ReadVFCmpV : SchedRead; 407def ReadVFCmpF : SchedRead; 408// 13.12. Vector Floating-Point Sign-Injection Instructions 409def ReadVFSgnjV : SchedRead; 410def ReadVFSgnjF : SchedRead; 411// 13.14. Vector Floating-Point Classify Instruction 412def ReadVFClassV : SchedRead; 413// 13.15. Vector Floating-Point Merge Instruction 414def ReadVFMergeV : SchedRead; 415def ReadVFMergeF : SchedRead; 416// 13.16. Vector Floating-Point Move Instruction 417def ReadVFMovF : SchedRead; 418// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 419def ReadVFCvtIToFV : SchedRead; 420def ReadVFCvtFToIV : SchedRead; 421// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 422def ReadVFWCvtIToFV : SchedRead; 423def ReadVFWCvtFToIV : SchedRead; 424def ReadVFWCvtFToFV : SchedRead; 425// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 426def ReadVFNCvtIToFV : SchedRead; 427def ReadVFNCvtFToIV : SchedRead; 428def ReadVFNCvtFToFV : SchedRead; 429 430// 14. Vector Reduction Operations 431// 14.1. Vector Single-Width Integer Reduction Instructions 432def ReadVIRedV : SchedRead; 433def ReadVIRedV0 : SchedRead; 434// 14.2. Vector Widening Integer Reduction Instructions 435def ReadVIWRedV : SchedRead; 436def ReadVIWRedV0 : SchedRead; 437// 14.3. Vector Single-Width Floating-Point Reduction Instructions 438def ReadVFRedV : SchedRead; 439def ReadVFRedV0 : SchedRead; 440def ReadVFRedOV : SchedRead; 441def ReadVFRedOV0 : SchedRead; 442// 14.4. Vector Widening Floating-Point Reduction Instructions 443def ReadVFWRedV : SchedRead; 444def ReadVFWRedV0 : SchedRead; 445def ReadVFWRedOV : SchedRead; 446def ReadVFWRedOV0 : SchedRead; 447 448// 15. Vector Mask Instructions 449// 15.1. Vector Mask-Register Logical Instructions 450def ReadVMALUV : SchedRead; 451// 15.2. Vector Mask Population Count 452def ReadVMPopV : SchedRead; 453// 15.3. Vector Find-First-Set Mask Bit 454def ReadVMFFSV : SchedRead; 455// 15.4. Vector Set-Before-First Mask Bit 456// 15.5. Vector Set-Including-First Mask Bit 457// 15.6. Vector Set-only-First Mask Bit 458def ReadVMSFSV : SchedRead; 459// 15.8. Vector Iota Instruction 460def ReadVMIotV : SchedRead; 461 462// 16. Vector Permutation Instructions 463// 16.1. Integer Scalar Move Instructions 464def ReadVIMovVX : SchedRead; 465def ReadVIMovXV : SchedRead; 466def ReadVIMovXX : SchedRead; 467// 16.2. Floating-Point Scalar Move Instructions 468def ReadVFMovVF : SchedRead; 469def ReadVFMovFV : SchedRead; 470def ReadVFMovFX : SchedRead; 471// 16.3. Vector Slide Instructions 472def ReadVISlideV : SchedRead; 473def ReadVISlideX : SchedRead; 474def ReadVFSlideV : SchedRead; 475def ReadVFSlideF : SchedRead; 476// 16.4. Vector Register Gather Instructions 477def ReadVGatherV : SchedRead; 478def ReadVGatherX : SchedRead; 479// 16.5. Vector Compress Instruction 480def ReadVCompressV : SchedRead; 481// 16.6. Whole Vector Register Move 482def ReadVMov1V : SchedRead; 483def ReadVMov2V : SchedRead; 484def ReadVMov4V : SchedRead; 485def ReadVMov8V : SchedRead; 486 487// Others 488def ReadVMask : SchedRead; 489 490//===----------------------------------------------------------------------===// 491/// Define default scheduler resources for V. 492 493multiclass UnsupportedSchedV { 494let Unsupported = true in { 495 496// 7. Vector Loads and Stores 497def : WriteRes<WriteVLDE8, []>; 498def : WriteRes<WriteVLDE16, []>; 499def : WriteRes<WriteVLDE32, []>; 500def : WriteRes<WriteVLDE64, []>; 501def : WriteRes<WriteVSTE8, []>; 502def : WriteRes<WriteVSTE16, []>; 503def : WriteRes<WriteVSTE32, []>; 504def : WriteRes<WriteVSTE64, []>; 505def : WriteRes<WriteVLDM, []>; 506def : WriteRes<WriteVSTM, []>; 507def : WriteRes<WriteVLDS8, []>; 508def : WriteRes<WriteVLDS16, []>; 509def : WriteRes<WriteVLDS32, []>; 510def : WriteRes<WriteVLDS64, []>; 511def : WriteRes<WriteVSTS8, []>; 512def : WriteRes<WriteVSTS16, []>; 513def : WriteRes<WriteVSTS32, []>; 514def : WriteRes<WriteVSTS64, []>; 515def : WriteRes<WriteVLDUX8, []>; 516def : WriteRes<WriteVLDUX16, []>; 517def : WriteRes<WriteVLDUX32, []>; 518def : WriteRes<WriteVLDUX64, []>; 519def : WriteRes<WriteVLDOX8, []>; 520def : WriteRes<WriteVLDOX16, []>; 521def : WriteRes<WriteVLDOX32, []>; 522def : WriteRes<WriteVLDOX64, []>; 523def : WriteRes<WriteVSTUX8, []>; 524def : WriteRes<WriteVSTUX16, []>; 525def : WriteRes<WriteVSTUX32, []>; 526def : WriteRes<WriteVSTUX64, []>; 527def : WriteRes<WriteVSTOX8, []>; 528def : WriteRes<WriteVSTOX16, []>; 529def : WriteRes<WriteVSTOX32, []>; 530def : WriteRes<WriteVSTOX64, []>; 531def : WriteRes<WriteVLDFF8, []>; 532def : WriteRes<WriteVLDFF16, []>; 533def : WriteRes<WriteVLDFF32, []>; 534def : WriteRes<WriteVLDFF64, []>; 535def : WriteRes<WriteVLD1R8, []>; 536def : WriteRes<WriteVLD1R16, []>; 537def : WriteRes<WriteVLD1R32, []>; 538def : WriteRes<WriteVLD1R64, []>; 539def : WriteRes<WriteVLD2R8, []>; 540def : WriteRes<WriteVLD2R16, []>; 541def : WriteRes<WriteVLD2R32, []>; 542def : WriteRes<WriteVLD2R64, []>; 543def : WriteRes<WriteVLD4R8, []>; 544def : WriteRes<WriteVLD4R16, []>; 545def : WriteRes<WriteVLD4R32, []>; 546def : WriteRes<WriteVLD4R64, []>; 547def : WriteRes<WriteVLD8R8, []>; 548def : WriteRes<WriteVLD8R16, []>; 549def : WriteRes<WriteVLD8R32, []>; 550def : WriteRes<WriteVLD8R64, []>; 551def : WriteRes<WriteVST1R, []>; 552def : WriteRes<WriteVST2R, []>; 553def : WriteRes<WriteVST4R, []>; 554def : WriteRes<WriteVST8R, []>; 555// Vector Segment Loads and Stores 556foreach nf=2-8 in { 557 foreach eew = [8, 16, 32, 64] in { 558 def : WriteRes <!cast<SchedWrite>("WriteVLSEG" # nf # "e" # eew), []>; 559 def : WriteRes <!cast<SchedWrite>("WriteVLSEGFF" # nf # "e" # eew), []>; 560 def : WriteRes <!cast<SchedWrite>("WriteVSSEG" # nf # "e" # eew), []>; 561 def : WriteRes <!cast<SchedWrite>("WriteVLSSEG" # nf # "e" # eew), []>; 562 def : WriteRes <!cast<SchedWrite>("WriteVSSSEG" # nf # "e" # eew), []>; 563 def : WriteRes <!cast<SchedWrite>("WriteVLUXSEG" # nf # "e" # eew), []>; 564 def : WriteRes <!cast<SchedWrite>("WriteVLOXSEG" # nf # "e" # eew), []>; 565 def : WriteRes <!cast<SchedWrite>("WriteVSUXSEG" # nf # "e" # eew), []>; 566 def : WriteRes <!cast<SchedWrite>("WriteVSOXSEG" # nf # "e" # eew), []>; 567 } 568} 569 570// 12. Vector Integer Arithmetic Instructions 571def : WriteRes<WriteVIALUV, []>; 572def : WriteRes<WriteVIALUX, []>; 573def : WriteRes<WriteVIALUI, []>; 574def : WriteRes<WriteVIWALUV, []>; 575def : WriteRes<WriteVIWALUX, []>; 576def : WriteRes<WriteVIWALUI, []>; 577def : WriteRes<WriteVExtV, []>; 578def : WriteRes<WriteVICALUV, []>; 579def : WriteRes<WriteVICALUX, []>; 580def : WriteRes<WriteVICALUI, []>; 581def : WriteRes<WriteVShiftV, []>; 582def : WriteRes<WriteVShiftX, []>; 583def : WriteRes<WriteVShiftI, []>; 584def : WriteRes<WriteVNShiftV, []>; 585def : WriteRes<WriteVNShiftX, []>; 586def : WriteRes<WriteVNShiftI, []>; 587def : WriteRes<WriteVICmpV, []>; 588def : WriteRes<WriteVICmpX, []>; 589def : WriteRes<WriteVICmpI, []>; 590def : WriteRes<WriteVIMulV, []>; 591def : WriteRes<WriteVIMulX, []>; 592def : WriteRes<WriteVIDivV, []>; 593def : WriteRes<WriteVIDivX, []>; 594def : WriteRes<WriteVIWMulV, []>; 595def : WriteRes<WriteVIWMulX, []>; 596def : WriteRes<WriteVIMulAddV, []>; 597def : WriteRes<WriteVIMulAddX, []>; 598def : WriteRes<WriteVIWMulAddV, []>; 599def : WriteRes<WriteVIWMulAddX, []>; 600def : WriteRes<WriteVIMergeV, []>; 601def : WriteRes<WriteVIMergeX, []>; 602def : WriteRes<WriteVIMergeI, []>; 603def : WriteRes<WriteVIMovV, []>; 604def : WriteRes<WriteVIMovX, []>; 605def : WriteRes<WriteVIMovI, []>; 606 607// 13. Vector Fixed-Point Arithmetic Instructions 608def : WriteRes<WriteVSALUV, []>; 609def : WriteRes<WriteVSALUX, []>; 610def : WriteRes<WriteVSALUI, []>; 611def : WriteRes<WriteVAALUV, []>; 612def : WriteRes<WriteVAALUX, []>; 613def : WriteRes<WriteVSMulV, []>; 614def : WriteRes<WriteVSMulX, []>; 615def : WriteRes<WriteVSShiftV, []>; 616def : WriteRes<WriteVSShiftX, []>; 617def : WriteRes<WriteVSShiftI, []>; 618def : WriteRes<WriteVNClipV, []>; 619def : WriteRes<WriteVNClipX, []>; 620def : WriteRes<WriteVNClipI, []>; 621 622// 14. Vector Floating-Point Instructions 623def : WriteRes<WriteVFALUV, []>; 624def : WriteRes<WriteVFALUF, []>; 625def : WriteRes<WriteVFWALUV, []>; 626def : WriteRes<WriteVFWALUF, []>; 627def : WriteRes<WriteVFMulV, []>; 628def : WriteRes<WriteVFMulF, []>; 629def : WriteRes<WriteVFDivV, []>; 630def : WriteRes<WriteVFDivF, []>; 631def : WriteRes<WriteVFWMulV, []>; 632def : WriteRes<WriteVFWMulF, []>; 633def : WriteRes<WriteVFMulAddV, []>; 634def : WriteRes<WriteVFMulAddF, []>; 635def : WriteRes<WriteVFWMulAddV, []>; 636def : WriteRes<WriteVFWMulAddF, []>; 637def : WriteRes<WriteVFSqrtV, []>; 638def : WriteRes<WriteVFRecpV, []>; 639def : WriteRes<WriteVFCmpV, []>; 640def : WriteRes<WriteVFCmpF, []>; 641def : WriteRes<WriteVFSgnjV, []>; 642def : WriteRes<WriteVFSgnjF, []>; 643def : WriteRes<WriteVFClassV, []>; 644def : WriteRes<WriteVFMergeV, []>; 645def : WriteRes<WriteVFMovV, []>; 646def : WriteRes<WriteVFCvtIToFV, []>; 647def : WriteRes<WriteVFCvtFToIV, []>; 648def : WriteRes<WriteVFCvtFToFV, []>; 649def : WriteRes<WriteVFWCvtIToFV, []>; 650def : WriteRes<WriteVFWCvtFToIV, []>; 651def : WriteRes<WriteVFWCvtFToFV, []>; 652def : WriteRes<WriteVFNCvtIToFV, []>; 653def : WriteRes<WriteVFNCvtFToIV, []>; 654def : WriteRes<WriteVFNCvtFToFV, []>; 655 656// 15. Vector Reduction Operations 657def : WriteRes<WriteVIRedV, []>; 658def : WriteRes<WriteVIWRedV, []>; 659def : WriteRes<WriteVFRedV, []>; 660def : WriteRes<WriteVFRedOV, []>; 661def : WriteRes<WriteVFWRedV, []>; 662def : WriteRes<WriteVFWRedOV, []>; 663 664// 16. Vector Mask Instructions 665def : WriteRes<WriteVMALUV, []>; 666def : WriteRes<WriteVMPopV, []>; 667def : WriteRes<WriteVMFFSV, []>; 668def : WriteRes<WriteVMSFSV, []>; 669def : WriteRes<WriteVMIotV, []>; 670def : WriteRes<WriteVMIdxV, []>; 671 672// 17. Vector Permutation Instructions 673def : WriteRes<WriteVIMovVX, []>; 674def : WriteRes<WriteVIMovXV, []>; 675def : WriteRes<WriteVFMovVF, []>; 676def : WriteRes<WriteVFMovFV, []>; 677def : WriteRes<WriteVISlideX, []>; 678def : WriteRes<WriteVISlideI, []>; 679def : WriteRes<WriteVISlide1X, []>; 680def : WriteRes<WriteVFSlide1F, []>; 681def : WriteRes<WriteVGatherV, []>; 682def : WriteRes<WriteVGatherX, []>; 683def : WriteRes<WriteVGatherI, []>; 684def : WriteRes<WriteVCompressV, []>; 685def : WriteRes<WriteVMov1V, []>; 686def : WriteRes<WriteVMov2V, []>; 687def : WriteRes<WriteVMov4V, []>; 688def : WriteRes<WriteVMov8V, []>; 689 690// 7. Vector Loads and Stores 691def : ReadAdvance<ReadVLDX, 0>; 692def : ReadAdvance<ReadVSTX, 0>; 693def : ReadAdvance<ReadVSTE8V, 0>; 694def : ReadAdvance<ReadVSTE16V, 0>; 695def : ReadAdvance<ReadVSTE32V, 0>; 696def : ReadAdvance<ReadVSTE64V, 0>; 697def : ReadAdvance<ReadVSTM, 0>; 698def : ReadAdvance<ReadVLDSX, 0>; 699def : ReadAdvance<ReadVSTSX, 0>; 700def : ReadAdvance<ReadVSTS8V, 0>; 701def : ReadAdvance<ReadVSTS16V, 0>; 702def : ReadAdvance<ReadVSTS32V, 0>; 703def : ReadAdvance<ReadVSTS64V, 0>; 704def : ReadAdvance<ReadVLDUXV, 0>; 705def : ReadAdvance<ReadVLDOXV, 0>; 706def : ReadAdvance<ReadVSTUXV, 0>; 707def : ReadAdvance<ReadVSTUX8, 0>; 708def : ReadAdvance<ReadVSTUX16, 0>; 709def : ReadAdvance<ReadVSTUX32, 0>; 710def : ReadAdvance<ReadVSTUX64, 0>; 711def : ReadAdvance<ReadVSTUX8V, 0>; 712def : ReadAdvance<ReadVSTUX16V, 0>; 713def : ReadAdvance<ReadVSTUX32V, 0>; 714def : ReadAdvance<ReadVSTUX64V, 0>; 715def : ReadAdvance<ReadVSTOX8, 0>; 716def : ReadAdvance<ReadVSTOX16, 0>; 717def : ReadAdvance<ReadVSTOX32, 0>; 718def : ReadAdvance<ReadVSTOX64, 0>; 719def : ReadAdvance<ReadVSTOXV, 0>; 720def : ReadAdvance<ReadVSTOX8V, 0>; 721def : ReadAdvance<ReadVSTOX16V, 0>; 722def : ReadAdvance<ReadVSTOX32V, 0>; 723def : ReadAdvance<ReadVSTOX64V, 0>; 724def : ReadAdvance<ReadVST1R, 0>; 725def : ReadAdvance<ReadVST2R, 0>; 726def : ReadAdvance<ReadVST4R, 0>; 727def : ReadAdvance<ReadVST8R, 0>; 728 729// 12. Vector Integer Arithmetic Instructions 730def : ReadAdvance<ReadVIALUV, 0>; 731def : ReadAdvance<ReadVIALUX, 0>; 732def : ReadAdvance<ReadVIWALUV, 0>; 733def : ReadAdvance<ReadVIWALUX, 0>; 734def : ReadAdvance<ReadVExtV, 0>; 735def : ReadAdvance<ReadVIALUCV, 0>; 736def : ReadAdvance<ReadVIALUCX, 0>; 737def : ReadAdvance<ReadVShiftV, 0>; 738def : ReadAdvance<ReadVShiftX, 0>; 739def : ReadAdvance<ReadVNShiftV, 0>; 740def : ReadAdvance<ReadVNShiftX, 0>; 741def : ReadAdvance<ReadVICmpV, 0>; 742def : ReadAdvance<ReadVICmpX, 0>; 743def : ReadAdvance<ReadVIMulV, 0>; 744def : ReadAdvance<ReadVIMulX, 0>; 745def : ReadAdvance<ReadVIDivV, 0>; 746def : ReadAdvance<ReadVIDivX, 0>; 747def : ReadAdvance<ReadVIWMulV, 0>; 748def : ReadAdvance<ReadVIWMulX, 0>; 749def : ReadAdvance<ReadVIMulAddV, 0>; 750def : ReadAdvance<ReadVIMulAddX, 0>; 751def : ReadAdvance<ReadVIWMulAddV, 0>; 752def : ReadAdvance<ReadVIWMulAddX, 0>; 753def : ReadAdvance<ReadVIMergeV, 0>; 754def : ReadAdvance<ReadVIMergeX, 0>; 755def : ReadAdvance<ReadVIMovV, 0>; 756def : ReadAdvance<ReadVIMovX, 0>; 757 758// 13. Vector Fixed-Point Arithmetic Instructions 759def : ReadAdvance<ReadVSALUV, 0>; 760def : ReadAdvance<ReadVSALUX, 0>; 761def : ReadAdvance<ReadVAALUV, 0>; 762def : ReadAdvance<ReadVAALUX, 0>; 763def : ReadAdvance<ReadVSMulV, 0>; 764def : ReadAdvance<ReadVSMulX, 0>; 765def : ReadAdvance<ReadVSShiftV, 0>; 766def : ReadAdvance<ReadVSShiftX, 0>; 767def : ReadAdvance<ReadVNClipV, 0>; 768def : ReadAdvance<ReadVNClipX, 0>; 769 770// 14. Vector Floating-Point Instructions 771def : ReadAdvance<ReadVFALUV, 0>; 772def : ReadAdvance<ReadVFALUF, 0>; 773def : ReadAdvance<ReadVFWALUV, 0>; 774def : ReadAdvance<ReadVFWALUF, 0>; 775def : ReadAdvance<ReadVFMulV, 0>; 776def : ReadAdvance<ReadVFMulF, 0>; 777def : ReadAdvance<ReadVFDivV, 0>; 778def : ReadAdvance<ReadVFDivF, 0>; 779def : ReadAdvance<ReadVFWMulV, 0>; 780def : ReadAdvance<ReadVFWMulF, 0>; 781def : ReadAdvance<ReadVFMulAddV, 0>; 782def : ReadAdvance<ReadVFMulAddF, 0>; 783def : ReadAdvance<ReadVFWMulAddV, 0>; 784def : ReadAdvance<ReadVFWMulAddF, 0>; 785def : ReadAdvance<ReadVFSqrtV, 0>; 786def : ReadAdvance<ReadVFRecpV, 0>; 787def : ReadAdvance<ReadVFCmpV, 0>; 788def : ReadAdvance<ReadVFCmpF, 0>; 789def : ReadAdvance<ReadVFSgnjV, 0>; 790def : ReadAdvance<ReadVFSgnjF, 0>; 791def : ReadAdvance<ReadVFClassV, 0>; 792def : ReadAdvance<ReadVFMergeV, 0>; 793def : ReadAdvance<ReadVFMergeF, 0>; 794def : ReadAdvance<ReadVFMovF, 0>; 795def : ReadAdvance<ReadVFCvtIToFV, 0>; 796def : ReadAdvance<ReadVFCvtFToIV, 0>; 797def : ReadAdvance<ReadVFWCvtIToFV, 0>; 798def : ReadAdvance<ReadVFWCvtFToIV, 0>; 799def : ReadAdvance<ReadVFWCvtFToFV, 0>; 800def : ReadAdvance<ReadVFNCvtIToFV, 0>; 801def : ReadAdvance<ReadVFNCvtFToIV, 0>; 802def : ReadAdvance<ReadVFNCvtFToFV, 0>; 803 804// 15. Vector Reduction Operations 805def : ReadAdvance<ReadVIRedV, 0>; 806def : ReadAdvance<ReadVIRedV0, 0>; 807def : ReadAdvance<ReadVIWRedV, 0>; 808def : ReadAdvance<ReadVIWRedV0, 0>; 809def : ReadAdvance<ReadVFRedV, 0>; 810def : ReadAdvance<ReadVFRedV0, 0>; 811def : ReadAdvance<ReadVFRedOV, 0>; 812def : ReadAdvance<ReadVFRedOV0, 0>; 813def : ReadAdvance<ReadVFWRedV, 0>; 814def : ReadAdvance<ReadVFWRedV0, 0>; 815def : ReadAdvance<ReadVFWRedOV, 0>; 816def : ReadAdvance<ReadVFWRedOV0, 0>; 817 818// 16. Vector Mask Instructions 819def : ReadAdvance<ReadVMALUV, 0>; 820def : ReadAdvance<ReadVMPopV, 0>; 821def : ReadAdvance<ReadVMFFSV, 0>; 822def : ReadAdvance<ReadVMSFSV, 0>; 823def : ReadAdvance<ReadVMIotV, 0>; 824 825// 17. Vector Permutation Instructions 826def : ReadAdvance<ReadVIMovVX, 0>; 827def : ReadAdvance<ReadVIMovXV, 0>; 828def : ReadAdvance<ReadVIMovXX, 0>; 829def : ReadAdvance<ReadVFMovVF, 0>; 830def : ReadAdvance<ReadVFMovFV, 0>; 831def : ReadAdvance<ReadVFMovFX, 0>; 832def : ReadAdvance<ReadVISlideV, 0>; 833def : ReadAdvance<ReadVISlideX, 0>; 834def : ReadAdvance<ReadVFSlideV, 0>; 835def : ReadAdvance<ReadVFSlideF, 0>; 836def : ReadAdvance<ReadVGatherV, 0>; 837def : ReadAdvance<ReadVGatherX, 0>; 838def : ReadAdvance<ReadVCompressV, 0>; 839def : ReadAdvance<ReadVMov1V, 0>; 840def : ReadAdvance<ReadVMov2V, 0>; 841def : ReadAdvance<ReadVMov4V, 0>; 842def : ReadAdvance<ReadVMov8V, 0>; 843 844// Others 845def : ReadAdvance<ReadVMask, 0>; 846 847} // Unsupported 848} // UnsupportedSchedV 849