1//===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10/// Define scheduler resources associated with def operands. 11 12defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"]; 13// Used for widening and narrowing instructions as it doesn't contain M8. 14defvar SchedMxListW = !listremove(SchedMxList, ["M8"]); 15// Used for widening reductions, which does contain M8. 16defvar SchedMxListWRed = SchedMxList; 17defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]); 18// Used for floating-point as it doesn't contain MF8. 19defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]); 20// Used for widening floating-point Reduction as it doesn't contain MF8. 21defvar SchedMxListFWRed = SchedMxListF; 22 23class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> { 24 assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point"; 25 defvar t = !cond(!eq(mx, "M1"): [8, 16, 32, 64], 26 !eq(mx, "M2"): [8, 16, 32, 64], 27 !eq(mx, "M4"): [8, 16, 32, 64], 28 !eq(mx, "M8"): [8, 16, 32, 64], 29 !eq(mx, "MF2"): [8, 16, 32], 30 !eq(mx, "MF4"): [8, 16], 31 !eq(mx, "MF8"): [8]); 32 // For floating-point instructions, SEW won't be 8. 33 defvar remove8 = !if(isF, !listremove(t, [8]), t); 34 // For widening instructions, SEW will not be 64. 35 defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8); 36 list<int> val = remove64; 37} 38 39// Helper function to get the largest LMUL from MxList 40// Precondition: MxList is sorted in ascending LMUL order. 41class LargestLMUL<list<string> MxList> { 42 // MX list is sorted from smallest to largest 43 string r = !foldl(!head(MxList), MxList, last, curr, curr); 44} 45// Helper function to get the smallest SEW that can be used with LMUL mx 46// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx> 47class SmallestSEW<string mx, bit isF = 0> { 48 int r = !head(SchedSEWSet<mx, isF>.val); 49} 50 51// Creates WriteRes for (name, mx, resources) tuple 52multiclass LMULWriteResMX<string name, list<ProcResourceKind> resources, 53 string mx, bit IsWorstCase> { 54 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>; 55 if IsWorstCase then 56 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 57} 58multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources, 59 string mx, int sew, bit IsWorstCase> { 60 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>; 61 if IsWorstCase then 62 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 63} 64 65// Define a SchedAlias for the SchedWrite associated with (name, mx) whose 66// behavior is aliased to a Variant. The Variant has Latency predLad and 67// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has 68// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite 69// is created similiarly if IsWorstCase is true. 70multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred, 71 list<ProcResourceKind> resources, 72 int predLat, list<int> predAcquireCycles, 73 list<int> predReleaseCycles, int noPredLat, 74 list<int> noPredAcquireCycles, 75 list<int> noPredReleaseCycles, 76 string mx, bit IsWorstCase> { 77 defvar nameMX = name # "_" # mx; 78 79 // Define the different behaviors 80 def nameMX # "_Pred" : SchedWriteRes<resources>{ 81 let Latency = predLat; 82 let AcquireAtCycles = predAcquireCycles; 83 let ReleaseAtCycles = predReleaseCycles; 84 } 85 def nameMX # "_NoPred" : SchedWriteRes<resources> { 86 let Latency = noPredLat; 87 let AcquireAtCycles = noPredAcquireCycles; 88 let ReleaseAtCycles = noPredReleaseCycles; 89 } 90 91 // Define SchedVars 92 def nameMX # PredSchedVar 93 : SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>; 94 def nameMX # NoPredSchedVar 95 : SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX #"_NoPred")]>; 96 // Allow multiclass to refer to SchedVars -- need to have NAME prefix. 97 defvar PredSchedVar = !cast<SchedVar>(NAME # nameMX # PredSchedVar); 98 defvar NoPredSchedVar = !cast<SchedVar>(NAME # nameMX # NoPredSchedVar); 99 100 // Tie behavior to predicate 101 def NAME # nameMX # "_Variant" 102 : SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>; 103 def : SchedAlias< 104 !cast<SchedReadWrite>(nameMX), 105 !cast<SchedReadWrite>(NAME # nameMX # "_Variant")>; 106 107 if IsWorstCase then { 108 def NAME # name # "_WorstCase_Variant" 109 : SchedWriteVariant<[PredSchedVar, NoPredSchedVar]>; 110 def : SchedAlias< 111 !cast<SchedReadWrite>(name # "_WorstCase"), 112 !cast<SchedReadWrite>(NAME # name # "_WorstCase_Variant")>; 113 } 114} 115 116// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and 117// ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the 118// SchedMxList variants above. Each multiclass is responsible for defining 119// a record that represents the WorseCase behavior for name. 120multiclass LMULSchedWritesImpl<string name, list<string> MxList> { 121 def name # "_WorstCase" : SchedWrite; 122 foreach mx = MxList in { 123 def name # "_" # mx : SchedWrite; 124 } 125} 126multiclass LMULSchedReadsImpl<string name, list<string> MxList> { 127 def name # "_WorstCase" : SchedRead; 128 foreach mx = MxList in { 129 def name # "_" # mx : SchedRead; 130 } 131} 132multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> { 133 if !exists<SchedWrite>(name # "_WorstCase") then 134 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 135 foreach mx = SchedMxList in { 136 if !exists<SchedWrite>(name # "_" # mx) then 137 def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>; 138 } 139} 140multiclass LMULReadAdvanceImpl<string name, int val, 141 list<SchedWrite> writes = []> { 142 if !exists<SchedRead>(name # "_WorstCase") then 143 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>; 144 foreach mx = SchedMxList in { 145 if !exists<SchedRead>(name # "_" # mx) then 146 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>; 147 } 148} 149 150// Define multiclasses to define SchedWrite, SchedRead, WriteRes, and 151// ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the 152// SchedMxList variants above. Each multiclass is responsible for defining 153// a record that represents the WorseCase behavior for name. 154multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0, 155 bit isWidening = 0> { 156 def name # "_WorstCase" : SchedWrite; 157 foreach mx = MxList in { 158 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 159 def name # "_" # mx # "_E" # sew : SchedWrite; 160 } 161} 162multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0, 163 bit isWidening = 0> { 164 def name # "_WorstCase" : SchedRead; 165 foreach mx = MxList in { 166 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 167 def name # "_" # mx # "_E" # sew : SchedRead; 168 } 169} 170multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources, 171 list<string> MxList, bit isF = 0, 172 bit isWidening = 0> { 173 if !exists<SchedWrite>(name # "_WorstCase") then 174 def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>; 175 foreach mx = MxList in { 176 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 177 if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then 178 def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>; 179 } 180} 181multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [], 182 list<string> MxList, bit isF = 0, 183 bit isWidening = 0> { 184 if !exists<SchedRead>(name # "_WorstCase") then 185 def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>; 186 foreach mx = MxList in { 187 foreach sew = SchedSEWSet<mx, isF, isWidening>.val in 188 if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then 189 def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>; 190 } 191} 192// Define classes to define list containing all SchedWrites for each (name, LMUL) 193// pair for each LMUL in each of the SchedMxList variants above and name in 194// argument `names`. These classes can be used to construct a list of existing 195// definitions of writes corresponding to each (name, LMUL) pair, that are needed 196// by the ReadAdvance. For example: 197// ``` 198// defm "" : LMULReadAdvance<"ReadVIALUX", 1, 199// LMULSchedWriteList<["WriteVMovSX"]>.value>; 200// ``` 201class LMULSchedWriteListImpl<list<string> names, list<string> MxList> { 202 list<SchedWrite> value = !foldl([]<SchedWrite>, 203 !foreach(name, names, 204 !foreach(mx, MxList, !cast<SchedWrite>(name # "_" # mx))), 205 all, writes, !listconcat(all, writes)); 206} 207 208multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>; 209multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>; 210multiclass LMULWriteRes<string name, list<ProcResourceKind> resources> 211 : LMULWriteResImpl<name, resources>; 212multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []> 213 : LMULReadAdvanceImpl<name, val, writes>; 214class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>; 215 216multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>; 217multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>; 218multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources> 219 : LMULSEWWriteResImpl<name, resources, SchedMxList>; 220multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []> 221 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxList>; 222 223multiclass LMULSEWSchedWritesWRed<string name> 224 : LMULSEWSchedWritesImpl<name, SchedMxListWRed, isWidening=1>; 225multiclass LMULSEWWriteResWRed<string name, list<ProcResourceKind> resources> 226 : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, isWidening=1>; 227 228multiclass LMULSEWSchedWritesFWRed<string name> 229 : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, isF=1, isWidening=1>; 230multiclass LMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources> 231 : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>; 232 233multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, isF=1>; 234multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, isF=1>; 235multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources> 236 : LMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>; 237multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []> 238 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>; 239 240multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>; 241multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>; 242multiclass LMULWriteResW<string name, list<ProcResourceKind> resources> 243 : LMULWriteResImpl<name, resources>; 244multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []> 245 : LMULReadAdvanceImpl<name, val, writes>; 246class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>; 247 248multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>; 249multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>; 250multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources> 251 : LMULWriteResImpl<name, resources>; 252multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []> 253 : LMULReadAdvanceImpl<name, val, writes>; 254class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>; 255 256multiclass LMULSEWSchedWritesW<string name> 257 : LMULSEWSchedWritesImpl<name, SchedMxListW, isF = 0, isWidening = 1>; 258multiclass LMULSEWSchedReadsW<string name> 259 : LMULSEWSchedReadsImpl<name, SchedMxListW, isF = 0, isWidening = 1>; 260multiclass LMULSEWWriteResW<string name, list<ProcResourceKind> resources> 261 : LMULSEWWriteResImpl<name, resources, SchedMxListW, isF = 0, 262 isWidening = 1>; 263multiclass 264 LMULSEWReadAdvanceW<string name, int val, list<SchedWrite> writes = []> 265 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListW, isF = 0, 266 isWidening = 1>; 267 268multiclass LMULSEWSchedWritesFW<string name> 269 : LMULSEWSchedWritesImpl<name, SchedMxListFW, isF = 1, isWidening = 1>; 270multiclass LMULSEWSchedReadsFW<string name> 271 : LMULSEWSchedReadsImpl<name, SchedMxListFW, isF = 1, isWidening = 1>; 272multiclass LMULSEWWriteResFW<string name, list<ProcResourceKind> resources> 273 : LMULSEWWriteResImpl<name, resources, SchedMxListFW, isF = 1, 274 isWidening = 1>; 275multiclass 276 LMULSEWReadAdvanceFW<string name, int val, list<SchedWrite> writes = []> 277 : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListFW, isF = 1, 278 isWidening = 1>; 279 280// 3.6 Vector Byte Length vlenb 281def WriteRdVLENB : SchedWrite; 282 283// 6. Configuration-Setting Instructions 284def WriteVSETVLI : SchedWrite; 285def WriteVSETIVLI : SchedWrite; 286def WriteVSETVL : SchedWrite; 287 288// 7. Vector Loads and Stores 289// 7.4. Vector Unit-Stride Instructions 290defm "" : LMULSchedWrites<"WriteVLDE">; 291defm "" : LMULSchedWrites<"WriteVSTE">; 292// 7.4.1. Vector Unit-Strided Mask 293defm "" : LMULSchedWrites<"WriteVLDM">; 294defm "" : LMULSchedWrites<"WriteVSTM">; 295// 7.5. Vector Strided Instructions 296defm "" : LMULSchedWrites<"WriteVLDS8">; 297defm "" : LMULSchedWrites<"WriteVLDS16">; 298defm "" : LMULSchedWrites<"WriteVLDS32">; 299defm "" : LMULSchedWrites<"WriteVLDS64">; 300defm "" : LMULSchedWrites<"WriteVSTS8">; 301defm "" : LMULSchedWrites<"WriteVSTS16">; 302defm "" : LMULSchedWrites<"WriteVSTS32">; 303defm "" : LMULSchedWrites<"WriteVSTS64">; 304// 7.6. Vector Indexed Instructions 305defm "" : LMULSchedWrites<"WriteVLDUX8">; 306defm "" : LMULSchedWrites<"WriteVLDUX16">; 307defm "" : LMULSchedWrites<"WriteVLDUX32">; 308defm "" : LMULSchedWrites<"WriteVLDUX64">; 309defm "" : LMULSchedWrites<"WriteVLDOX8">; 310defm "" : LMULSchedWrites<"WriteVLDOX16">; 311defm "" : LMULSchedWrites<"WriteVLDOX32">; 312defm "" : LMULSchedWrites<"WriteVLDOX64">; 313defm "" : LMULSchedWrites<"WriteVSTUX8">; 314defm "" : LMULSchedWrites<"WriteVSTUX16">; 315defm "" : LMULSchedWrites<"WriteVSTUX32">; 316defm "" : LMULSchedWrites<"WriteVSTUX64">; 317defm "" : LMULSchedWrites<"WriteVSTOX8">; 318defm "" : LMULSchedWrites<"WriteVSTOX16">; 319defm "" : LMULSchedWrites<"WriteVSTOX32">; 320defm "" : LMULSchedWrites<"WriteVSTOX64">; 321// 7.7. Vector Unit-stride Fault-Only-First Loads 322defm "" : LMULSchedWrites<"WriteVLDFF">; 323// 7.8. Vector Segment Instructions 324foreach nf=2-8 in { 325 foreach eew = [8, 16, 32, 64] in { 326 defm "" : LMULSchedWrites<"WriteVLSEG" # nf # e # eew>; 327 defm "" : LMULSchedWrites<"WriteVSSEG" # nf # e # eew>; 328 defm "" : LMULSchedWrites<"WriteVLSEGFF" # nf # e # eew>; 329 defm "" : LMULSchedWrites<"WriteVLSSEG" # nf # e # eew>; 330 defm "" : LMULSchedWrites<"WriteVSSSEG" # nf # e # eew>; 331 defm "" : LMULSchedWrites<"WriteVLUXSEG" # nf # e # eew>; 332 defm "" : LMULSchedWrites<"WriteVLOXSEG" # nf # e # eew>; 333 defm "" : LMULSchedWrites<"WriteVSUXSEG" # nf # e # eew>; 334 defm "" : LMULSchedWrites<"WriteVSOXSEG" # nf # e # eew>; 335 } 336} 337// 7.9. Vector Whole Register Instructions 338def WriteVLD1R : SchedWrite; 339def WriteVLD2R : SchedWrite; 340def WriteVLD4R : SchedWrite; 341def WriteVLD8R : SchedWrite; 342def WriteVST1R : SchedWrite; 343def WriteVST2R : SchedWrite; 344def WriteVST4R : SchedWrite; 345def WriteVST8R : SchedWrite; 346 347// 11. Vector Integer Arithmetic Instructions 348// 11.1. Vector Single-Width Integer Add and Subtract 349// 11.5. Vector Bitwise Logical Instructions 350defm "" : LMULSchedWrites<"WriteVIALUV">; 351defm "" : LMULSchedWrites<"WriteVIALUX">; 352defm "" : LMULSchedWrites<"WriteVIALUI">; 353// 11.2. Vector Widening Integer Add/Subtract 354defm "" : LMULSchedWritesW<"WriteVIWALUV">; 355defm "" : LMULSchedWritesW<"WriteVIWALUX">; 356defm "" : LMULSchedWritesW<"WriteVIWALUI">; 357// 11.3. Vector Integer Extension 358defm "" : LMULSchedWrites<"WriteVExtV">; 359// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions 360defm "" : LMULSchedWrites<"WriteVICALUV">; 361defm "" : LMULSchedWrites<"WriteVICALUX">; 362defm "" : LMULSchedWrites<"WriteVICALUI">; 363// 11.6. Vector Single-Width Bit Shift Instructions 364defm "" : LMULSchedWrites<"WriteVShiftV">; 365defm "" : LMULSchedWrites<"WriteVShiftX">; 366defm "" : LMULSchedWrites<"WriteVShiftI">; 367// 11.7. Vector Narrowing Integer Right Shift Instructions 368defm "" : LMULSchedWritesW<"WriteVNShiftV">; 369defm "" : LMULSchedWritesW<"WriteVNShiftX">; 370defm "" : LMULSchedWritesW<"WriteVNShiftI">; 371// 11.8. Vector Integer Comparison Instructions 372defm "" : LMULSchedWrites<"WriteVICmpV">; 373defm "" : LMULSchedWrites<"WriteVICmpX">; 374defm "" : LMULSchedWrites<"WriteVICmpI">; 375// 11.9. Vector Integer Min/Max Instructions 376defm "" : LMULSchedWrites<"WriteVIMinMaxV">; 377defm "" : LMULSchedWrites<"WriteVIMinMaxX">; 378// 11.10. Vector Single-Width Integer Multiply Instructions 379defm "" : LMULSchedWrites<"WriteVIMulV">; 380defm "" : LMULSchedWrites<"WriteVIMulX">; 381// 11.11. Vector Integer Divide Instructions 382defm "" : LMULSEWSchedWrites<"WriteVIDivV">; 383defm "" : LMULSEWSchedWrites<"WriteVIDivX">; 384// 11.12. Vector Widening Integer Multiply Instructions 385defm "" : LMULSchedWritesW<"WriteVIWMulV">; 386defm "" : LMULSchedWritesW<"WriteVIWMulX">; 387// 11.13. Vector Single-Width Integer Multiply-Add Instructions 388defm "" : LMULSchedWrites<"WriteVIMulAddV">; 389defm "" : LMULSchedWrites<"WriteVIMulAddX">; 390// 11.14. Vector Widening Integer Multiply-Add Instructions 391defm "" : LMULSchedWritesW<"WriteVIWMulAddV">; 392defm "" : LMULSchedWritesW<"WriteVIWMulAddX">; 393// 11.15. Vector Integer Merge Instructions 394defm "" : LMULSchedWrites<"WriteVIMergeV">; 395defm "" : LMULSchedWrites<"WriteVIMergeX">; 396defm "" : LMULSchedWrites<"WriteVIMergeI">; 397// 11.16. Vector Integer Move Instructions 398defm "" : LMULSchedWrites<"WriteVIMovV">; 399defm "" : LMULSchedWrites<"WriteVIMovX">; 400defm "" : LMULSchedWrites<"WriteVIMovI">; 401 402// 12. Vector Fixed-Point Arithmetic Instructions 403// 12.1. Vector Single-Width Saturating Add and Subtract 404defm "" : LMULSchedWrites<"WriteVSALUV">; 405defm "" : LMULSchedWrites<"WriteVSALUX">; 406defm "" : LMULSchedWrites<"WriteVSALUI">; 407// 12.2. Vector Single-Width Averaging Add and Subtract 408defm "" : LMULSchedWrites<"WriteVAALUV">; 409defm "" : LMULSchedWrites<"WriteVAALUX">; 410// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 411defm "" : LMULSchedWrites<"WriteVSMulV">; 412defm "" : LMULSchedWrites<"WriteVSMulX">; 413// 12.4. Vector Single-Width Scaling Shift Instructions 414defm "" : LMULSchedWrites<"WriteVSShiftV">; 415defm "" : LMULSchedWrites<"WriteVSShiftX">; 416defm "" : LMULSchedWrites<"WriteVSShiftI">; 417// 12.5. Vector Narrowing Fixed-Point Clip Instructions 418defm "" : LMULSchedWritesW<"WriteVNClipV">; 419defm "" : LMULSchedWritesW<"WriteVNClipX">; 420defm "" : LMULSchedWritesW<"WriteVNClipI">; 421 422// 13. Vector Floating-Point Instructions 423// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 424defm "" : LMULSEWSchedWritesF<"WriteVFALUV">; 425defm "" : LMULSEWSchedWritesF<"WriteVFALUF">; 426// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 427defm "" : LMULSEWSchedWritesFW<"WriteVFWALUV">; 428defm "" : LMULSEWSchedWritesFW<"WriteVFWALUF">; 429// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 430defm "" : LMULSEWSchedWritesF<"WriteVFMulV">; 431defm "" : LMULSEWSchedWritesF<"WriteVFMulF">; 432defm "" : LMULSEWSchedWritesF<"WriteVFDivV">; 433defm "" : LMULSEWSchedWritesF<"WriteVFDivF">; 434// 13.5. Vector Widening Floating-Point Multiply 435defm "" : LMULSEWSchedWritesFW<"WriteVFWMulV">; 436defm "" : LMULSEWSchedWritesFW<"WriteVFWMulF">; 437// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 438defm "" : LMULSEWSchedWritesF<"WriteVFMulAddV">; 439defm "" : LMULSEWSchedWritesF<"WriteVFMulAddF">; 440// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 441defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddV">; 442defm "" : LMULSEWSchedWritesFW<"WriteVFWMulAddF">; 443// 13.8. Vector Floating-Point Square-Root Instruction 444defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">; 445// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 446// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 447defm "" : LMULSEWSchedWritesF<"WriteVFRecpV">; 448// 13.11. Vector Floating-Point MIN/MAX Instructions 449defm "" : LMULSEWSchedWritesF<"WriteVFMinMaxV">; 450defm "" : LMULSEWSchedWritesF<"WriteVFMinMaxF">; 451// 13.12. Vector Floating-Point Sign-Injection Instructions 452defm "" : LMULSEWSchedWritesF<"WriteVFSgnjV">; 453defm "" : LMULSEWSchedWritesF<"WriteVFSgnjF">; 454// 13.13. Vector Floating-Point Compare Instructions 455defm "" : LMULSchedWrites<"WriteVFCmpV">; 456defm "" : LMULSchedWrites<"WriteVFCmpF">; 457// 13.14. Vector Floating-Point Classify Instruction 458defm "" : LMULSchedWrites<"WriteVFClassV">; 459// 13.15. Vector Floating-Point Merge Instruction 460defm "" : LMULSchedWrites<"WriteVFMergeV">; 461// 13.16. Vector Floating-Point Move Instruction 462defm "" : LMULSchedWrites<"WriteVFMovV">; 463// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 464defm "" : LMULSEWSchedWritesF<"WriteVFCvtIToFV">; 465defm "" : LMULSchedWrites<"WriteVFCvtFToIV">; 466// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 467defm "" : LMULSEWSchedWritesW<"WriteVFWCvtIToFV">; 468defm "" : LMULSchedWritesFW<"WriteVFWCvtFToIV">; 469defm "" : LMULSEWSchedWritesFW<"WriteVFWCvtFToFV">; 470// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 471defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtIToFV">; 472defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">; 473defm "" : LMULSEWSchedWritesFW<"WriteVFNCvtFToFV">; 474 475// 14. Vector Reduction Operations 476// The latency of reduction is determined by the size of the read resource. 477// The LMUL range of read resource(VS2) for reduction operantion is between 478// MF8 and M8. Use the _From suffix to indicate the number of the 479// LMUL from VS2. 480// 14.1. Vector Single-Width Integer Reduction Instructions 481defm "" : LMULSEWSchedWrites<"WriteVIRedV_From">; 482defm "" : LMULSEWSchedWrites<"WriteVIRedMinMaxV_From">; 483// 14.2. Vector Widening Integer Reduction Instructions 484defm "" : LMULSEWSchedWritesWRed<"WriteVIWRedV_From">; 485// 14.3. Vector Single-Width Floating-Point Reduction Instructions 486defm "" : LMULSEWSchedWritesF<"WriteVFRedV_From">; 487defm "" : LMULSEWSchedWritesF<"WriteVFRedOV_From">; 488defm "" : LMULSEWSchedWritesF<"WriteVFRedMinMaxV_From">; 489// 14.4. Vector Widening Floating-Point Reduction Instructions 490defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedV_From">; 491defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedOV_From">; 492 493// 15. Vector Mask Instructions 494// 15.1. Vector Mask-Register Logical Instructions 495defm "" : LMULSchedWrites<"WriteVMALUV">; 496// 15.2. Vector Mask Population Count 497defm "" : LMULSchedWrites<"WriteVMPopV">; 498// 15.3. Vector Find-First-Set Mask Bit 499defm "" : LMULSchedWrites<"WriteVMFFSV">; 500// 15.4. Vector Set-Before-First Mask Bit 501// 15.5. Vector Set-Including-First Mask Bit 502// 15.6. Vector Set-only-First Mask Bit 503defm "" : LMULSchedWrites<"WriteVMSFSV">; 504// 15.8. Vector Iota Instruction 505defm "" : LMULSchedWrites<"WriteVIotaV">; 506// 15.9. Vector Element Index Instruction 507defm "" : LMULSchedWrites<"WriteVIdxV">; 508 509// 16. Vector Permutation Instructions 510// 16.1. Integer Scalar Move Instructions 511def WriteVMovSX : SchedWrite; 512def WriteVMovXS : SchedWrite; 513// 16.2. Floating-Point Scalar Move Instructions 514def WriteVMovSF : SchedWrite; 515def WriteVMovFS : SchedWrite; 516// 16.3. Vector Slide Instructions 517defm "" : LMULSchedWrites<"WriteVSlideUpX">; 518defm "" : LMULSchedWrites<"WriteVSlideDownX">; 519defm "" : LMULSchedWrites<"WriteVSlideI">; 520defm "" : LMULSchedWrites<"WriteVISlide1X">; 521defm "" : LMULSchedWrites<"WriteVFSlide1F">; 522// 16.4. Vector Register Gather Instructions 523defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">; 524defm "" : LMULSEWSchedWrites<"WriteVRGatherEI16VV">; 525defm "" : LMULSchedWrites<"WriteVRGatherVX">; 526defm "" : LMULSchedWrites<"WriteVRGatherVI">; 527// 16.5. Vector Compress Instruction 528defm "" : LMULSEWSchedWrites<"WriteVCompressV">; 529// 16.6. Whole Vector Register Move 530// These are already LMUL aware 531def WriteVMov1V : SchedWrite; 532def WriteVMov2V : SchedWrite; 533def WriteVMov4V : SchedWrite; 534def WriteVMov8V : SchedWrite; 535 536//===----------------------------------------------------------------------===// 537/// Define scheduler resources associated with use operands. 538 539// 6. Configuration-Setting Instructions 540def ReadVSETVLI : SchedRead; 541def ReadVSETVL : SchedRead; 542 543// 7. Vector Loads and Stores 544def ReadVLDX : SchedRead; 545def ReadVSTX : SchedRead; 546// 7.4. Vector Unit-Stride Instructions 547defm "" : LMULSchedReads<"ReadVSTEV">; 548// 7.4.1. Vector Unit-Strided Mask 549defm "" : LMULSchedReads<"ReadVSTM">; 550// 7.5. Vector Strided Instructions 551def ReadVLDSX : SchedRead; 552def ReadVSTSX : SchedRead; 553defm "" : LMULSchedReads<"ReadVSTS8V">; 554defm "" : LMULSchedReads<"ReadVSTS16V">; 555defm "" : LMULSchedReads<"ReadVSTS32V">; 556defm "" : LMULSchedReads<"ReadVSTS64V">; 557// 7.6. Vector Indexed Instructions 558defm "" : LMULSchedReads<"ReadVLDUXV">; 559defm "" : LMULSchedReads<"ReadVLDOXV">; 560defm "" : LMULSchedReads<"ReadVSTUX8">; 561defm "" : LMULSchedReads<"ReadVSTUX16">; 562defm "" : LMULSchedReads<"ReadVSTUX32">; 563defm "" : LMULSchedReads<"ReadVSTUX64">; 564defm "" : LMULSchedReads<"ReadVSTUXV">; 565defm "" : LMULSchedReads<"ReadVSTUX8V">; 566defm "" : LMULSchedReads<"ReadVSTUX16V">; 567defm "" : LMULSchedReads<"ReadVSTUX32V">; 568defm "" : LMULSchedReads<"ReadVSTUX64V">; 569defm "" : LMULSchedReads<"ReadVSTOX8">; 570defm "" : LMULSchedReads<"ReadVSTOX16">; 571defm "" : LMULSchedReads<"ReadVSTOX32">; 572defm "" : LMULSchedReads<"ReadVSTOX64">; 573defm "" : LMULSchedReads<"ReadVSTOXV">; 574defm "" : LMULSchedReads<"ReadVSTOX8V">; 575defm "" : LMULSchedReads<"ReadVSTOX16V">; 576defm "" : LMULSchedReads<"ReadVSTOX32V">; 577defm "" : LMULSchedReads<"ReadVSTOX64V">; 578// 7.9. Vector Whole Register Instructions 579// These are already LMUL aware 580def ReadVST1R : SchedRead; 581def ReadVST2R : SchedRead; 582def ReadVST4R : SchedRead; 583def ReadVST8R : SchedRead; 584 585// 11. Vector Integer Arithmetic Instructions 586// 11.1. Vector Single-Width Integer Add and Subtract 587// 11.5. Vector Bitwise Logical Instructions 588defm "" : LMULSchedReads<"ReadVIALUV">; 589defm "" : LMULSchedReads<"ReadVIALUX">; 590// 11.2. Vector Widening Integer Add/Subtract 591defm "" : LMULSchedReadsW<"ReadVIWALUV">; 592defm "" : LMULSchedReadsW<"ReadVIWALUX">; 593// 11.3. Vector Integer Extension 594defm "" : LMULSchedReads<"ReadVExtV">; 595// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions 596defm "" : LMULSchedReads<"ReadVICALUV">; 597defm "" : LMULSchedReads<"ReadVICALUX">; 598// 11.6. Vector Single-Width Bit Shift Instructions 599defm "" : LMULSchedReads<"ReadVShiftV">; 600defm "" : LMULSchedReads<"ReadVShiftX">; 601// 11.7. Vector Narrowing Integer Right Shift Instructions 602defm "" : LMULSchedReadsW<"ReadVNShiftV">; 603defm "" : LMULSchedReadsW<"ReadVNShiftX">; 604// 11.8. Vector Integer Comparison Instructions 605defm "" : LMULSchedReads<"ReadVICmpV">; 606defm "" : LMULSchedReads<"ReadVICmpX">; 607// 11.9. Vector Integer Min/Max Instructions 608defm "" : LMULSchedReads<"ReadVIMinMaxV">; 609defm "" : LMULSchedReads<"ReadVIMinMaxX">; 610// 11.10. Vector Single-Width Integer Multiply Instructions 611defm "" : LMULSchedReads<"ReadVIMulV">; 612defm "" : LMULSchedReads<"ReadVIMulX">; 613// 11.11. Vector Integer Divide Instructions 614defm "" : LMULSEWSchedReads<"ReadVIDivV">; 615defm "" : LMULSEWSchedReads<"ReadVIDivX">; 616// 11.12. Vector Widening Integer Multiply Instructions 617defm "" : LMULSchedReadsW<"ReadVIWMulV">; 618defm "" : LMULSchedReadsW<"ReadVIWMulX">; 619// 11.13. Vector Single-Width Integer Multiply-Add Instructions 620defm "" : LMULSchedReads<"ReadVIMulAddV">; 621defm "" : LMULSchedReads<"ReadVIMulAddX">; 622// 11.14. Vector Widening Integer Multiply-Add Instructions 623defm "" : LMULSchedReadsW<"ReadVIWMulAddV">; 624defm "" : LMULSchedReadsW<"ReadVIWMulAddX">; 625// 11.15. Vector Integer Merge Instructions 626defm "" : LMULSchedReads<"ReadVIMergeV">; 627defm "" : LMULSchedReads<"ReadVIMergeX">; 628// 11.16. Vector Integer Move Instructions 629defm "" : LMULSchedReads<"ReadVIMovV">; 630defm "" : LMULSchedReads<"ReadVIMovX">; 631 632// 12. Vector Fixed-Point Arithmetic Instructions 633// 12.1. Vector Single-Width Saturating Add and Subtract 634defm "" : LMULSchedReads<"ReadVSALUV">; 635defm "" : LMULSchedReads<"ReadVSALUX">; 636// 12.2. Vector Single-Width Averaging Add and Subtract 637defm "" : LMULSchedReads<"ReadVAALUV">; 638defm "" : LMULSchedReads<"ReadVAALUX">; 639// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation 640defm "" : LMULSchedReads<"ReadVSMulV">; 641defm "" : LMULSchedReads<"ReadVSMulX">; 642// 12.4. Vector Single-Width Scaling Shift Instructions 643defm "" : LMULSchedReads<"ReadVSShiftV">; 644defm "" : LMULSchedReads<"ReadVSShiftX">; 645// 12.5. Vector Narrowing Fixed-Point Clip Instructions 646defm "" : LMULSchedReadsW<"ReadVNClipV">; 647defm "" : LMULSchedReadsW<"ReadVNClipX">; 648 649// 13. Vector Floating-Point Instructions 650// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions 651defm "" : LMULSEWSchedReadsF<"ReadVFALUV">; 652defm "" : LMULSEWSchedReadsF<"ReadVFALUF">; 653// 13.3. Vector Widening Floating-Point Add/Subtract Instructions 654defm "" : LMULSEWSchedReadsFW<"ReadVFWALUV">; 655defm "" : LMULSEWSchedReadsFW<"ReadVFWALUF">; 656// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 657defm "" : LMULSEWSchedReadsF<"ReadVFMulV">; 658defm "" : LMULSEWSchedReadsF<"ReadVFMulF">; 659defm "" : LMULSEWSchedReadsF<"ReadVFDivV">; 660defm "" : LMULSEWSchedReadsF<"ReadVFDivF">; 661// 13.5. Vector Widening Floating-Point Multiply 662defm "" : LMULSEWSchedReadsFW<"ReadVFWMulV">; 663defm "" : LMULSEWSchedReadsFW<"ReadVFWMulF">; 664// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions 665defm "" : LMULSEWSchedReadsF<"ReadVFMulAddV">; 666defm "" : LMULSEWSchedReadsF<"ReadVFMulAddF">; 667// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 668defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddV">; 669defm "" : LMULSEWSchedReadsFW<"ReadVFWMulAddF">; 670// 13.8. Vector Floating-Point Square-Root Instruction 671defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">; 672// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction 673// 13.10. Vector Floating-Point Reciprocal Estimate Instruction 674defm "" : LMULSEWSchedReadsF<"ReadVFRecpV">; 675// 13.11. Vector Floating-Point MIN/MAX Instructions 676defm "" : LMULSEWSchedReadsF<"ReadVFMinMaxV">; 677defm "" : LMULSEWSchedReadsF<"ReadVFMinMaxF">; 678// 13.12. Vector Floating-Point Sign-Injection Instructions 679defm "" : LMULSEWSchedReadsF<"ReadVFSgnjV">; 680defm "" : LMULSEWSchedReadsF<"ReadVFSgnjF">; 681// 13.13. Vector Floating-Point Compare Instructions 682defm "" : LMULSchedReads<"ReadVFCmpV">; 683defm "" : LMULSchedReads<"ReadVFCmpF">; 684// 13.14. Vector Floating-Point Classify Instruction 685defm "" : LMULSchedReads<"ReadVFClassV">; 686// 13.15. Vector Floating-Point Merge Instruction 687defm "" : LMULSchedReads<"ReadVFMergeV">; 688defm "" : LMULSchedReads<"ReadVFMergeF">; 689// 13.16. Vector Floating-Point Move Instruction 690defm "" : LMULSchedReads<"ReadVFMovF">; 691// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions 692defm "" : LMULSEWSchedReadsF<"ReadVFCvtIToFV">; 693defm "" : LMULSchedReads<"ReadVFCvtFToIV">; 694// 13.18. Widening Floating-Point/Integer Type-Convert Instructions 695defm "" : LMULSEWSchedReadsW<"ReadVFWCvtIToFV">; 696defm "" : LMULSchedReadsFW<"ReadVFWCvtFToIV">; 697defm "" : LMULSEWSchedReadsFW<"ReadVFWCvtFToFV">; 698// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions 699defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtIToFV">; 700defm "" : LMULSchedReadsW<"ReadVFNCvtFToIV">; 701defm "" : LMULSEWSchedReadsFW<"ReadVFNCvtFToFV">; 702 703// 14. Vector Reduction Operations 704// 14.1. Vector Single-Width Integer Reduction Instructions 705def ReadVIRedV : SchedRead; 706def ReadVIRedV0 : SchedRead; 707// 14.2. Vector Widening Integer Reduction Instructions 708def ReadVIWRedV : SchedRead; 709def ReadVIWRedV0 : SchedRead; 710// 14.3. Vector Single-Width Floating-Point Reduction Instructions 711def ReadVFRedV : SchedRead; 712def ReadVFRedV0 : SchedRead; 713def ReadVFRedOV : SchedRead; 714def ReadVFRedOV0 : SchedRead; 715def ReadVFRedMinMaxV : SchedRead; 716// 14.4. Vector Widening Floating-Point Reduction Instructions 717def ReadVFWRedV : SchedRead; 718def ReadVFWRedV0 : SchedRead; 719def ReadVFWRedOV : SchedRead; 720def ReadVFWRedOV0 : SchedRead; 721 722// 15. Vector Mask Instructions 723// 15.1. Vector Mask-Register Logical Instructions 724defm "" : LMULSchedReads<"ReadVMALUV">; 725// 15.2. Vector Mask Population Count 726defm "" : LMULSchedReads<"ReadVMPopV">; 727// 15.3. Vector Find-First-Set Mask Bit 728defm "" : LMULSchedReads<"ReadVMFFSV">; 729// 15.4. Vector Set-Before-First Mask Bit 730// 15.5. Vector Set-Including-First Mask Bit 731// 15.6. Vector Set-only-First Mask Bit 732defm "" : LMULSchedReads<"ReadVMSFSV">; 733// 15.8. Vector Iota Instruction 734defm "" : LMULSchedReads<"ReadVIotaV">; 735 736// 16. Vector Permutation Instructions 737// 16.1. Integer Scalar Move Instructions 738def ReadVMovXS : SchedRead; 739def ReadVMovSX_V : SchedRead; 740def ReadVMovSX_X : SchedRead; 741// 16.2. Floating-Point Scalar Move Instructions 742def ReadVMovFS : SchedRead; 743def ReadVMovSF_V : SchedRead; 744def ReadVMovSF_F : SchedRead; 745// 16.3. Vector Slide Instructions 746defm "" : LMULSchedReads<"ReadVISlideV">; 747defm "" : LMULSchedReads<"ReadVISlideX">; 748defm "" : LMULSchedReads<"ReadVFSlideV">; 749defm "" : LMULSchedReads<"ReadVFSlideF">; 750// 16.4. Vector Register Gather Instructions 751defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">; 752defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">; 753defm "" : LMULSEWSchedReads<"ReadVRGatherEI16VV_data">; 754defm "" : LMULSEWSchedReads<"ReadVRGatherEI16VV_index">; 755defm "" : LMULSchedReads<"ReadVRGatherVX_data">; 756defm "" : LMULSchedReads<"ReadVRGatherVX_index">; 757defm "" : LMULSchedReads<"ReadVRGatherVI_data">; 758// 16.5. Vector Compress Instruction 759defm "" : LMULSEWSchedReads<"ReadVCompressV">; 760// 16.6. Whole Vector Register Move 761// These are already LMUL aware 762def ReadVMov1V : SchedRead; 763def ReadVMov2V : SchedRead; 764def ReadVMov4V : SchedRead; 765def ReadVMov8V : SchedRead; 766 767// Others 768def ReadVMask : SchedRead; 769def ReadVMergeOp_WorstCase : SchedRead; 770foreach mx = SchedMxList in { 771 def ReadVMergeOp_ # mx : SchedRead; 772 foreach sew = SchedSEWSet<mx>.val in 773 def ReadVMergeOp_ # mx # "_E" # sew : SchedRead; 774} 775 776//===----------------------------------------------------------------------===// 777/// Define default scheduler resources for V. 778 779multiclass UnsupportedSchedV { 780let Unsupported = true in { 781 782// 3.6 Vector Byte Length vlenb 783def : WriteRes<WriteRdVLENB, []>; 784 785// 6. Configuration-Setting Instructions 786def : WriteRes<WriteVSETVLI, []>; 787def : WriteRes<WriteVSETIVLI, []>; 788def : WriteRes<WriteVSETVL, []>; 789 790// 7. Vector Loads and Stores 791defm "" : LMULWriteRes<"WriteVLDE", []>; 792defm "" : LMULWriteRes<"WriteVSTE", []>; 793defm "" : LMULWriteRes<"WriteVLDM", []>; 794defm "" : LMULWriteRes<"WriteVSTM", []>; 795defm "" : LMULWriteRes<"WriteVLDS8", []>; 796defm "" : LMULWriteRes<"WriteVLDS16", []>; 797defm "" : LMULWriteRes<"WriteVLDS32", []>; 798defm "" : LMULWriteRes<"WriteVLDS64", []>; 799defm "" : LMULWriteRes<"WriteVSTS8", []>; 800defm "" : LMULWriteRes<"WriteVSTS16", []>; 801defm "" : LMULWriteRes<"WriteVSTS32", []>; 802defm "" : LMULWriteRes<"WriteVSTS64", []>; 803defm "" : LMULWriteRes<"WriteVLDUX8", []>; 804defm "" : LMULWriteRes<"WriteVLDUX16", []>; 805defm "" : LMULWriteRes<"WriteVLDUX32", []>; 806defm "" : LMULWriteRes<"WriteVLDUX64", []>; 807defm "" : LMULWriteRes<"WriteVLDOX8", []>; 808defm "" : LMULWriteRes<"WriteVLDOX16", []>; 809defm "" : LMULWriteRes<"WriteVLDOX32", []>; 810defm "" : LMULWriteRes<"WriteVLDOX64", []>; 811defm "" : LMULWriteRes<"WriteVSTUX8", []>; 812defm "" : LMULWriteRes<"WriteVSTUX16", []>; 813defm "" : LMULWriteRes<"WriteVSTUX32", []>; 814defm "" : LMULWriteRes<"WriteVSTUX64", []>; 815defm "" : LMULWriteRes<"WriteVSTOX8", []>; 816defm "" : LMULWriteRes<"WriteVSTOX16", []>; 817defm "" : LMULWriteRes<"WriteVSTOX32", []>; 818defm "" : LMULWriteRes<"WriteVSTOX64", []>; 819defm "" : LMULWriteRes<"WriteVLDFF", []>; 820// These are already LMUL aware 821def : WriteRes<WriteVLD1R, []>; 822def : WriteRes<WriteVLD2R, []>; 823def : WriteRes<WriteVLD4R, []>; 824def : WriteRes<WriteVLD8R, []>; 825def : WriteRes<WriteVST1R, []>; 826def : WriteRes<WriteVST2R, []>; 827def : WriteRes<WriteVST4R, []>; 828def : WriteRes<WriteVST8R, []>; 829// Vector Segment Loads and Stores 830foreach nf=2-8 in { 831 foreach eew = [8, 16, 32, 64] in { 832 defm "" : LMULWriteRes <"WriteVLSEG" # nf # "e" # eew, []>; 833 defm "" : LMULWriteRes <"WriteVLSEGFF" # nf # "e" # eew, []>; 834 defm "" : LMULWriteRes <"WriteVSSEG" # nf # "e" # eew, []>; 835 defm "" : LMULWriteRes <"WriteVLSSEG" # nf # "e" # eew, []>; 836 defm "" : LMULWriteRes <"WriteVSSSEG" # nf # "e" # eew, []>; 837 defm "" : LMULWriteRes <"WriteVLUXSEG" # nf # "e" # eew, []>; 838 defm "" : LMULWriteRes <"WriteVLOXSEG" # nf # "e" # eew, []>; 839 defm "" : LMULWriteRes <"WriteVSUXSEG" # nf # "e" # eew, []>; 840 defm "" : LMULWriteRes <"WriteVSOXSEG" # nf # "e" # eew, []>; 841 } 842} 843 844// 11. Vector Integer Arithmetic Instructions 845defm "" : LMULWriteRes<"WriteVIALUV", []>; 846defm "" : LMULWriteRes<"WriteVIALUX", []>; 847defm "" : LMULWriteRes<"WriteVIALUI", []>; 848defm "" : LMULWriteResW<"WriteVIWALUV", []>; 849defm "" : LMULWriteResW<"WriteVIWALUX", []>; 850defm "" : LMULWriteResW<"WriteVIWALUI", []>; 851defm "" : LMULWriteRes<"WriteVExtV", []>; 852defm "" : LMULWriteRes<"WriteVICALUV", []>; 853defm "" : LMULWriteRes<"WriteVICALUX", []>; 854defm "" : LMULWriteRes<"WriteVICALUI", []>; 855defm "" : LMULWriteRes<"WriteVShiftV", []>; 856defm "" : LMULWriteRes<"WriteVShiftX", []>; 857defm "" : LMULWriteRes<"WriteVShiftI", []>; 858defm "" : LMULWriteResW<"WriteVNShiftV", []>; 859defm "" : LMULWriteResW<"WriteVNShiftX", []>; 860defm "" : LMULWriteResW<"WriteVNShiftI", []>; 861defm "" : LMULWriteRes<"WriteVICmpV", []>; 862defm "" : LMULWriteRes<"WriteVICmpX", []>; 863defm "" : LMULWriteRes<"WriteVICmpI", []>; 864defm "" : LMULWriteRes<"WriteVIMinMaxV", []>; 865defm "" : LMULWriteRes<"WriteVIMinMaxX", []>; 866defm "" : LMULWriteRes<"WriteVIMulV", []>; 867defm "" : LMULWriteRes<"WriteVIMulX", []>; 868defm "" : LMULSEWWriteRes<"WriteVIDivV", []>; 869defm "" : LMULSEWWriteRes<"WriteVIDivX", []>; 870defm "" : LMULWriteResW<"WriteVIWMulV", []>; 871defm "" : LMULWriteResW<"WriteVIWMulX", []>; 872defm "" : LMULWriteRes<"WriteVIMulAddV", []>; 873defm "" : LMULWriteRes<"WriteVIMulAddX", []>; 874defm "" : LMULWriteResW<"WriteVIWMulAddV", []>; 875defm "" : LMULWriteResW<"WriteVIWMulAddX", []>; 876defm "" : LMULWriteRes<"WriteVIMergeV", []>; 877defm "" : LMULWriteRes<"WriteVIMergeX", []>; 878defm "" : LMULWriteRes<"WriteVIMergeI", []>; 879defm "" : LMULWriteRes<"WriteVIMovV", []>; 880defm "" : LMULWriteRes<"WriteVIMovX", []>; 881defm "" : LMULWriteRes<"WriteVIMovI", []>; 882 883// 12. Vector Fixed-Point Arithmetic Instructions 884defm "" : LMULWriteRes<"WriteVSALUV", []>; 885defm "" : LMULWriteRes<"WriteVSALUX", []>; 886defm "" : LMULWriteRes<"WriteVSALUI", []>; 887defm "" : LMULWriteRes<"WriteVAALUV", []>; 888defm "" : LMULWriteRes<"WriteVAALUX", []>; 889defm "" : LMULWriteRes<"WriteVSMulV", []>; 890defm "" : LMULWriteRes<"WriteVSMulX", []>; 891defm "" : LMULWriteRes<"WriteVSShiftV", []>; 892defm "" : LMULWriteRes<"WriteVSShiftX", []>; 893defm "" : LMULWriteRes<"WriteVSShiftI", []>; 894defm "" : LMULWriteResW<"WriteVNClipV", []>; 895defm "" : LMULWriteResW<"WriteVNClipX", []>; 896defm "" : LMULWriteResW<"WriteVNClipI", []>; 897 898// 13. Vector Floating-Point Instructions 899defm "" : LMULSEWWriteResF<"WriteVFALUV", []>; 900defm "" : LMULSEWWriteResF<"WriteVFALUF", []>; 901defm "" : LMULSEWWriteResFW<"WriteVFWALUV", []>; 902defm "" : LMULSEWWriteResFW<"WriteVFWALUF", []>; 903defm "" : LMULSEWWriteResF<"WriteVFMulV", []>; 904defm "" : LMULSEWWriteResF<"WriteVFMulF", []>; 905defm "" : LMULSEWWriteResF<"WriteVFDivV", []>; 906defm "" : LMULSEWWriteResF<"WriteVFDivF", []>; 907defm "" : LMULSEWWriteResFW<"WriteVFWMulV", []>; 908defm "" : LMULSEWWriteResFW<"WriteVFWMulF", []>; 909defm "" : LMULSEWWriteResF<"WriteVFMulAddV", []>; 910defm "" : LMULSEWWriteResF<"WriteVFMulAddF", []>; 911defm "" : LMULSEWWriteResFW<"WriteVFWMulAddV", []>; 912defm "" : LMULSEWWriteResFW<"WriteVFWMulAddF", []>; 913defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>; 914defm "" : LMULSEWWriteResF<"WriteVFRecpV", []>; 915defm "" : LMULSEWWriteResF<"WriteVFMinMaxV", []>; 916defm "" : LMULSEWWriteResF<"WriteVFMinMaxF", []>; 917defm "" : LMULSEWWriteResF<"WriteVFSgnjV", []>; 918defm "" : LMULSEWWriteResF<"WriteVFSgnjF", []>; 919defm "" : LMULWriteRes<"WriteVFCmpV", []>; 920defm "" : LMULWriteRes<"WriteVFCmpF", []>; 921defm "" : LMULWriteRes<"WriteVFClassV", []>; 922defm "" : LMULWriteRes<"WriteVFMergeV", []>; 923defm "" : LMULWriteRes<"WriteVFMovV", []>; 924defm "" : LMULSEWWriteResF<"WriteVFCvtIToFV", []>; 925defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>; 926defm "" : LMULSEWWriteResW<"WriteVFWCvtIToFV", []>; 927defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>; 928defm "" : LMULSEWWriteResFW<"WriteVFWCvtFToFV", []>; 929defm "" : LMULSEWWriteResFW<"WriteVFNCvtIToFV", []>; 930defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>; 931defm "" : LMULSEWWriteResFW<"WriteVFNCvtFToFV", []>; 932 933// 14. Vector Reduction Operations 934defm "" : LMULSEWWriteRes<"WriteVIRedV_From", []>; 935defm "" : LMULSEWWriteRes<"WriteVIRedMinMaxV_From", []>; 936defm "" : LMULSEWWriteResWRed<"WriteVIWRedV_From", []>; 937defm "" : LMULSEWWriteResF<"WriteVFRedV_From", []>; 938defm "" : LMULSEWWriteResF<"WriteVFRedOV_From", []>; 939defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>; 940defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", []>; 941defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>; 942 943// 15. Vector Mask Instructions 944defm "" : LMULWriteRes<"WriteVMALUV", []>; 945defm "" : LMULWriteRes<"WriteVMPopV", []>; 946defm "" : LMULWriteRes<"WriteVMFFSV", []>; 947defm "" : LMULWriteRes<"WriteVMSFSV", []>; 948defm "" : LMULWriteRes<"WriteVIotaV", []>; 949defm "" : LMULWriteRes<"WriteVIdxV", []>; 950 951// 16. Vector Permutation Instructions 952def : WriteRes<WriteVMovSX, []>; 953def : WriteRes<WriteVMovXS, []>; 954def : WriteRes<WriteVMovSF, []>; 955def : WriteRes<WriteVMovFS, []>; 956defm "" : LMULWriteRes<"WriteVSlideUpX", []>; 957defm "" : LMULWriteRes<"WriteVSlideDownX", []>; 958defm "" : LMULWriteRes<"WriteVSlideI", []>; 959defm "" : LMULWriteRes<"WriteVISlide1X", []>; 960defm "" : LMULWriteRes<"WriteVFSlide1F", []>; 961defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>; 962defm "" : LMULSEWWriteRes<"WriteVRGatherEI16VV", []>; 963defm "" : LMULWriteRes<"WriteVRGatherVX", []>; 964defm "" : LMULWriteRes<"WriteVRGatherVI", []>; 965defm "" : LMULSEWWriteRes<"WriteVCompressV", []>; 966// These are already LMUL aware 967def : WriteRes<WriteVMov1V, []>; 968def : WriteRes<WriteVMov2V, []>; 969def : WriteRes<WriteVMov4V, []>; 970def : WriteRes<WriteVMov8V, []>; 971 972// 6. Configuration-Setting Instructions 973def : ReadAdvance<ReadVSETVLI, 0>; 974def : ReadAdvance<ReadVSETVL, 0>; 975 976// 7. Vector Loads and Stores 977def : ReadAdvance<ReadVLDX, 0>; 978def : ReadAdvance<ReadVSTX, 0>; 979defm "" : LMULReadAdvance<"ReadVSTEV", 0>; 980defm "" : LMULReadAdvance<"ReadVSTM", 0>; 981def : ReadAdvance<ReadVLDSX, 0>; 982def : ReadAdvance<ReadVSTSX, 0>; 983defm "" : LMULReadAdvance<"ReadVSTS8V", 0>; 984defm "" : LMULReadAdvance<"ReadVSTS16V", 0>; 985defm "" : LMULReadAdvance<"ReadVSTS32V", 0>; 986defm "" : LMULReadAdvance<"ReadVSTS64V", 0>; 987defm "" : LMULReadAdvance<"ReadVLDUXV", 0>; 988defm "" : LMULReadAdvance<"ReadVLDOXV", 0>; 989defm "" : LMULReadAdvance<"ReadVSTUXV", 0>; 990defm "" : LMULReadAdvance<"ReadVSTUX8", 0>; 991defm "" : LMULReadAdvance<"ReadVSTUX16", 0>; 992defm "" : LMULReadAdvance<"ReadVSTUX32", 0>; 993defm "" : LMULReadAdvance<"ReadVSTUX64", 0>; 994defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>; 995defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>; 996defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>; 997defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>; 998defm "" : LMULReadAdvance<"ReadVSTOX8", 0>; 999defm "" : LMULReadAdvance<"ReadVSTOX16", 0>; 1000defm "" : LMULReadAdvance<"ReadVSTOX32", 0>; 1001defm "" : LMULReadAdvance<"ReadVSTOX64", 0>; 1002defm "" : LMULReadAdvance<"ReadVSTOXV", 0>; 1003defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>; 1004defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>; 1005defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>; 1006defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>; 1007// These are already LMUL aware 1008def : ReadAdvance<ReadVST1R, 0>; 1009def : ReadAdvance<ReadVST2R, 0>; 1010def : ReadAdvance<ReadVST4R, 0>; 1011def : ReadAdvance<ReadVST8R, 0>; 1012 1013// 11. Vector Integer Arithmetic Instructions 1014defm "" : LMULReadAdvance<"ReadVIALUV", 0>; 1015defm "" : LMULReadAdvance<"ReadVIALUX", 0>; 1016defm "" : LMULReadAdvanceW<"ReadVIWALUV", 0>; 1017defm "" : LMULReadAdvanceW<"ReadVIWALUX", 0>; 1018defm "" : LMULReadAdvance<"ReadVExtV", 0>; 1019defm "" : LMULReadAdvance<"ReadVICALUV", 0>; 1020defm "" : LMULReadAdvance<"ReadVICALUX", 0>; 1021defm "" : LMULReadAdvance<"ReadVShiftV", 0>; 1022defm "" : LMULReadAdvance<"ReadVShiftX", 0>; 1023defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>; 1024defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>; 1025defm "" : LMULReadAdvance<"ReadVICmpV", 0>; 1026defm "" : LMULReadAdvance<"ReadVICmpX", 0>; 1027defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>; 1028defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>; 1029defm "" : LMULReadAdvance<"ReadVIMulV", 0>; 1030defm "" : LMULReadAdvance<"ReadVIMulX", 0>; 1031defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>; 1032defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>; 1033defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>; 1034defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>; 1035defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>; 1036defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>; 1037defm "" : LMULReadAdvanceW<"ReadVIWMulAddV", 0>; 1038defm "" : LMULReadAdvanceW<"ReadVIWMulAddX", 0>; 1039defm "" : LMULReadAdvance<"ReadVIMergeV", 0>; 1040defm "" : LMULReadAdvance<"ReadVIMergeX", 0>; 1041defm "" : LMULReadAdvance<"ReadVIMovV", 0>; 1042defm "" : LMULReadAdvance<"ReadVIMovX", 0>; 1043 1044// 12. Vector Fixed-Point Arithmetic Instructions 1045defm "" : LMULReadAdvance<"ReadVSALUV", 0>; 1046defm "" : LMULReadAdvance<"ReadVSALUX", 0>; 1047defm "" : LMULReadAdvance<"ReadVAALUV", 0>; 1048defm "" : LMULReadAdvance<"ReadVAALUX", 0>; 1049defm "" : LMULReadAdvance<"ReadVSMulV", 0>; 1050defm "" : LMULReadAdvance<"ReadVSMulX", 0>; 1051defm "" : LMULReadAdvance<"ReadVSShiftV", 0>; 1052defm "" : LMULReadAdvance<"ReadVSShiftX", 0>; 1053defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>; 1054defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>; 1055 1056// 13. Vector Floating-Point Instructions 1057defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>; 1058defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>; 1059defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>; 1060defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>; 1061defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>; 1062defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>; 1063defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>; 1064defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>; 1065defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>; 1066defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>; 1067defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>; 1068defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>; 1069defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>; 1070defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>; 1071defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>; 1072defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>; 1073defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>; 1074defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>; 1075defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>; 1076defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>; 1077defm "" : LMULReadAdvance<"ReadVFCmpV", 0>; 1078defm "" : LMULReadAdvance<"ReadVFCmpF", 0>; 1079defm "" : LMULReadAdvance<"ReadVFClassV", 0>; 1080defm "" : LMULReadAdvance<"ReadVFMergeV", 0>; 1081defm "" : LMULReadAdvance<"ReadVFMergeF", 0>; 1082defm "" : LMULReadAdvance<"ReadVFMovF", 0>; 1083defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>; 1084defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>; 1085defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>; 1086defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>; 1087defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>; 1088defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>; 1089defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>; 1090defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>; 1091 1092// 14. Vector Reduction Operations 1093def : ReadAdvance<ReadVIRedV, 0>; 1094def : ReadAdvance<ReadVIRedV0, 0>; 1095def : ReadAdvance<ReadVIWRedV, 0>; 1096def : ReadAdvance<ReadVIWRedV0, 0>; 1097def : ReadAdvance<ReadVFRedV, 0>; 1098def : ReadAdvance<ReadVFRedV0, 0>; 1099def : ReadAdvance<ReadVFRedOV, 0>; 1100def : ReadAdvance<ReadVFRedOV0, 0>; 1101def : ReadAdvance<ReadVFRedMinMaxV, 0>; 1102def : ReadAdvance<ReadVFWRedV, 0>; 1103def : ReadAdvance<ReadVFWRedV0, 0>; 1104def : ReadAdvance<ReadVFWRedOV, 0>; 1105def : ReadAdvance<ReadVFWRedOV0, 0>; 1106 1107// 15. Vector Mask Instructions 1108defm "" : LMULReadAdvance<"ReadVMALUV", 0>; 1109defm "" : LMULReadAdvance<"ReadVMPopV", 0>; 1110defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; 1111defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; 1112defm "" : LMULReadAdvance<"ReadVIotaV", 0>; 1113 1114// 16. Vector Permutation Instructions 1115def : ReadAdvance<ReadVMovXS, 0>; 1116def : ReadAdvance<ReadVMovSX_V, 0>; 1117def : ReadAdvance<ReadVMovSX_X, 0>; 1118def : ReadAdvance<ReadVMovFS, 0>; 1119def : ReadAdvance<ReadVMovSF_V, 0>; 1120def : ReadAdvance<ReadVMovSF_F, 0>; 1121defm "" : LMULReadAdvance<"ReadVISlideV", 0>; 1122defm "" : LMULReadAdvance<"ReadVISlideX", 0>; 1123defm "" : LMULReadAdvance<"ReadVFSlideV", 0>; 1124defm "" : LMULReadAdvance<"ReadVFSlideF", 0>; 1125defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>; 1126defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>; 1127defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>; 1128defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>; 1129defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>; 1130defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>; 1131defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>; 1132defm "" : LMULReadAdvance<"ReadVGatherV", 0>; 1133defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>; 1134// These are already LMUL aware 1135def : ReadAdvance<ReadVMov1V, 0>; 1136def : ReadAdvance<ReadVMov2V, 0>; 1137def : ReadAdvance<ReadVMov4V, 0>; 1138def : ReadAdvance<ReadVMov8V, 0>; 1139 1140// Others 1141def : ReadAdvance<ReadVMask, 0>; 1142def : ReadAdvance<ReadVMergeOp_WorstCase, 0>; 1143foreach mx = SchedMxList in { 1144 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>; 1145 foreach sew = SchedSEWSet<mx>.val in 1146 def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>; 1147} 1148 1149} // Unsupported 1150} // UnsupportedSchedV 1151