xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVScheduleV.td (revision 5b56413d04e608379c9a306373554a8e4d321bc0) 
1//===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10/// Define scheduler resources associated with def operands.
11
12defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
13// Used for widening and narrowing instructions as it doesn't contain M8.
14defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
15// Used for widening reductions, which does contain M8.
16defvar SchedMxListWRed = SchedMxList;
17defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
18// Used for floating-point as it doesn't contain MF8.
19defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
20// Used for widening floating-point Reduction as it doesn't contain MF8.
21defvar SchedMxListFWRed = SchedMxListF;
22
23class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
24  assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
25  defvar t = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
26                   !eq(mx, "M2"):  [8, 16, 32, 64],
27                   !eq(mx, "M4"):  [8, 16, 32, 64],
28                   !eq(mx, "M8"):  [8, 16, 32, 64],
29                   !eq(mx, "MF2"): [8, 16, 32],
30                   !eq(mx, "MF4"): [8, 16],
31                   !eq(mx, "MF8"): [8]);
32  // For floating-point instructions, SEW won't be 8.
33  defvar remove8 = !if(isF, !listremove(t, [8]), t);
34  // For widening instructions, SEW will not be 64.
35  defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8);
36  list<int> val = remove64;
37}
38
39// Helper function to get the largest LMUL from MxList
40// Precondition: MxList is sorted in ascending LMUL order.
41class LargestLMUL<list<string> MxList> {
42  // MX list is sorted from smallest to largest
43  string r = !foldl(!head(MxList), MxList, last, curr, curr);
44}
45// Helper function to get the smallest SEW that can be used with LMUL mx
46// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>
47class SmallestSEW<string mx, bit isF = 0> {
48  int r = !head(SchedSEWSet<mx, isF>.val);
49}
50
51// Creates WriteRes for (name, mx, resources) tuple
52multiclass LMULWriteResMX<string name, list<ProcResourceKind> resources,
53                          string mx, bit IsWorstCase> {
54  def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
55  if IsWorstCase then
56    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
57}
58multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
59                             string mx, int sew,  bit IsWorstCase> {
60  def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
61  if IsWorstCase then
62    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
63}
64
65// Define a SchedAlias for the SchedWrite associated with (name, mx) whose
66// behavior is aliased to a Variant. The Variant has Latency predLad and
67// ReleaseAtCycles predCycles if the SchedPredicate Pred is true, otherwise has
68// Latency noPredLat and ReleaseAtCycles noPredCycles. The WorstCase SchedWrite
69// is created similiarly if IsWorstCase is true.
70multiclass LMULWriteResMXVariant<string name, SchedPredicateBase Pred,
71                                 list<ProcResourceKind> resources,
72                                 int predLat, list<int> predAcquireCycles,
73                                 list<int> predReleaseCycles, int noPredLat,
74                                 list<int> noPredAcquireCycles,
75                                 list<int> noPredReleaseCycles,
76                                 string mx, bit IsWorstCase> {
77  defvar nameMX = name # "_" # mx;
78
79  // Define the different behaviors
80  def nameMX # "_Pred" : SchedWriteRes<resources>{
81    let Latency = predLat;
82    let AcquireAtCycles = predAcquireCycles;
83    let ReleaseAtCycles = predReleaseCycles;
84  }
85  def nameMX # "_NoPred" : SchedWriteRes<resources> {
86    let Latency = noPredLat;
87    let AcquireAtCycles = noPredAcquireCycles;
88    let ReleaseAtCycles = noPredReleaseCycles;
89  }
90
91  // Tie behavior to predicate
92  def NAME # nameMX # "_Variant" : SchedWriteVariant<[
93    SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>,
94    SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX # "_NoPred")]>
95  ]>;
96  def : SchedAlias<
97    !cast<SchedReadWrite>(nameMX),
98    !cast<SchedReadWrite>(NAME # nameMX # "_Variant")>;
99
100  if IsWorstCase then {
101    def NAME # name # "_WorstCase_Variant" : SchedWriteVariant<[
102      SchedVar<Pred, [!cast<SchedWriteRes>(NAME # nameMX # "_Pred")]>,
103      SchedVar<NoSchedPred, [!cast<SchedWriteRes>(NAME # nameMX # "_NoPred")]>
104    ]>;
105    def : SchedAlias<
106      !cast<SchedReadWrite>(name # "_WorstCase"),
107      !cast<SchedReadWrite>(NAME # name # "_WorstCase_Variant")>;
108  }
109}
110
111// Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
112// ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
113// SchedMxList variants above. Each multiclass is responsible for defining
114// a record that represents the WorseCase behavior for name.
115multiclass LMULSchedWritesImpl<string name, list<string> MxList> {
116  def name # "_WorstCase" : SchedWrite;
117  foreach mx = MxList in {
118    def name # "_" # mx : SchedWrite;
119  }
120}
121multiclass LMULSchedReadsImpl<string name, list<string> MxList> {
122  def name # "_WorstCase" : SchedRead;
123  foreach mx = MxList in {
124    def name # "_" # mx : SchedRead;
125  }
126}
127multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> {
128  if !exists<SchedWrite>(name # "_WorstCase") then
129    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
130  foreach mx = SchedMxList in {
131    if !exists<SchedWrite>(name # "_" # mx) then
132      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
133  }
134}
135multiclass LMULReadAdvanceImpl<string name, int val,
136                               list<SchedWrite> writes = []> {
137  if !exists<SchedRead>(name # "_WorstCase") then
138    def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
139  foreach mx = SchedMxList in {
140    if !exists<SchedRead>(name # "_" # mx) then
141      def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
142  }
143}
144
145// Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
146// ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
147// SchedMxList variants above. Each multiclass is responsible for defining
148// a record that represents the WorseCase behavior for name.
149multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0,
150                                  bit isWidening = 0> {
151  def name # "_WorstCase" : SchedWrite;
152  foreach mx = MxList in {
153    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
154      def name # "_" # mx # "_E" # sew : SchedWrite;
155  }
156}
157multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0,
158                                 bit isWidening = 0> {
159  def name # "_WorstCase" : SchedRead;
160  foreach mx = MxList in {
161    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
162      def name # "_" # mx # "_E" # sew : SchedRead;
163  }
164}
165multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
166                               list<string> MxList, bit isF = 0,
167                               bit isWidening = 0> {
168  if !exists<SchedWrite>(name # "_WorstCase") then
169    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
170  foreach mx = MxList in {
171    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
172      if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then
173        def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
174  }
175}
176multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
177                                  list<string> MxList, bit isF = 0,
178                                  bit isWidening = 0> {
179  if !exists<SchedRead>(name # "_WorstCase") then
180    def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
181  foreach mx = MxList in {
182    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
183      if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then
184        def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
185  }
186}
187// Define classes to define list containing all SchedWrites for each (name, LMUL)
188// pair for each LMUL in each of the SchedMxList variants above and name in
189// argument `names`. These classes can be used to construct a list of existing
190// definitions of writes corresponding to each (name, LMUL) pair, that are needed
191// by the ReadAdvance. For example:
192// ```
193//   defm "" : LMULReadAdvance<"ReadVIALUX", 1,
194//                             LMULSchedWriteList<["WriteVIMovVX"]>.value>;
195// ```
196class LMULSchedWriteListImpl<list<string> names, list<string> MxList> {
197  list<SchedWrite> value = !foldl([]<SchedWrite>,
198                                  !foreach(name, names,
199                                    !foreach(mx, MxList, !cast<SchedWrite>(name # "_" # mx))),
200                                  all, writes, !listconcat(all, writes));
201}
202
203multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;
204multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;
205multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>
206  : LMULWriteResImpl<name, resources>;
207multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
208  : LMULReadAdvanceImpl<name, val, writes>;
209class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
210
211multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>;
212multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>;
213multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources>
214  : LMULSEWWriteResImpl<name, resources, SchedMxList>;
215multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []>
216  : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxList>;
217
218multiclass LMULSEWSchedWritesWRed<string name>
219    : LMULSEWSchedWritesImpl<name, SchedMxListWRed, isWidening=1>;
220multiclass LMULSEWWriteResWRed<string name, list<ProcResourceKind> resources>
221    : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, isWidening=1>;
222
223multiclass LMULSEWSchedWritesFWRed<string name>
224    : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, isF=1, isWidening=1>;
225multiclass LMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources>
226    : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>;
227
228multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, isF=1>;
229multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, isF=1>;
230multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources>
231  : LMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>;
232multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>
233  : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>;
234
235multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
236multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
237multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
238  : LMULWriteResImpl<name, resources>;
239multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
240  : LMULReadAdvanceImpl<name, val, writes>;
241class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
242
243multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;
244multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;
245multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>
246  : LMULWriteResImpl<name, resources>;
247multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
248  : LMULReadAdvanceImpl<name, val, writes>;
249class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;
250
251// 3.6 Vector Byte Length vlenb
252def WriteRdVLENB      : SchedWrite;
253
254// 6. Configuration-Setting Instructions
255def WriteVSETVLI      : SchedWrite;
256def WriteVSETIVLI     : SchedWrite;
257def WriteVSETVL       : SchedWrite;
258
259// 7. Vector Loads and Stores
260// 7.4. Vector Unit-Stride Instructions
261defm "" : LMULSchedWrites<"WriteVLDE">;
262defm "" : LMULSchedWrites<"WriteVSTE">;
263// 7.4.1. Vector Unit-Strided Mask
264defm "" : LMULSchedWrites<"WriteVLDM">;
265defm "" : LMULSchedWrites<"WriteVSTM">;
266// 7.5. Vector Strided Instructions
267defm "" : LMULSchedWrites<"WriteVLDS8">;
268defm "" : LMULSchedWrites<"WriteVLDS16">;
269defm "" : LMULSchedWrites<"WriteVLDS32">;
270defm "" : LMULSchedWrites<"WriteVLDS64">;
271defm "" : LMULSchedWrites<"WriteVSTS8">;
272defm "" : LMULSchedWrites<"WriteVSTS16">;
273defm "" : LMULSchedWrites<"WriteVSTS32">;
274defm "" : LMULSchedWrites<"WriteVSTS64">;
275// 7.6. Vector Indexed Instructions
276defm "" : LMULSchedWrites<"WriteVLDUX8">;
277defm "" : LMULSchedWrites<"WriteVLDUX16">;
278defm "" : LMULSchedWrites<"WriteVLDUX32">;
279defm "" : LMULSchedWrites<"WriteVLDUX64">;
280defm "" : LMULSchedWrites<"WriteVLDOX8">;
281defm "" : LMULSchedWrites<"WriteVLDOX16">;
282defm "" : LMULSchedWrites<"WriteVLDOX32">;
283defm "" : LMULSchedWrites<"WriteVLDOX64">;
284defm "" : LMULSchedWrites<"WriteVSTUX8">;
285defm "" : LMULSchedWrites<"WriteVSTUX16">;
286defm "" : LMULSchedWrites<"WriteVSTUX32">;
287defm "" : LMULSchedWrites<"WriteVSTUX64">;
288defm "" : LMULSchedWrites<"WriteVSTOX8">;
289defm "" : LMULSchedWrites<"WriteVSTOX16">;
290defm "" : LMULSchedWrites<"WriteVSTOX32">;
291defm "" : LMULSchedWrites<"WriteVSTOX64">;
292// 7.7. Vector Unit-stride Fault-Only-First Loads
293defm "" : LMULSchedWrites<"WriteVLDFF">;
294// 7.8. Vector Segment Instructions
295foreach nf=2-8 in {
296  foreach eew = [8, 16, 32, 64] in {
297    defm "" : LMULSchedWrites<"WriteVLSEG" # nf # e # eew>;
298    defm "" : LMULSchedWrites<"WriteVSSEG" # nf # e # eew>;
299    defm "" : LMULSchedWrites<"WriteVLSEGFF" # nf # e # eew>;
300    defm "" : LMULSchedWrites<"WriteVLSSEG" # nf # e # eew>;
301    defm "" : LMULSchedWrites<"WriteVSSSEG" # nf # e # eew>;
302    defm "" : LMULSchedWrites<"WriteVLUXSEG" # nf # e # eew>;
303    defm "" : LMULSchedWrites<"WriteVLOXSEG" # nf # e # eew>;
304    defm "" : LMULSchedWrites<"WriteVSUXSEG" # nf # e # eew>;
305    defm "" : LMULSchedWrites<"WriteVSOXSEG" # nf # e # eew>;
306  }
307}
308// 7.9. Vector Whole Register Instructions
309def WriteVLD1R        : SchedWrite;
310def WriteVLD2R        : SchedWrite;
311def WriteVLD4R        : SchedWrite;
312def WriteVLD8R        : SchedWrite;
313def WriteVST1R        : SchedWrite;
314def WriteVST2R        : SchedWrite;
315def WriteVST4R        : SchedWrite;
316def WriteVST8R        : SchedWrite;
317
318// 11. Vector Integer Arithmetic Instructions
319// 11.1. Vector Single-Width Integer Add and Subtract
320// 11.5. Vector Bitwise Logical Instructions
321defm "" : LMULSchedWrites<"WriteVIALUV">;
322defm "" : LMULSchedWrites<"WriteVIALUX">;
323defm "" : LMULSchedWrites<"WriteVIALUI">;
324// 11.2. Vector Widening Integer Add/Subtract
325defm "" : LMULSchedWritesW<"WriteVIWALUV">;
326defm "" : LMULSchedWritesW<"WriteVIWALUX">;
327defm "" : LMULSchedWritesW<"WriteVIWALUI">;
328// 11.3. Vector Integer Extension
329defm "" : LMULSchedWrites<"WriteVExtV">;
330// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
331defm "" : LMULSchedWrites<"WriteVICALUV">;
332defm "" : LMULSchedWrites<"WriteVICALUX">;
333defm "" : LMULSchedWrites<"WriteVICALUI">;
334// 11.6. Vector Single-Width Bit Shift Instructions
335defm "" : LMULSchedWrites<"WriteVShiftV">;
336defm "" : LMULSchedWrites<"WriteVShiftX">;
337defm "" : LMULSchedWrites<"WriteVShiftI">;
338// 11.7. Vector Narrowing Integer Right Shift Instructions
339defm "" : LMULSchedWritesW<"WriteVNShiftV">;
340defm "" : LMULSchedWritesW<"WriteVNShiftX">;
341defm "" : LMULSchedWritesW<"WriteVNShiftI">;
342// 11.8. Vector Integer Comparison Instructions
343defm "" : LMULSchedWrites<"WriteVICmpV">;
344defm "" : LMULSchedWrites<"WriteVICmpX">;
345defm "" : LMULSchedWrites<"WriteVICmpI">;
346// 11.9. Vector Integer Min/Max Instructions
347defm "" : LMULSchedWrites<"WriteVIMinMaxV">;
348defm "" : LMULSchedWrites<"WriteVIMinMaxX">;
349// 11.10. Vector Single-Width Integer Multiply Instructions
350defm "" : LMULSchedWrites<"WriteVIMulV">;
351defm "" : LMULSchedWrites<"WriteVIMulX">;
352// 11.11. Vector Integer Divide Instructions
353defm "" : LMULSEWSchedWrites<"WriteVIDivV">;
354defm "" : LMULSEWSchedWrites<"WriteVIDivX">;
355// 11.12. Vector Widening Integer Multiply Instructions
356defm "" : LMULSchedWritesW<"WriteVIWMulV">;
357defm "" : LMULSchedWritesW<"WriteVIWMulX">;
358// 11.13. Vector Single-Width Integer Multiply-Add Instructions
359defm "" : LMULSchedWrites<"WriteVIMulAddV">;
360defm "" : LMULSchedWrites<"WriteVIMulAddX">;
361// 11.14. Vector Widening Integer Multiply-Add Instructions
362defm "" : LMULSchedWritesW<"WriteVIWMulAddV">;
363defm "" : LMULSchedWritesW<"WriteVIWMulAddX">;
364// 11.15. Vector Integer Merge Instructions
365defm "" : LMULSchedWrites<"WriteVIMergeV">;
366defm "" : LMULSchedWrites<"WriteVIMergeX">;
367defm "" : LMULSchedWrites<"WriteVIMergeI">;
368// 11.16. Vector Integer Move Instructions
369defm "" : LMULSchedWrites<"WriteVIMovV">;
370defm "" : LMULSchedWrites<"WriteVIMovX">;
371defm "" : LMULSchedWrites<"WriteVIMovI">;
372
373// 12. Vector Fixed-Point Arithmetic Instructions
374// 12.1. Vector Single-Width Saturating Add and Subtract
375defm "" : LMULSchedWrites<"WriteVSALUV">;
376defm "" : LMULSchedWrites<"WriteVSALUX">;
377defm "" : LMULSchedWrites<"WriteVSALUI">;
378// 12.2. Vector Single-Width Averaging Add and Subtract
379defm "" : LMULSchedWrites<"WriteVAALUV">;
380defm "" : LMULSchedWrites<"WriteVAALUX">;
381// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
382defm "" : LMULSchedWrites<"WriteVSMulV">;
383defm "" : LMULSchedWrites<"WriteVSMulX">;
384// 12.4. Vector Single-Width Scaling Shift Instructions
385defm "" : LMULSchedWrites<"WriteVSShiftV">;
386defm "" : LMULSchedWrites<"WriteVSShiftX">;
387defm "" : LMULSchedWrites<"WriteVSShiftI">;
388// 12.5. Vector Narrowing Fixed-Point Clip Instructions
389defm "" : LMULSchedWritesW<"WriteVNClipV">;
390defm "" : LMULSchedWritesW<"WriteVNClipX">;
391defm "" : LMULSchedWritesW<"WriteVNClipI">;
392
393// 13. Vector Floating-Point Instructions
394// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
395defm "" : LMULSchedWrites<"WriteVFALUV">;
396defm "" : LMULSchedWrites<"WriteVFALUF">;
397// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
398defm "" : LMULSchedWritesFW<"WriteVFWALUV">;
399defm "" : LMULSchedWritesFW<"WriteVFWALUF">;
400// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
401defm "" : LMULSchedWrites<"WriteVFMulV">;
402defm "" : LMULSchedWrites<"WriteVFMulF">;
403defm "" : LMULSEWSchedWritesF<"WriteVFDivV">;
404defm "" : LMULSEWSchedWritesF<"WriteVFDivF">;
405// 13.5. Vector Widening Floating-Point Multiply
406defm "" : LMULSchedWritesFW<"WriteVFWMulV">;
407defm "" : LMULSchedWritesFW<"WriteVFWMulF">;
408// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
409defm "" : LMULSchedWrites<"WriteVFMulAddV">;
410defm "" : LMULSchedWrites<"WriteVFMulAddF">;
411// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
412defm "" : LMULSchedWritesFW<"WriteVFWMulAddV">;
413defm "" : LMULSchedWritesFW<"WriteVFWMulAddF">;
414// 13.8. Vector Floating-Point Square-Root Instruction
415defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">;
416// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
417// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
418defm "" : LMULSchedWrites<"WriteVFRecpV">;
419// 13.11. Vector Floating-Point MIN/MAX Instructions
420defm "" : LMULSchedWrites<"WriteVFMinMaxV">;
421defm "" : LMULSchedWrites<"WriteVFMinMaxF">;
422// 13.12. Vector Floating-Point Sign-Injection Instructions
423defm "" : LMULSchedWrites<"WriteVFSgnjV">;
424defm "" : LMULSchedWrites<"WriteVFSgnjF">;
425// 13.13. Vector Floating-Point Compare Instructions
426defm "" : LMULSchedWrites<"WriteVFCmpV">;
427defm "" : LMULSchedWrites<"WriteVFCmpF">;
428// 13.14. Vector Floating-Point Classify Instruction
429defm "" : LMULSchedWrites<"WriteVFClassV">;
430// 13.15. Vector Floating-Point Merge Instruction
431defm "" : LMULSchedWrites<"WriteVFMergeV">;
432// 13.16. Vector Floating-Point Move Instruction
433defm "" : LMULSchedWrites<"WriteVFMovV">;
434// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
435defm "" : LMULSchedWrites<"WriteVFCvtIToFV">;
436defm "" : LMULSchedWrites<"WriteVFCvtFToIV">;
437// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
438defm "" : LMULSchedWritesW<"WriteVFWCvtIToFV">;
439defm "" : LMULSchedWritesFW<"WriteVFWCvtFToIV">;
440defm "" : LMULSchedWritesFW<"WriteVFWCvtFToFV">;
441// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
442defm "" : LMULSchedWritesFW<"WriteVFNCvtIToFV">;
443defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">;
444defm "" : LMULSchedWritesFW<"WriteVFNCvtFToFV">;
445
446// 14. Vector Reduction Operations
447// The latency of reduction is determined by the size of the read resource.
448// The LMUL range of read resource(VS2) for reduction operantion is between
449// MF8 and M8. Use the _From suffix to indicate the number of the
450// LMUL from VS2.
451// 14.1. Vector Single-Width Integer Reduction Instructions
452defm "" : LMULSEWSchedWrites<"WriteVIRedV_From">;
453defm "" : LMULSEWSchedWrites<"WriteVIRedMinMaxV_From">;
454// 14.2. Vector Widening Integer Reduction Instructions
455defm "" : LMULSEWSchedWritesWRed<"WriteVIWRedV_From">;
456// 14.3. Vector Single-Width Floating-Point Reduction Instructions
457defm "" : LMULSEWSchedWritesF<"WriteVFRedV_From">;
458defm "" : LMULSEWSchedWritesF<"WriteVFRedOV_From">;
459defm "" : LMULSEWSchedWritesF<"WriteVFRedMinMaxV_From">;
460// 14.4. Vector Widening Floating-Point Reduction Instructions
461defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedV_From">;
462defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedOV_From">;
463
464// 15. Vector Mask Instructions
465// 15.1. Vector Mask-Register Logical Instructions
466defm "" : LMULSchedWrites<"WriteVMALUV">;
467// 15.2. Vector Mask Population Count
468defm "" : LMULSchedWrites<"WriteVMPopV">;
469// 15.3. Vector Find-First-Set Mask Bit
470defm "" : LMULSchedWrites<"WriteVMFFSV">;
471// 15.4. Vector Set-Before-First Mask Bit
472// 15.5. Vector Set-Including-First Mask Bit
473// 15.6. Vector Set-only-First Mask Bit
474defm "" : LMULSchedWrites<"WriteVMSFSV">;
475// 15.8. Vector Iota Instruction
476defm "" : LMULSchedWrites<"WriteVMIotV">;
477// 15.9. Vector Element Index Instruction
478defm "" : LMULSchedWrites<"WriteVMIdxV">;
479
480// 16. Vector Permutation Instructions
481// 16.1. Integer Scalar Move Instructions
482def WriteVIMovVX : SchedWrite;
483def WriteVIMovXV : SchedWrite;
484// 16.2. Floating-Point Scalar Move Instructions
485def WriteVFMovVF : SchedWrite;
486def WriteVFMovFV : SchedWrite;
487// 16.3. Vector Slide Instructions
488defm "" : LMULSchedWrites<"WriteVISlideX">;
489defm "" : LMULSchedWrites<"WriteVISlideI">;
490defm "" : LMULSchedWrites<"WriteVISlide1X">;
491defm "" : LMULSchedWrites<"WriteVFSlide1F">;
492// 16.4. Vector Register Gather Instructions
493defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
494defm "" : LMULSchedWrites<"WriteVRGatherVX">;
495defm "" : LMULSchedWrites<"WriteVRGatherVI">;
496// 16.5. Vector Compress Instruction
497defm "" : LMULSEWSchedWrites<"WriteVCompressV">;
498// 16.6. Whole Vector Register Move
499// These are already LMUL aware
500def WriteVMov1V       : SchedWrite;
501def WriteVMov2V       : SchedWrite;
502def WriteVMov4V       : SchedWrite;
503def WriteVMov8V       : SchedWrite;
504
505//===----------------------------------------------------------------------===//
506/// Define scheduler resources associated with use operands.
507
508// 6. Configuration-Setting Instructions
509def ReadVSETVLI       : SchedRead;
510def ReadVSETVL        : SchedRead;
511
512// 7. Vector Loads and Stores
513def ReadVLDX : SchedRead;
514def ReadVSTX : SchedRead;
515// 7.4. Vector Unit-Stride Instructions
516defm "" : LMULSchedReads<"ReadVSTEV">;
517// 7.4.1. Vector Unit-Strided Mask
518defm "" : LMULSchedReads<"ReadVSTM">;
519// 7.5. Vector Strided Instructions
520def ReadVLDSX : SchedRead;
521def ReadVSTSX : SchedRead;
522defm "" : LMULSchedReads<"ReadVSTS8V">;
523defm "" : LMULSchedReads<"ReadVSTS16V">;
524defm "" : LMULSchedReads<"ReadVSTS32V">;
525defm "" : LMULSchedReads<"ReadVSTS64V">;
526// 7.6. Vector Indexed Instructions
527defm "" : LMULSchedReads<"ReadVLDUXV">;
528defm "" : LMULSchedReads<"ReadVLDOXV">;
529defm "" : LMULSchedReads<"ReadVSTUX8">;
530defm "" : LMULSchedReads<"ReadVSTUX16">;
531defm "" : LMULSchedReads<"ReadVSTUX32">;
532defm "" : LMULSchedReads<"ReadVSTUX64">;
533defm "" : LMULSchedReads<"ReadVSTUXV">;
534defm "" : LMULSchedReads<"ReadVSTUX8V">;
535defm "" : LMULSchedReads<"ReadVSTUX16V">;
536defm "" : LMULSchedReads<"ReadVSTUX32V">;
537defm "" : LMULSchedReads<"ReadVSTUX64V">;
538defm "" : LMULSchedReads<"ReadVSTOX8">;
539defm "" : LMULSchedReads<"ReadVSTOX16">;
540defm "" : LMULSchedReads<"ReadVSTOX32">;
541defm "" : LMULSchedReads<"ReadVSTOX64">;
542defm "" : LMULSchedReads<"ReadVSTOXV">;
543defm "" : LMULSchedReads<"ReadVSTOX8V">;
544defm "" : LMULSchedReads<"ReadVSTOX16V">;
545defm "" : LMULSchedReads<"ReadVSTOX32V">;
546defm "" : LMULSchedReads<"ReadVSTOX64V">;
547// 7.9. Vector Whole Register Instructions
548// These are already LMUL aware
549def ReadVST1R         : SchedRead;
550def ReadVST2R         : SchedRead;
551def ReadVST4R         : SchedRead;
552def ReadVST8R         : SchedRead;
553
554// 11. Vector Integer Arithmetic Instructions
555// 11.1. Vector Single-Width Integer Add and Subtract
556// 11.5. Vector Bitwise Logical Instructions
557defm "" : LMULSchedReads<"ReadVIALUV">;
558defm "" : LMULSchedReads<"ReadVIALUX">;
559// 11.2. Vector Widening Integer Add/Subtract
560defm "" : LMULSchedReadsW<"ReadVIWALUV">;
561defm "" : LMULSchedReadsW<"ReadVIWALUX">;
562// 11.3. Vector Integer Extension
563defm "" : LMULSchedReads<"ReadVExtV">;
564// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
565defm "" : LMULSchedReads<"ReadVICALUV">;
566defm "" : LMULSchedReads<"ReadVICALUX">;
567// 11.6. Vector Single-Width Bit Shift Instructions
568defm "" : LMULSchedReads<"ReadVShiftV">;
569defm "" : LMULSchedReads<"ReadVShiftX">;
570// 11.7. Vector Narrowing Integer Right Shift Instructions
571defm "" : LMULSchedReadsW<"ReadVNShiftV">;
572defm "" : LMULSchedReadsW<"ReadVNShiftX">;
573// 11.8. Vector Integer Comparison Instructions
574defm "" : LMULSchedReads<"ReadVICmpV">;
575defm "" : LMULSchedReads<"ReadVICmpX">;
576// 11.9. Vector Integer Min/Max Instructions
577defm "" : LMULSchedReads<"ReadVIMinMaxV">;
578defm "" : LMULSchedReads<"ReadVIMinMaxX">;
579// 11.10. Vector Single-Width Integer Multiply Instructions
580defm "" : LMULSchedReads<"ReadVIMulV">;
581defm "" : LMULSchedReads<"ReadVIMulX">;
582// 11.11. Vector Integer Divide Instructions
583defm "" : LMULSEWSchedReads<"ReadVIDivV">;
584defm "" : LMULSEWSchedReads<"ReadVIDivX">;
585// 11.12. Vector Widening Integer Multiply Instructions
586defm "" : LMULSchedReadsW<"ReadVIWMulV">;
587defm "" : LMULSchedReadsW<"ReadVIWMulX">;
588// 11.13. Vector Single-Width Integer Multiply-Add Instructions
589defm "" : LMULSchedReads<"ReadVIMulAddV">;
590defm "" : LMULSchedReads<"ReadVIMulAddX">;
591// 11.14. Vector Widening Integer Multiply-Add Instructions
592defm "" : LMULSchedReadsW<"ReadVIWMulAddV">;
593defm "" : LMULSchedReadsW<"ReadVIWMulAddX">;
594// 11.15. Vector Integer Merge Instructions
595defm "" : LMULSchedReads<"ReadVIMergeV">;
596defm "" : LMULSchedReads<"ReadVIMergeX">;
597// 11.16. Vector Integer Move Instructions
598defm "" : LMULSchedReads<"ReadVIMovV">;
599defm "" : LMULSchedReads<"ReadVIMovX">;
600
601// 12. Vector Fixed-Point Arithmetic Instructions
602// 12.1. Vector Single-Width Saturating Add and Subtract
603defm "" : LMULSchedReads<"ReadVSALUV">;
604defm "" : LMULSchedReads<"ReadVSALUX">;
605// 12.2. Vector Single-Width Averaging Add and Subtract
606defm "" : LMULSchedReads<"ReadVAALUV">;
607defm "" : LMULSchedReads<"ReadVAALUX">;
608// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
609defm "" : LMULSchedReads<"ReadVSMulV">;
610defm "" : LMULSchedReads<"ReadVSMulX">;
611// 12.4. Vector Single-Width Scaling Shift Instructions
612defm "" : LMULSchedReads<"ReadVSShiftV">;
613defm "" : LMULSchedReads<"ReadVSShiftX">;
614// 12.5. Vector Narrowing Fixed-Point Clip Instructions
615defm "" : LMULSchedReadsW<"ReadVNClipV">;
616defm "" : LMULSchedReadsW<"ReadVNClipX">;
617
618// 13. Vector Floating-Point Instructions
619// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
620defm "" : LMULSchedReads<"ReadVFALUV">;
621defm "" : LMULSchedReads<"ReadVFALUF">;
622// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
623defm "" : LMULSchedReadsFW<"ReadVFWALUV">;
624defm "" : LMULSchedReadsFW<"ReadVFWALUF">;
625// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
626defm "" : LMULSchedReads<"ReadVFMulV">;
627defm "" : LMULSchedReads<"ReadVFMulF">;
628defm "" : LMULSEWSchedReadsF<"ReadVFDivV">;
629defm "" : LMULSEWSchedReadsF<"ReadVFDivF">;
630// 13.5. Vector Widening Floating-Point Multiply
631defm "" : LMULSchedReadsFW<"ReadVFWMulV">;
632defm "" : LMULSchedReadsFW<"ReadVFWMulF">;
633// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
634defm "" : LMULSchedReads<"ReadVFMulAddV">;
635defm "" : LMULSchedReads<"ReadVFMulAddF">;
636// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
637defm "" : LMULSchedReadsFW<"ReadVFWMulAddV">;
638defm "" : LMULSchedReadsFW<"ReadVFWMulAddF">;
639// 13.8. Vector Floating-Point Square-Root Instruction
640defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">;
641// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
642// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
643defm "" : LMULSchedReads<"ReadVFRecpV">;
644// 13.11. Vector Floating-Point MIN/MAX Instructions
645defm "" : LMULSchedReads<"ReadVFMinMaxV">;
646defm "" : LMULSchedReads<"ReadVFMinMaxF">;
647// 13.12. Vector Floating-Point Sign-Injection Instructions
648defm "" : LMULSchedReads<"ReadVFSgnjV">;
649defm "" : LMULSchedReads<"ReadVFSgnjF">;
650// 13.13. Vector Floating-Point Compare Instructions
651defm "" : LMULSchedReads<"ReadVFCmpV">;
652defm "" : LMULSchedReads<"ReadVFCmpF">;
653// 13.14. Vector Floating-Point Classify Instruction
654defm "" : LMULSchedReads<"ReadVFClassV">;
655// 13.15. Vector Floating-Point Merge Instruction
656defm "" : LMULSchedReads<"ReadVFMergeV">;
657defm "" : LMULSchedReads<"ReadVFMergeF">;
658// 13.16. Vector Floating-Point Move Instruction
659defm "" : LMULSchedReads<"ReadVFMovF">;
660// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
661defm "" : LMULSchedReads<"ReadVFCvtIToFV">;
662defm "" : LMULSchedReads<"ReadVFCvtFToIV">;
663// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
664defm "" : LMULSchedReadsW<"ReadVFWCvtIToFV">;
665defm "" : LMULSchedReadsFW<"ReadVFWCvtFToIV">;
666defm "" : LMULSchedReadsFW<"ReadVFWCvtFToFV">;
667// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
668defm "" : LMULSchedReadsFW<"ReadVFNCvtIToFV">;
669defm "" : LMULSchedReadsW<"ReadVFNCvtFToIV">;
670defm "" : LMULSchedReadsFW<"ReadVFNCvtFToFV">;
671
672// 14. Vector Reduction Operations
673// 14.1. Vector Single-Width Integer Reduction Instructions
674def ReadVIRedV        : SchedRead;
675def ReadVIRedV0       : SchedRead;
676// 14.2. Vector Widening Integer Reduction Instructions
677def ReadVIWRedV       : SchedRead;
678def ReadVIWRedV0      : SchedRead;
679// 14.3. Vector Single-Width Floating-Point Reduction Instructions
680def ReadVFRedV        : SchedRead;
681def ReadVFRedV0       : SchedRead;
682def ReadVFRedOV       : SchedRead;
683def ReadVFRedOV0      : SchedRead;
684def ReadVFRedMinMaxV  : SchedRead;
685// 14.4. Vector Widening Floating-Point Reduction Instructions
686def ReadVFWRedV       : SchedRead;
687def ReadVFWRedV0      : SchedRead;
688def ReadVFWRedOV      : SchedRead;
689def ReadVFWRedOV0     : SchedRead;
690
691// 15. Vector Mask Instructions
692// 15.1. Vector Mask-Register Logical Instructions
693defm "" : LMULSchedReads<"ReadVMALUV">;
694// 15.2. Vector Mask Population Count
695defm "" : LMULSchedReads<"ReadVMPopV">;
696// 15.3. Vector Find-First-Set Mask Bit
697defm "" : LMULSchedReads<"ReadVMFFSV">;
698// 15.4. Vector Set-Before-First Mask Bit
699// 15.5. Vector Set-Including-First Mask Bit
700// 15.6. Vector Set-only-First Mask Bit
701defm "" : LMULSchedReads<"ReadVMSFSV">;
702// 15.8. Vector Iota Instruction
703defm "" : LMULSchedReads<"ReadVMIotV">;
704
705// 16. Vector Permutation Instructions
706// 16.1. Integer Scalar Move Instructions
707def ReadVIMovVX : SchedRead;
708def ReadVIMovXV : SchedRead;
709def ReadVIMovXX : SchedRead;
710// 16.2. Floating-Point Scalar Move Instructions
711def ReadVFMovVF : SchedRead;
712def ReadVFMovFV : SchedRead;
713def ReadVFMovFX : SchedRead;
714// 16.3. Vector Slide Instructions
715defm "" : LMULSchedReads<"ReadVISlideV">;
716defm "" : LMULSchedReads<"ReadVISlideX">;
717defm "" : LMULSchedReads<"ReadVFSlideV">;
718defm "" : LMULSchedReads<"ReadVFSlideF">;
719// 16.4. Vector Register Gather Instructions
720defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">;
721defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">;
722defm "" : LMULSchedReads<"ReadVRGatherVX_data">;
723defm "" : LMULSchedReads<"ReadVRGatherVX_index">;
724defm "" : LMULSchedReads<"ReadVRGatherVI_data">;
725// 16.5. Vector Compress Instruction
726defm "" : LMULSEWSchedReads<"ReadVCompressV">;
727// 16.6. Whole Vector Register Move
728// These are already LMUL aware
729def ReadVMov1V        : SchedRead;
730def ReadVMov2V        : SchedRead;
731def ReadVMov4V        : SchedRead;
732def ReadVMov8V        : SchedRead;
733
734// Others
735def ReadVMask         : SchedRead;
736def ReadVMergeOp_WorstCase : SchedRead;
737foreach mx = SchedMxList in {
738  def ReadVMergeOp_ # mx : SchedRead;
739  foreach sew = SchedSEWSet<mx>.val in
740    def ReadVMergeOp_ # mx  # "_E" # sew : SchedRead;
741}
742
743//===----------------------------------------------------------------------===//
744/// Define default scheduler resources for V.
745
746multiclass UnsupportedSchedV {
747let Unsupported = true in {
748
749// 3.6 Vector Byte Length vlenb
750def : WriteRes<WriteRdVLENB, []>;
751
752// 6. Configuration-Setting Instructions
753def : WriteRes<WriteVSETVLI, []>;
754def : WriteRes<WriteVSETIVLI, []>;
755def : WriteRes<WriteVSETVL, []>;
756
757// 7. Vector Loads and Stores
758defm "" : LMULWriteRes<"WriteVLDE", []>;
759defm "" : LMULWriteRes<"WriteVSTE", []>;
760defm "" : LMULWriteRes<"WriteVLDM", []>;
761defm "" : LMULWriteRes<"WriteVSTM", []>;
762defm "" : LMULWriteRes<"WriteVLDS8", []>;
763defm "" : LMULWriteRes<"WriteVLDS16", []>;
764defm "" : LMULWriteRes<"WriteVLDS32", []>;
765defm "" : LMULWriteRes<"WriteVLDS64", []>;
766defm "" : LMULWriteRes<"WriteVSTS8", []>;
767defm "" : LMULWriteRes<"WriteVSTS16", []>;
768defm "" : LMULWriteRes<"WriteVSTS32", []>;
769defm "" : LMULWriteRes<"WriteVSTS64", []>;
770defm "" : LMULWriteRes<"WriteVLDUX8", []>;
771defm "" : LMULWriteRes<"WriteVLDUX16", []>;
772defm "" : LMULWriteRes<"WriteVLDUX32", []>;
773defm "" : LMULWriteRes<"WriteVLDUX64", []>;
774defm "" : LMULWriteRes<"WriteVLDOX8", []>;
775defm "" : LMULWriteRes<"WriteVLDOX16", []>;
776defm "" : LMULWriteRes<"WriteVLDOX32", []>;
777defm "" : LMULWriteRes<"WriteVLDOX64", []>;
778defm "" : LMULWriteRes<"WriteVSTUX8", []>;
779defm "" : LMULWriteRes<"WriteVSTUX16", []>;
780defm "" : LMULWriteRes<"WriteVSTUX32", []>;
781defm "" : LMULWriteRes<"WriteVSTUX64", []>;
782defm "" : LMULWriteRes<"WriteVSTOX8", []>;
783defm "" : LMULWriteRes<"WriteVSTOX16", []>;
784defm "" : LMULWriteRes<"WriteVSTOX32", []>;
785defm "" : LMULWriteRes<"WriteVSTOX64", []>;
786defm "" : LMULWriteRes<"WriteVLDFF", []>;
787// These are already LMUL aware
788def : WriteRes<WriteVLD1R, []>;
789def : WriteRes<WriteVLD2R, []>;
790def : WriteRes<WriteVLD4R, []>;
791def : WriteRes<WriteVLD8R, []>;
792def : WriteRes<WriteVST1R, []>;
793def : WriteRes<WriteVST2R, []>;
794def : WriteRes<WriteVST4R, []>;
795def : WriteRes<WriteVST8R, []>;
796// Vector Segment Loads and Stores
797foreach nf=2-8 in {
798  foreach eew = [8, 16, 32, 64] in {
799    defm "" : LMULWriteRes <"WriteVLSEG" # nf # "e" # eew, []>;
800    defm "" : LMULWriteRes <"WriteVLSEGFF" # nf # "e" # eew, []>;
801    defm "" : LMULWriteRes <"WriteVSSEG" # nf # "e" # eew, []>;
802    defm "" : LMULWriteRes <"WriteVLSSEG" # nf # "e" # eew, []>;
803    defm "" : LMULWriteRes <"WriteVSSSEG" # nf # "e" # eew, []>;
804    defm "" : LMULWriteRes <"WriteVLUXSEG" # nf # "e" # eew, []>;
805    defm "" : LMULWriteRes <"WriteVLOXSEG" # nf # "e" # eew, []>;
806    defm "" : LMULWriteRes <"WriteVSUXSEG" # nf # "e" # eew, []>;
807    defm "" : LMULWriteRes <"WriteVSOXSEG" # nf # "e" # eew, []>;
808  }
809}
810
811// 11. Vector Integer Arithmetic Instructions
812defm "" : LMULWriteRes<"WriteVIALUV", []>;
813defm "" : LMULWriteRes<"WriteVIALUX", []>;
814defm "" : LMULWriteRes<"WriteVIALUI", []>;
815defm "" : LMULWriteResW<"WriteVIWALUV", []>;
816defm "" : LMULWriteResW<"WriteVIWALUX", []>;
817defm "" : LMULWriteResW<"WriteVIWALUI", []>;
818defm "" : LMULWriteRes<"WriteVExtV", []>;
819defm "" : LMULWriteRes<"WriteVICALUV", []>;
820defm "" : LMULWriteRes<"WriteVICALUX", []>;
821defm "" : LMULWriteRes<"WriteVICALUI", []>;
822defm "" : LMULWriteRes<"WriteVShiftV", []>;
823defm "" : LMULWriteRes<"WriteVShiftX", []>;
824defm "" : LMULWriteRes<"WriteVShiftI", []>;
825defm "" : LMULWriteResW<"WriteVNShiftV", []>;
826defm "" : LMULWriteResW<"WriteVNShiftX", []>;
827defm "" : LMULWriteResW<"WriteVNShiftI", []>;
828defm "" : LMULWriteRes<"WriteVICmpV", []>;
829defm "" : LMULWriteRes<"WriteVICmpX", []>;
830defm "" : LMULWriteRes<"WriteVICmpI", []>;
831defm "" : LMULWriteRes<"WriteVIMinMaxV", []>;
832defm "" : LMULWriteRes<"WriteVIMinMaxX", []>;
833defm "" : LMULWriteRes<"WriteVIMulV", []>;
834defm "" : LMULWriteRes<"WriteVIMulX", []>;
835defm "" : LMULSEWWriteRes<"WriteVIDivV", []>;
836defm "" : LMULSEWWriteRes<"WriteVIDivX", []>;
837defm "" : LMULWriteResW<"WriteVIWMulV", []>;
838defm "" : LMULWriteResW<"WriteVIWMulX", []>;
839defm "" : LMULWriteRes<"WriteVIMulAddV", []>;
840defm "" : LMULWriteRes<"WriteVIMulAddX", []>;
841defm "" : LMULWriteResW<"WriteVIWMulAddV", []>;
842defm "" : LMULWriteResW<"WriteVIWMulAddX", []>;
843defm "" : LMULWriteRes<"WriteVIMergeV", []>;
844defm "" : LMULWriteRes<"WriteVIMergeX", []>;
845defm "" : LMULWriteRes<"WriteVIMergeI", []>;
846defm "" : LMULWriteRes<"WriteVIMovV", []>;
847defm "" : LMULWriteRes<"WriteVIMovX", []>;
848defm "" : LMULWriteRes<"WriteVIMovI", []>;
849
850// 12. Vector Fixed-Point Arithmetic Instructions
851defm "" : LMULWriteRes<"WriteVSALUV", []>;
852defm "" : LMULWriteRes<"WriteVSALUX", []>;
853defm "" : LMULWriteRes<"WriteVSALUI", []>;
854defm "" : LMULWriteRes<"WriteVAALUV", []>;
855defm "" : LMULWriteRes<"WriteVAALUX", []>;
856defm "" : LMULWriteRes<"WriteVSMulV", []>;
857defm "" : LMULWriteRes<"WriteVSMulX", []>;
858defm "" : LMULWriteRes<"WriteVSShiftV", []>;
859defm "" : LMULWriteRes<"WriteVSShiftX", []>;
860defm "" : LMULWriteRes<"WriteVSShiftI", []>;
861defm "" : LMULWriteResW<"WriteVNClipV", []>;
862defm "" : LMULWriteResW<"WriteVNClipX", []>;
863defm "" : LMULWriteResW<"WriteVNClipI", []>;
864
865// 13. Vector Floating-Point Instructions
866defm "" : LMULWriteRes<"WriteVFALUV", []>;
867defm "" : LMULWriteRes<"WriteVFALUF", []>;
868defm "" : LMULWriteResFW<"WriteVFWALUV", []>;
869defm "" : LMULWriteResFW<"WriteVFWALUF", []>;
870defm "" : LMULWriteRes<"WriteVFMulV", []>;
871defm "" : LMULWriteRes<"WriteVFMulF", []>;
872defm "" : LMULSEWWriteResF<"WriteVFDivV", []>;
873defm "" : LMULSEWWriteResF<"WriteVFDivF", []>;
874defm "" : LMULWriteResFW<"WriteVFWMulV", []>;
875defm "" : LMULWriteResFW<"WriteVFWMulF", []>;
876defm "" : LMULWriteRes<"WriteVFMulAddV", []>;
877defm "" : LMULWriteRes<"WriteVFMulAddF", []>;
878defm "" : LMULWriteResFW<"WriteVFWMulAddV", []>;
879defm "" : LMULWriteResFW<"WriteVFWMulAddF", []>;
880defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>;
881defm "" : LMULWriteRes<"WriteVFRecpV", []>;
882defm "" : LMULWriteRes<"WriteVFMinMaxV", []>;
883defm "" : LMULWriteRes<"WriteVFMinMaxF", []>;
884defm "" : LMULWriteRes<"WriteVFSgnjV", []>;
885defm "" : LMULWriteRes<"WriteVFSgnjF", []>;
886defm "" : LMULWriteRes<"WriteVFCmpV", []>;
887defm "" : LMULWriteRes<"WriteVFCmpF", []>;
888defm "" : LMULWriteRes<"WriteVFClassV", []>;
889defm "" : LMULWriteRes<"WriteVFMergeV", []>;
890defm "" : LMULWriteRes<"WriteVFMovV", []>;
891defm "" : LMULWriteRes<"WriteVFCvtIToFV", []>;
892defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>;
893defm "" : LMULWriteResW<"WriteVFWCvtIToFV", []>;
894defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>;
895defm "" : LMULWriteResFW<"WriteVFWCvtFToFV", []>;
896defm "" : LMULWriteResFW<"WriteVFNCvtIToFV", []>;
897defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>;
898defm "" : LMULWriteResFW<"WriteVFNCvtFToFV", []>;
899
900// 14. Vector Reduction Operations
901defm "" : LMULSEWWriteRes<"WriteVIRedV_From", []>;
902defm "" : LMULSEWWriteRes<"WriteVIRedMinMaxV_From", []>;
903defm "" : LMULSEWWriteResWRed<"WriteVIWRedV_From", []>;
904defm "" : LMULSEWWriteResF<"WriteVFRedV_From", []>;
905defm "" : LMULSEWWriteResF<"WriteVFRedOV_From", []>;
906defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>;
907defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", []>;
908defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>;
909
910// 15. Vector Mask Instructions
911defm "" : LMULWriteRes<"WriteVMALUV", []>;
912defm "" : LMULWriteRes<"WriteVMPopV", []>;
913defm "" : LMULWriteRes<"WriteVMFFSV", []>;
914defm "" : LMULWriteRes<"WriteVMSFSV", []>;
915defm "" : LMULWriteRes<"WriteVMIotV", []>;
916defm "" : LMULWriteRes<"WriteVMIdxV", []>;
917
918// 16. Vector Permutation Instructions
919def : WriteRes<WriteVIMovVX, []>;
920def : WriteRes<WriteVIMovXV, []>;
921def : WriteRes<WriteVFMovVF, []>;
922def : WriteRes<WriteVFMovFV, []>;
923defm "" : LMULWriteRes<"WriteVISlideX", []>;
924defm "" : LMULWriteRes<"WriteVISlideI", []>;
925defm "" : LMULWriteRes<"WriteVISlide1X", []>;
926defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
927defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
928defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
929defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
930defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;
931// These are already LMUL aware
932def : WriteRes<WriteVMov1V, []>;
933def : WriteRes<WriteVMov2V, []>;
934def : WriteRes<WriteVMov4V, []>;
935def : WriteRes<WriteVMov8V, []>;
936
937// 6. Configuration-Setting Instructions
938def : ReadAdvance<ReadVSETVLI, 0>;
939def : ReadAdvance<ReadVSETVL, 0>;
940
941// 7. Vector Loads and Stores
942def : ReadAdvance<ReadVLDX, 0>;
943def : ReadAdvance<ReadVSTX, 0>;
944defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
945defm "" : LMULReadAdvance<"ReadVSTM", 0>;
946def : ReadAdvance<ReadVLDSX, 0>;
947def : ReadAdvance<ReadVSTSX, 0>;
948defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
949defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
950defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
951defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
952defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
953defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
954defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
955defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
956defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
957defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
958defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
959defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
960defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
961defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
962defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
963defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
964defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
965defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
966defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
967defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
968defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
969defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
970defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
971defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
972// These are already LMUL aware
973def : ReadAdvance<ReadVST1R, 0>;
974def : ReadAdvance<ReadVST2R, 0>;
975def : ReadAdvance<ReadVST4R, 0>;
976def : ReadAdvance<ReadVST8R, 0>;
977
978// 11. Vector Integer Arithmetic Instructions
979defm "" : LMULReadAdvance<"ReadVIALUV", 0>;
980defm "" : LMULReadAdvance<"ReadVIALUX", 0>;
981defm "" : LMULReadAdvanceW<"ReadVIWALUV", 0>;
982defm "" : LMULReadAdvanceW<"ReadVIWALUX", 0>;
983defm "" : LMULReadAdvance<"ReadVExtV", 0>;
984defm "" : LMULReadAdvance<"ReadVICALUV", 0>;
985defm "" : LMULReadAdvance<"ReadVICALUX", 0>;
986defm "" : LMULReadAdvance<"ReadVShiftV", 0>;
987defm "" : LMULReadAdvance<"ReadVShiftX", 0>;
988defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>;
989defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>;
990defm "" : LMULReadAdvance<"ReadVICmpV", 0>;
991defm "" : LMULReadAdvance<"ReadVICmpX", 0>;
992defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>;
993defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>;
994defm "" : LMULReadAdvance<"ReadVIMulV", 0>;
995defm "" : LMULReadAdvance<"ReadVIMulX", 0>;
996defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>;
997defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>;
998defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>;
999defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>;
1000defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;
1001defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>;
1002defm "" : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
1003defm "" : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
1004defm "" : LMULReadAdvance<"ReadVIMergeV", 0>;
1005defm "" : LMULReadAdvance<"ReadVIMergeX", 0>;
1006defm "" : LMULReadAdvance<"ReadVIMovV", 0>;
1007defm "" : LMULReadAdvance<"ReadVIMovX", 0>;
1008
1009// 12. Vector Fixed-Point Arithmetic Instructions
1010defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
1011defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
1012defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
1013defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
1014defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
1015defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
1016defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
1017defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
1018defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
1019defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
1020
1021// 13. Vector Floating-Point Instructions
1022defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
1023defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
1024defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
1025defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
1026defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
1027defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
1028defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
1029defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
1030defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
1031defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
1032defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
1033defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>;
1034defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>;
1035defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>;
1036defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
1037defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
1038defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;
1039defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>;
1040defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;
1041defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>;
1042defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
1043defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
1044defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
1045defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
1046defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
1047defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
1048defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
1049defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
1050defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
1051defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
1052defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
1053defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
1054defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
1055defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
1056
1057// 14. Vector Reduction Operations
1058def : ReadAdvance<ReadVIRedV, 0>;
1059def : ReadAdvance<ReadVIRedV0, 0>;
1060def : ReadAdvance<ReadVIWRedV, 0>;
1061def : ReadAdvance<ReadVIWRedV0, 0>;
1062def : ReadAdvance<ReadVFRedV, 0>;
1063def : ReadAdvance<ReadVFRedV0, 0>;
1064def : ReadAdvance<ReadVFRedOV, 0>;
1065def : ReadAdvance<ReadVFRedOV0, 0>;
1066def : ReadAdvance<ReadVFRedMinMaxV, 0>;
1067def : ReadAdvance<ReadVFWRedV, 0>;
1068def : ReadAdvance<ReadVFWRedV0, 0>;
1069def : ReadAdvance<ReadVFWRedOV, 0>;
1070def : ReadAdvance<ReadVFWRedOV0, 0>;
1071
1072// 15. Vector Mask Instructions
1073defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
1074defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
1075defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
1076defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
1077defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
1078
1079// 16. Vector Permutation Instructions
1080def : ReadAdvance<ReadVIMovVX, 0>;
1081def : ReadAdvance<ReadVIMovXV, 0>;
1082def : ReadAdvance<ReadVIMovXX, 0>;
1083def : ReadAdvance<ReadVFMovVF, 0>;
1084def : ReadAdvance<ReadVFMovFV, 0>;
1085def : ReadAdvance<ReadVFMovFX, 0>;
1086defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
1087defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
1088defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
1089defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
1090defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
1091defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
1092defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
1093defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
1094defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
1095defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
1096defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
1097// These are already LMUL aware
1098def : ReadAdvance<ReadVMov1V, 0>;
1099def : ReadAdvance<ReadVMov2V, 0>;
1100def : ReadAdvance<ReadVMov4V, 0>;
1101def : ReadAdvance<ReadVMov8V, 0>;
1102
1103// Others
1104def : ReadAdvance<ReadVMask, 0>;
1105def : ReadAdvance<ReadVMergeOp_WorstCase, 0>;
1106foreach mx = SchedMxList in {
1107  def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx), 0>;
1108  foreach sew = SchedSEWSet<mx>.val in
1109    def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx  # "_E" # sew), 0>;
1110}
1111
1112} // Unsupported
1113} // UnsupportedSchedV
1114