xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVScheduleV.td (revision 02e9120893770924227138ba49df1edb3896112a) 
1//===- RISCVScheduleV.td - RISC-V Scheduling Definitions V -*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10/// Define scheduler resources associated with def operands.
11
12defvar SchedMxList = ["MF8", "MF4", "MF2", "M1", "M2", "M4", "M8"];
13// Used for widening and narrowing instructions as it doesn't contain M8.
14defvar SchedMxListW = !listremove(SchedMxList, ["M8"]);
15// Used for widening reductions, which does contain M8.
16defvar SchedMxListWRed = SchedMxList;
17defvar SchedMxListFW = !listremove(SchedMxList, ["M8", "MF8"]);
18// Used for floating-point as it doesn't contain MF8.
19defvar SchedMxListF = !listremove(SchedMxList, ["MF8"]);
20// Used for widening floating-point Reduction as it doesn't contain MF8.
21defvar SchedMxListFWRed = SchedMxListF;
22
23class SchedSEWSet<string mx, bit isF = 0, bit isWidening = 0> {
24  assert !or(!not(isF), !ne(mx, "MF8")), "LMUL shouldn't be MF8 for floating-point";
25  defvar t = !cond(!eq(mx, "M1"):  [8, 16, 32, 64],
26                   !eq(mx, "M2"):  [8, 16, 32, 64],
27                   !eq(mx, "M4"):  [8, 16, 32, 64],
28                   !eq(mx, "M8"):  [8, 16, 32, 64],
29                   !eq(mx, "MF2"): [8, 16, 32],
30                   !eq(mx, "MF4"): [8, 16],
31                   !eq(mx, "MF8"): [8]);
32  // For floating-point instructions, SEW won't be 8.
33  defvar remove8 = !if(isF, !listremove(t, [8]), t);
34  // For widening instructions, SEW will not be 64.
35  defvar remove64 = !if(isWidening, !listremove(remove8, [64]), remove8);
36  list<int> val = remove64;
37}
38
39// Helper function to get the largest LMUL from MxList
40// Precondition: MxList is sorted in ascending LMUL order.
41class LargestLMUL<list<string> MxList> {
42  // MX list is sorted from smallest to largest
43  string r = !foldl(!head(MxList), MxList, last, curr, curr);
44}
45// Helper function to get the smallest SEW that can be used with LMUL mx
46// Precondition: MxList is sorted in ascending LMUL order and SchedSEWSet<mx>
47class SmallestSEW<string mx, bit isF = 0> {
48  int r = !head(SchedSEWSet<mx, isF>.val);
49}
50
51// Creates WriteRes for (name, mx, resources) tuple
52multiclass LMULWriteResMX<string name, list<ProcResourceKind> resources,
53                          string mx, bit IsWorstCase> {
54  def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
55  if IsWorstCase then
56    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
57}
58multiclass LMULSEWWriteResMXSEW<string name, list<ProcResourceKind> resources,
59                             string mx, int sew,  bit IsWorstCase> {
60  def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
61  if IsWorstCase then
62    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
63}
64
65// Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
66// ReadAdvance for each (name, LMUL) pair and for each LMUL in each of the
67// SchedMxList variants above. Each multiclass is responsible for defining
68// a record that represents the WorseCase behavior for name.
69multiclass LMULSchedWritesImpl<string name, list<string> MxList> {
70  def name # "_WorstCase" : SchedWrite;
71  foreach mx = MxList in {
72    def name # "_" # mx : SchedWrite;
73  }
74}
75multiclass LMULSchedReadsImpl<string name, list<string> MxList> {
76  def name # "_WorstCase" : SchedRead;
77  foreach mx = MxList in {
78    def name # "_" # mx : SchedRead;
79  }
80}
81multiclass LMULWriteResImpl<string name, list<ProcResourceKind> resources> {
82  if !exists<SchedWrite>(name # "_WorstCase") then
83    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
84  foreach mx = SchedMxList in {
85    if !exists<SchedWrite>(name # "_" # mx) then
86      def : WriteRes<!cast<SchedWrite>(name # "_" # mx), resources>;
87  }
88}
89multiclass LMULReadAdvanceImpl<string name, int val,
90                               list<SchedWrite> writes = []> {
91  if !exists<SchedRead>(name # "_WorstCase") then
92    def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
93  foreach mx = SchedMxList in {
94    if !exists<SchedRead>(name # "_" # mx) then
95      def : ReadAdvance<!cast<SchedRead>(name # "_" # mx), val, writes>;
96  }
97}
98
99// Define multiclasses to define SchedWrite, SchedRead,  WriteRes, and
100// ReadAdvance for each (name, LMUL, SEW) tuple for each LMUL in each of the
101// SchedMxList variants above. Each multiclass is responsible for defining
102// a record that represents the WorseCase behavior for name.
103multiclass LMULSEWSchedWritesImpl<string name, list<string> MxList, bit isF = 0,
104                                  bit isWidening = 0> {
105  def name # "_WorstCase" : SchedWrite;
106  foreach mx = MxList in {
107    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
108      def name # "_" # mx # "_E" # sew : SchedWrite;
109  }
110}
111multiclass LMULSEWSchedReadsImpl<string name, list<string> MxList, bit isF = 0,
112                                 bit isWidening = 0> {
113  def name # "_WorstCase" : SchedRead;
114  foreach mx = MxList in {
115    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
116      def name # "_" # mx # "_E" # sew : SchedRead;
117  }
118}
119multiclass LMULSEWWriteResImpl<string name, list<ProcResourceKind> resources,
120                               list<string> MxList, bit isF = 0,
121                               bit isWidening = 0> {
122  if !exists<SchedWrite>(name # "_WorstCase") then
123    def : WriteRes<!cast<SchedWrite>(name # "_WorstCase"), resources>;
124  foreach mx = MxList in {
125    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
126      if !exists<SchedWrite>(name # "_" # mx # "_E" # sew) then
127        def : WriteRes<!cast<SchedWrite>(name # "_" # mx # "_E" # sew), resources>;
128  }
129}
130multiclass LMULSEWReadAdvanceImpl<string name, int val, list<SchedWrite> writes = [],
131                                  list<string> MxList, bit isF = 0,
132                                  bit isWidening = 0> {
133  if !exists<SchedRead>(name # "_WorstCase") then
134    def : ReadAdvance<!cast<SchedRead>(name # "_WorstCase"), val, writes>;
135  foreach mx = MxList in {
136    foreach sew = SchedSEWSet<mx, isF, isWidening>.val in
137      if !exists<SchedRead>(name # "_" # mx # "_E" # sew) then
138        def : ReadAdvance<!cast<SchedRead>(name # "_" # mx # "_E" # sew), val, writes>;
139  }
140}
141// Define classes to define list containing all SchedWrites for each (name, LMUL)
142// pair for each LMUL in each of the SchedMxList variants above and name in
143// argument `names`. These classes can be used to construct a list of existing
144// definitions of writes corresponding to each (name, LMUL) pair, that are needed
145// by the ReadAdvance. For example:
146// ```
147//   defm "" : LMULReadAdvance<"ReadVIALUX", 1,
148//                             LMULSchedWriteList<["WriteVIMovVX"]>.value>;
149// ```
150class LMULSchedWriteListImpl<list<string> names, list<string> MxList> {
151  list<SchedWrite> value = !foldl([]<SchedWrite>,
152                                  !foreach(name, names,
153                                    !foreach(mx, MxList, !cast<SchedWrite>(name # "_" # mx))),
154                                  all, writes, !listconcat(all, writes));
155}
156
157multiclass LMULSchedWrites<string name> : LMULSchedWritesImpl<name, SchedMxList>;
158multiclass LMULSchedReads<string name> : LMULSchedReadsImpl<name, SchedMxList>;
159multiclass LMULWriteRes<string name, list<ProcResourceKind> resources>
160  : LMULWriteResImpl<name, resources>;
161multiclass LMULReadAdvance<string name, int val, list<SchedWrite> writes = []>
162  : LMULReadAdvanceImpl<name, val, writes>;
163class LMULSchedWriteList<list<string> names> : LMULSchedWriteListImpl<names, SchedMxList>;
164
165multiclass LMULSEWSchedWrites<string name> : LMULSEWSchedWritesImpl<name, SchedMxList>;
166multiclass LMULSEWSchedReads<string name> : LMULSEWSchedReadsImpl<name, SchedMxList>;
167multiclass LMULSEWWriteRes<string name, list<ProcResourceKind> resources>
168  : LMULSEWWriteResImpl<name, resources, SchedMxList>;
169multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []>
170  : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxList>;
171
172multiclass LMULSEWSchedWritesWRed<string name>
173    : LMULSEWSchedWritesImpl<name, SchedMxListWRed, isWidening=1>;
174multiclass LMULSEWWriteResWRed<string name, list<ProcResourceKind> resources>
175    : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, isWidening=1>;
176
177multiclass LMULSEWSchedWritesFWRed<string name>
178    : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, isF=1, isWidening=1>;
179multiclass LMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources>
180    : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>;
181
182multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, isF=1>;
183multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, isF=1>;
184multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources>
185  : LMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>;
186multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>
187  : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>;
188
189multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
190multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
191multiclass LMULWriteResW<string name, list<ProcResourceKind> resources>
192  : LMULWriteResImpl<name, resources>;
193multiclass LMULReadAdvanceW<string name, int val, list<SchedWrite> writes = []>
194  : LMULReadAdvanceImpl<name, val, writes>;
195class LMULSchedWriteListW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListW>;
196
197multiclass LMULSchedWritesFW<string name> : LMULSchedWritesImpl<name, SchedMxListFW>;
198multiclass LMULSchedReadsFW<string name> : LMULSchedReadsImpl<name, SchedMxListFW>;
199multiclass LMULWriteResFW<string name, list<ProcResourceKind> resources>
200  : LMULWriteResImpl<name, resources>;
201multiclass LMULReadAdvanceFW<string name, int val, list<SchedWrite> writes = []>
202  : LMULReadAdvanceImpl<name, val, writes>;
203class LMULSchedWriteListFW<list<string> names> : LMULSchedWriteListImpl<names, SchedMxListFW>;
204
205// 3.6 Vector Byte Length vlenb
206def WriteRdVLENB      : SchedWrite;
207
208// 6. Configuration-Setting Instructions
209def WriteVSETVLI      : SchedWrite;
210def WriteVSETIVLI     : SchedWrite;
211def WriteVSETVL       : SchedWrite;
212
213// 7. Vector Loads and Stores
214// 7.4. Vector Unit-Stride Instructions
215defm "" : LMULSchedWrites<"WriteVLDE">;
216defm "" : LMULSchedWrites<"WriteVSTE">;
217// 7.4.1. Vector Unit-Strided Mask
218defm "" : LMULSchedWrites<"WriteVLDM">;
219defm "" : LMULSchedWrites<"WriteVSTM">;
220// 7.5. Vector Strided Instructions
221defm "" : LMULSchedWrites<"WriteVLDS8">;
222defm "" : LMULSchedWrites<"WriteVLDS16">;
223defm "" : LMULSchedWrites<"WriteVLDS32">;
224defm "" : LMULSchedWrites<"WriteVLDS64">;
225defm "" : LMULSchedWrites<"WriteVSTS8">;
226defm "" : LMULSchedWrites<"WriteVSTS16">;
227defm "" : LMULSchedWrites<"WriteVSTS32">;
228defm "" : LMULSchedWrites<"WriteVSTS64">;
229// 7.6. Vector Indexed Instructions
230defm "" : LMULSchedWrites<"WriteVLDUX8">;
231defm "" : LMULSchedWrites<"WriteVLDUX16">;
232defm "" : LMULSchedWrites<"WriteVLDUX32">;
233defm "" : LMULSchedWrites<"WriteVLDUX64">;
234defm "" : LMULSchedWrites<"WriteVLDOX8">;
235defm "" : LMULSchedWrites<"WriteVLDOX16">;
236defm "" : LMULSchedWrites<"WriteVLDOX32">;
237defm "" : LMULSchedWrites<"WriteVLDOX64">;
238defm "" : LMULSchedWrites<"WriteVSTUX8">;
239defm "" : LMULSchedWrites<"WriteVSTUX16">;
240defm "" : LMULSchedWrites<"WriteVSTUX32">;
241defm "" : LMULSchedWrites<"WriteVSTUX64">;
242defm "" : LMULSchedWrites<"WriteVSTOX8">;
243defm "" : LMULSchedWrites<"WriteVSTOX16">;
244defm "" : LMULSchedWrites<"WriteVSTOX32">;
245defm "" : LMULSchedWrites<"WriteVSTOX64">;
246// 7.7. Vector Unit-stride Fault-Only-First Loads
247defm "" : LMULSchedWrites<"WriteVLDFF">;
248// 7.8. Vector Segment Instructions
249foreach nf=2-8 in {
250  foreach eew = [8, 16, 32, 64] in {
251    defm "" : LMULSchedWrites<"WriteVLSEG" # nf # e # eew>;
252    defm "" : LMULSchedWrites<"WriteVSSEG" # nf # e # eew>;
253    defm "" : LMULSchedWrites<"WriteVLSEGFF" # nf # e # eew>;
254    defm "" : LMULSchedWrites<"WriteVLSSEG" # nf # e # eew>;
255    defm "" : LMULSchedWrites<"WriteVSSSEG" # nf # e # eew>;
256    defm "" : LMULSchedWrites<"WriteVLUXSEG" # nf # e # eew>;
257    defm "" : LMULSchedWrites<"WriteVLOXSEG" # nf # e # eew>;
258    defm "" : LMULSchedWrites<"WriteVSUXSEG" # nf # e # eew>;
259    defm "" : LMULSchedWrites<"WriteVSOXSEG" # nf # e # eew>;
260  }
261}
262// 7.9. Vector Whole Register Instructions
263def WriteVLD1R        : SchedWrite;
264def WriteVLD2R        : SchedWrite;
265def WriteVLD4R        : SchedWrite;
266def WriteVLD8R        : SchedWrite;
267def WriteVST1R        : SchedWrite;
268def WriteVST2R        : SchedWrite;
269def WriteVST4R        : SchedWrite;
270def WriteVST8R        : SchedWrite;
271
272// 11. Vector Integer Arithmetic Instructions
273// 11.1. Vector Single-Width Integer Add and Subtract
274// 11.5. Vector Bitwise Logical Instructions
275defm "" : LMULSchedWrites<"WriteVIALUV">;
276defm "" : LMULSchedWrites<"WriteVIALUX">;
277defm "" : LMULSchedWrites<"WriteVIALUI">;
278// 11.2. Vector Widening Integer Add/Subtract
279defm "" : LMULSchedWritesW<"WriteVIWALUV">;
280defm "" : LMULSchedWritesW<"WriteVIWALUX">;
281defm "" : LMULSchedWritesW<"WriteVIWALUI">;
282// 11.3. Vector Integer Extension
283defm "" : LMULSchedWrites<"WriteVExtV">;
284// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
285defm "" : LMULSchedWrites<"WriteVICALUV">;
286defm "" : LMULSchedWrites<"WriteVICALUX">;
287defm "" : LMULSchedWrites<"WriteVICALUI">;
288// 11.6. Vector Single-Width Bit Shift Instructions
289defm "" : LMULSchedWrites<"WriteVShiftV">;
290defm "" : LMULSchedWrites<"WriteVShiftX">;
291defm "" : LMULSchedWrites<"WriteVShiftI">;
292// 11.7. Vector Narrowing Integer Right Shift Instructions
293defm "" : LMULSchedWritesW<"WriteVNShiftV">;
294defm "" : LMULSchedWritesW<"WriteVNShiftX">;
295defm "" : LMULSchedWritesW<"WriteVNShiftI">;
296// 11.8. Vector Integer Comparison Instructions
297defm "" : LMULSchedWrites<"WriteVICmpV">;
298defm "" : LMULSchedWrites<"WriteVICmpX">;
299defm "" : LMULSchedWrites<"WriteVICmpI">;
300// 11.9. Vector Integer Min/Max Instructions
301defm "" : LMULSchedWrites<"WriteVIMinMaxV">;
302defm "" : LMULSchedWrites<"WriteVIMinMaxX">;
303// 11.10. Vector Single-Width Integer Multiply Instructions
304defm "" : LMULSchedWrites<"WriteVIMulV">;
305defm "" : LMULSchedWrites<"WriteVIMulX">;
306// 11.11. Vector Integer Divide Instructions
307defm "" : LMULSEWSchedWrites<"WriteVIDivV">;
308defm "" : LMULSEWSchedWrites<"WriteVIDivX">;
309// 11.12. Vector Widening Integer Multiply Instructions
310defm "" : LMULSchedWritesW<"WriteVIWMulV">;
311defm "" : LMULSchedWritesW<"WriteVIWMulX">;
312// 11.13. Vector Single-Width Integer Multiply-Add Instructions
313defm "" : LMULSchedWrites<"WriteVIMulAddV">;
314defm "" : LMULSchedWrites<"WriteVIMulAddX">;
315// 11.14. Vector Widening Integer Multiply-Add Instructions
316defm "" : LMULSchedWritesW<"WriteVIWMulAddV">;
317defm "" : LMULSchedWritesW<"WriteVIWMulAddX">;
318// 11.15. Vector Integer Merge Instructions
319defm "" : LMULSchedWrites<"WriteVIMergeV">;
320defm "" : LMULSchedWrites<"WriteVIMergeX">;
321defm "" : LMULSchedWrites<"WriteVIMergeI">;
322// 11.16. Vector Integer Move Instructions
323defm "" : LMULSchedWrites<"WriteVIMovV">;
324defm "" : LMULSchedWrites<"WriteVIMovX">;
325defm "" : LMULSchedWrites<"WriteVIMovI">;
326
327// 12. Vector Fixed-Point Arithmetic Instructions
328// 12.1. Vector Single-Width Saturating Add and Subtract
329defm "" : LMULSchedWrites<"WriteVSALUV">;
330defm "" : LMULSchedWrites<"WriteVSALUX">;
331defm "" : LMULSchedWrites<"WriteVSALUI">;
332// 12.2. Vector Single-Width Averaging Add and Subtract
333defm "" : LMULSchedWrites<"WriteVAALUV">;
334defm "" : LMULSchedWrites<"WriteVAALUX">;
335// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
336defm "" : LMULSchedWrites<"WriteVSMulV">;
337defm "" : LMULSchedWrites<"WriteVSMulX">;
338// 12.4. Vector Single-Width Scaling Shift Instructions
339defm "" : LMULSchedWrites<"WriteVSShiftV">;
340defm "" : LMULSchedWrites<"WriteVSShiftX">;
341defm "" : LMULSchedWrites<"WriteVSShiftI">;
342// 12.5. Vector Narrowing Fixed-Point Clip Instructions
343defm "" : LMULSchedWritesW<"WriteVNClipV">;
344defm "" : LMULSchedWritesW<"WriteVNClipX">;
345defm "" : LMULSchedWritesW<"WriteVNClipI">;
346
347// 13. Vector Floating-Point Instructions
348// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
349defm "" : LMULSchedWrites<"WriteVFALUV">;
350defm "" : LMULSchedWrites<"WriteVFALUF">;
351// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
352defm "" : LMULSchedWritesFW<"WriteVFWALUV">;
353defm "" : LMULSchedWritesFW<"WriteVFWALUF">;
354// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
355defm "" : LMULSchedWrites<"WriteVFMulV">;
356defm "" : LMULSchedWrites<"WriteVFMulF">;
357defm "" : LMULSEWSchedWritesF<"WriteVFDivV">;
358defm "" : LMULSEWSchedWritesF<"WriteVFDivF">;
359// 13.5. Vector Widening Floating-Point Multiply
360defm "" : LMULSchedWritesFW<"WriteVFWMulV">;
361defm "" : LMULSchedWritesFW<"WriteVFWMulF">;
362// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
363defm "" : LMULSchedWrites<"WriteVFMulAddV">;
364defm "" : LMULSchedWrites<"WriteVFMulAddF">;
365// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
366defm "" : LMULSchedWritesFW<"WriteVFWMulAddV">;
367defm "" : LMULSchedWritesFW<"WriteVFWMulAddF">;
368// 13.8. Vector Floating-Point Square-Root Instruction
369defm "" : LMULSEWSchedWritesF<"WriteVFSqrtV">;
370// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
371// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
372defm "" : LMULSchedWrites<"WriteVFRecpV">;
373// 13.11. Vector Floating-Point MIN/MAX Instructions
374defm "" : LMULSchedWrites<"WriteVFMinMaxV">;
375defm "" : LMULSchedWrites<"WriteVFMinMaxF">;
376// 13.12. Vector Floating-Point Sign-Injection Instructions
377defm "" : LMULSchedWrites<"WriteVFSgnjV">;
378defm "" : LMULSchedWrites<"WriteVFSgnjF">;
379// 13.13. Vector Floating-Point Compare Instructions
380defm "" : LMULSchedWrites<"WriteVFCmpV">;
381defm "" : LMULSchedWrites<"WriteVFCmpF">;
382// 13.14. Vector Floating-Point Classify Instruction
383defm "" : LMULSchedWrites<"WriteVFClassV">;
384// 13.15. Vector Floating-Point Merge Instruction
385defm "" : LMULSchedWrites<"WriteVFMergeV">;
386// 13.16. Vector Floating-Point Move Instruction
387defm "" : LMULSchedWrites<"WriteVFMovV">;
388// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
389defm "" : LMULSchedWrites<"WriteVFCvtIToFV">;
390defm "" : LMULSchedWrites<"WriteVFCvtFToIV">;
391// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
392defm "" : LMULSchedWritesW<"WriteVFWCvtIToFV">;
393defm "" : LMULSchedWritesFW<"WriteVFWCvtFToIV">;
394defm "" : LMULSchedWritesFW<"WriteVFWCvtFToFV">;
395// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
396defm "" : LMULSchedWritesFW<"WriteVFNCvtIToFV">;
397defm "" : LMULSchedWritesW<"WriteVFNCvtFToIV">;
398defm "" : LMULSchedWritesFW<"WriteVFNCvtFToFV">;
399
400// 14. Vector Reduction Operations
401// The latency of reduction is determined by the size of the read resource.
402// The LMUL range of read resource(VS2) for reduction operantion is between
403// MF8 and M8. Use the _From suffix to indicate the number of the
404// LMUL from VS2.
405// 14.1. Vector Single-Width Integer Reduction Instructions
406defm "" : LMULSEWSchedWrites<"WriteVIRedV_From">;
407defm "" : LMULSEWSchedWrites<"WriteVIRedMinMaxV_From">;
408// 14.2. Vector Widening Integer Reduction Instructions
409defm "" : LMULSEWSchedWritesWRed<"WriteVIWRedV_From">;
410// 14.3. Vector Single-Width Floating-Point Reduction Instructions
411defm "" : LMULSEWSchedWritesF<"WriteVFRedV_From">;
412defm "" : LMULSEWSchedWritesF<"WriteVFRedOV_From">;
413defm "" : LMULSEWSchedWritesF<"WriteVFRedMinMaxV_From">;
414// 14.4. Vector Widening Floating-Point Reduction Instructions
415defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedV_From">;
416defm "" : LMULSEWSchedWritesFWRed<"WriteVFWRedOV_From">;
417
418// 15. Vector Mask Instructions
419// 15.1. Vector Mask-Register Logical Instructions
420defm "" : LMULSchedWrites<"WriteVMALUV">;
421// 15.2. Vector Mask Population Count
422defm "" : LMULSchedWrites<"WriteVMPopV">;
423// 15.3. Vector Find-First-Set Mask Bit
424defm "" : LMULSchedWrites<"WriteVMFFSV">;
425// 15.4. Vector Set-Before-First Mask Bit
426// 15.5. Vector Set-Including-First Mask Bit
427// 15.6. Vector Set-only-First Mask Bit
428defm "" : LMULSchedWrites<"WriteVMSFSV">;
429// 15.8. Vector Iota Instruction
430defm "" : LMULSchedWrites<"WriteVMIotV">;
431// 15.9. Vector Element Index Instruction
432defm "" : LMULSchedWrites<"WriteVMIdxV">;
433
434// 16. Vector Permutation Instructions
435// 16.1. Integer Scalar Move Instructions
436def WriteVIMovVX : SchedWrite;
437def WriteVIMovXV : SchedWrite;
438// 16.2. Floating-Point Scalar Move Instructions
439def WriteVFMovVF : SchedWrite;
440def WriteVFMovFV : SchedWrite;
441// 16.3. Vector Slide Instructions
442defm "" : LMULSchedWrites<"WriteVISlideX">;
443defm "" : LMULSchedWrites<"WriteVISlideI">;
444defm "" : LMULSchedWrites<"WriteVISlide1X">;
445defm "" : LMULSchedWrites<"WriteVFSlide1F">;
446// 16.4. Vector Register Gather Instructions
447defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
448defm "" : LMULSchedWrites<"WriteVRGatherVX">;
449defm "" : LMULSchedWrites<"WriteVRGatherVI">;
450// 16.5. Vector Compress Instruction
451defm "" : LMULSEWSchedWrites<"WriteVCompressV">;
452// 16.6. Whole Vector Register Move
453// These are already LMUL aware
454def WriteVMov1V       : SchedWrite;
455def WriteVMov2V       : SchedWrite;
456def WriteVMov4V       : SchedWrite;
457def WriteVMov8V       : SchedWrite;
458
459//===----------------------------------------------------------------------===//
460/// Define scheduler resources associated with use operands.
461
462// 6. Configuration-Setting Instructions
463def ReadVSETVLI       : SchedRead;
464def ReadVSETVL        : SchedRead;
465
466// 7. Vector Loads and Stores
467def ReadVLDX : SchedRead;
468def ReadVSTX : SchedRead;
469// 7.4. Vector Unit-Stride Instructions
470defm "" : LMULSchedReads<"ReadVSTEV">;
471// 7.4.1. Vector Unit-Strided Mask
472defm "" : LMULSchedReads<"ReadVSTM">;
473// 7.5. Vector Strided Instructions
474def ReadVLDSX : SchedRead;
475def ReadVSTSX : SchedRead;
476defm "" : LMULSchedReads<"ReadVSTS8V">;
477defm "" : LMULSchedReads<"ReadVSTS16V">;
478defm "" : LMULSchedReads<"ReadVSTS32V">;
479defm "" : LMULSchedReads<"ReadVSTS64V">;
480// 7.6. Vector Indexed Instructions
481defm "" : LMULSchedReads<"ReadVLDUXV">;
482defm "" : LMULSchedReads<"ReadVLDOXV">;
483defm "" : LMULSchedReads<"ReadVSTUX8">;
484defm "" : LMULSchedReads<"ReadVSTUX16">;
485defm "" : LMULSchedReads<"ReadVSTUX32">;
486defm "" : LMULSchedReads<"ReadVSTUX64">;
487defm "" : LMULSchedReads<"ReadVSTUXV">;
488defm "" : LMULSchedReads<"ReadVSTUX8V">;
489defm "" : LMULSchedReads<"ReadVSTUX16V">;
490defm "" : LMULSchedReads<"ReadVSTUX32V">;
491defm "" : LMULSchedReads<"ReadVSTUX64V">;
492defm "" : LMULSchedReads<"ReadVSTOX8">;
493defm "" : LMULSchedReads<"ReadVSTOX16">;
494defm "" : LMULSchedReads<"ReadVSTOX32">;
495defm "" : LMULSchedReads<"ReadVSTOX64">;
496defm "" : LMULSchedReads<"ReadVSTOXV">;
497defm "" : LMULSchedReads<"ReadVSTOX8V">;
498defm "" : LMULSchedReads<"ReadVSTOX16V">;
499defm "" : LMULSchedReads<"ReadVSTOX32V">;
500defm "" : LMULSchedReads<"ReadVSTOX64V">;
501// 7.9. Vector Whole Register Instructions
502// These are already LMUL aware
503def ReadVST1R         : SchedRead;
504def ReadVST2R         : SchedRead;
505def ReadVST4R         : SchedRead;
506def ReadVST8R         : SchedRead;
507
508// 11. Vector Integer Arithmetic Instructions
509// 11.1. Vector Single-Width Integer Add and Subtract
510// 11.5. Vector Bitwise Logical Instructions
511defm "" : LMULSchedReads<"ReadVIALUV">;
512defm "" : LMULSchedReads<"ReadVIALUX">;
513// 11.2. Vector Widening Integer Add/Subtract
514defm "" : LMULSchedReadsW<"ReadVIWALUV">;
515defm "" : LMULSchedReadsW<"ReadVIWALUX">;
516// 11.3. Vector Integer Extension
517defm "" : LMULSchedReads<"ReadVExtV">;
518// 11.4. Vector Integer Arithmetic with Carry or Borrow Instructions
519defm "" : LMULSchedReads<"ReadVICALUV">;
520defm "" : LMULSchedReads<"ReadVICALUX">;
521// 11.6. Vector Single-Width Bit Shift Instructions
522defm "" : LMULSchedReads<"ReadVShiftV">;
523defm "" : LMULSchedReads<"ReadVShiftX">;
524// 11.7. Vector Narrowing Integer Right Shift Instructions
525defm "" : LMULSchedReadsW<"ReadVNShiftV">;
526defm "" : LMULSchedReadsW<"ReadVNShiftX">;
527// 11.8. Vector Integer Comparison Instructions
528defm "" : LMULSchedReads<"ReadVICmpV">;
529defm "" : LMULSchedReads<"ReadVICmpX">;
530// 11.9. Vector Integer Min/Max Instructions
531defm "" : LMULSchedReads<"ReadVIMinMaxV">;
532defm "" : LMULSchedReads<"ReadVIMinMaxX">;
533// 11.10. Vector Single-Width Integer Multiply Instructions
534defm "" : LMULSchedReads<"ReadVIMulV">;
535defm "" : LMULSchedReads<"ReadVIMulX">;
536// 11.11. Vector Integer Divide Instructions
537defm "" : LMULSEWSchedReads<"ReadVIDivV">;
538defm "" : LMULSEWSchedReads<"ReadVIDivX">;
539// 11.12. Vector Widening Integer Multiply Instructions
540defm "" : LMULSchedReadsW<"ReadVIWMulV">;
541defm "" : LMULSchedReadsW<"ReadVIWMulX">;
542// 11.13. Vector Single-Width Integer Multiply-Add Instructions
543defm "" : LMULSchedReads<"ReadVIMulAddV">;
544defm "" : LMULSchedReads<"ReadVIMulAddX">;
545// 11.14. Vector Widening Integer Multiply-Add Instructions
546defm "" : LMULSchedReadsW<"ReadVIWMulAddV">;
547defm "" : LMULSchedReadsW<"ReadVIWMulAddX">;
548// 11.15. Vector Integer Merge Instructions
549defm "" : LMULSchedReads<"ReadVIMergeV">;
550defm "" : LMULSchedReads<"ReadVIMergeX">;
551// 11.16. Vector Integer Move Instructions
552defm "" : LMULSchedReads<"ReadVIMovV">;
553defm "" : LMULSchedReads<"ReadVIMovX">;
554
555// 12. Vector Fixed-Point Arithmetic Instructions
556// 12.1. Vector Single-Width Saturating Add and Subtract
557defm "" : LMULSchedReads<"ReadVSALUV">;
558defm "" : LMULSchedReads<"ReadVSALUX">;
559// 12.2. Vector Single-Width Averaging Add and Subtract
560defm "" : LMULSchedReads<"ReadVAALUV">;
561defm "" : LMULSchedReads<"ReadVAALUX">;
562// 12.3. Vector Single-Width Fractional Multiply with Rounding and Saturation
563defm "" : LMULSchedReads<"ReadVSMulV">;
564defm "" : LMULSchedReads<"ReadVSMulX">;
565// 12.4. Vector Single-Width Scaling Shift Instructions
566defm "" : LMULSchedReads<"ReadVSShiftV">;
567defm "" : LMULSchedReads<"ReadVSShiftX">;
568// 12.5. Vector Narrowing Fixed-Point Clip Instructions
569defm "" : LMULSchedReadsW<"ReadVNClipV">;
570defm "" : LMULSchedReadsW<"ReadVNClipX">;
571
572// 13. Vector Floating-Point Instructions
573// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions
574defm "" : LMULSchedReads<"ReadVFALUV">;
575defm "" : LMULSchedReads<"ReadVFALUF">;
576// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
577defm "" : LMULSchedReadsFW<"ReadVFWALUV">;
578defm "" : LMULSchedReadsFW<"ReadVFWALUF">;
579// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
580defm "" : LMULSchedReads<"ReadVFMulV">;
581defm "" : LMULSchedReads<"ReadVFMulF">;
582defm "" : LMULSEWSchedReadsF<"ReadVFDivV">;
583defm "" : LMULSEWSchedReadsF<"ReadVFDivF">;
584// 13.5. Vector Widening Floating-Point Multiply
585defm "" : LMULSchedReadsFW<"ReadVFWMulV">;
586defm "" : LMULSchedReadsFW<"ReadVFWMulF">;
587// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
588defm "" : LMULSchedReads<"ReadVFMulAddV">;
589defm "" : LMULSchedReads<"ReadVFMulAddF">;
590// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
591defm "" : LMULSchedReadsFW<"ReadVFWMulAddV">;
592defm "" : LMULSchedReadsFW<"ReadVFWMulAddF">;
593// 13.8. Vector Floating-Point Square-Root Instruction
594defm "" : LMULSEWSchedReadsF<"ReadVFSqrtV">;
595// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
596// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
597defm "" : LMULSchedReads<"ReadVFRecpV">;
598// 13.11. Vector Floating-Point MIN/MAX Instructions
599defm "" : LMULSchedReads<"ReadVFMinMaxV">;
600defm "" : LMULSchedReads<"ReadVFMinMaxF">;
601// 13.12. Vector Floating-Point Sign-Injection Instructions
602defm "" : LMULSchedReads<"ReadVFSgnjV">;
603defm "" : LMULSchedReads<"ReadVFSgnjF">;
604// 13.13. Vector Floating-Point Compare Instructions
605defm "" : LMULSchedReads<"ReadVFCmpV">;
606defm "" : LMULSchedReads<"ReadVFCmpF">;
607// 13.14. Vector Floating-Point Classify Instruction
608defm "" : LMULSchedReads<"ReadVFClassV">;
609// 13.15. Vector Floating-Point Merge Instruction
610defm "" : LMULSchedReads<"ReadVFMergeV">;
611defm "" : LMULSchedReads<"ReadVFMergeF">;
612// 13.16. Vector Floating-Point Move Instruction
613defm "" : LMULSchedReads<"ReadVFMovF">;
614// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
615defm "" : LMULSchedReads<"ReadVFCvtIToFV">;
616defm "" : LMULSchedReads<"ReadVFCvtFToIV">;
617// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
618defm "" : LMULSchedReadsW<"ReadVFWCvtIToFV">;
619defm "" : LMULSchedReadsFW<"ReadVFWCvtFToIV">;
620defm "" : LMULSchedReadsFW<"ReadVFWCvtFToFV">;
621// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
622defm "" : LMULSchedReadsFW<"ReadVFNCvtIToFV">;
623defm "" : LMULSchedReadsW<"ReadVFNCvtFToIV">;
624defm "" : LMULSchedReadsFW<"ReadVFNCvtFToFV">;
625
626// 14. Vector Reduction Operations
627// 14.1. Vector Single-Width Integer Reduction Instructions
628def ReadVIRedV        : SchedRead;
629def ReadVIRedV0       : SchedRead;
630// 14.2. Vector Widening Integer Reduction Instructions
631def ReadVIWRedV       : SchedRead;
632def ReadVIWRedV0      : SchedRead;
633// 14.3. Vector Single-Width Floating-Point Reduction Instructions
634def ReadVFRedV        : SchedRead;
635def ReadVFRedV0       : SchedRead;
636def ReadVFRedOV       : SchedRead;
637def ReadVFRedOV0      : SchedRead;
638def ReadVFRedMinMaxV  : SchedRead;
639// 14.4. Vector Widening Floating-Point Reduction Instructions
640def ReadVFWRedV       : SchedRead;
641def ReadVFWRedV0      : SchedRead;
642def ReadVFWRedOV      : SchedRead;
643def ReadVFWRedOV0     : SchedRead;
644
645// 15. Vector Mask Instructions
646// 15.1. Vector Mask-Register Logical Instructions
647defm "" : LMULSchedReads<"ReadVMALUV">;
648// 15.2. Vector Mask Population Count
649defm "" : LMULSchedReads<"ReadVMPopV">;
650// 15.3. Vector Find-First-Set Mask Bit
651defm "" : LMULSchedReads<"ReadVMFFSV">;
652// 15.4. Vector Set-Before-First Mask Bit
653// 15.5. Vector Set-Including-First Mask Bit
654// 15.6. Vector Set-only-First Mask Bit
655defm "" : LMULSchedReads<"ReadVMSFSV">;
656// 15.8. Vector Iota Instruction
657defm "" : LMULSchedReads<"ReadVMIotV">;
658
659// 16. Vector Permutation Instructions
660// 16.1. Integer Scalar Move Instructions
661def ReadVIMovVX : SchedRead;
662def ReadVIMovXV : SchedRead;
663def ReadVIMovXX : SchedRead;
664// 16.2. Floating-Point Scalar Move Instructions
665def ReadVFMovVF : SchedRead;
666def ReadVFMovFV : SchedRead;
667def ReadVFMovFX : SchedRead;
668// 16.3. Vector Slide Instructions
669defm "" : LMULSchedReads<"ReadVISlideV">;
670defm "" : LMULSchedReads<"ReadVISlideX">;
671defm "" : LMULSchedReads<"ReadVFSlideV">;
672defm "" : LMULSchedReads<"ReadVFSlideF">;
673// 16.4. Vector Register Gather Instructions
674defm "" : LMULSEWSchedReads<"ReadVRGatherVV_data">;
675defm "" : LMULSEWSchedReads<"ReadVRGatherVV_index">;
676defm "" : LMULSchedReads<"ReadVRGatherVX_data">;
677defm "" : LMULSchedReads<"ReadVRGatherVX_index">;
678defm "" : LMULSchedReads<"ReadVRGatherVI_data">;
679// 16.5. Vector Compress Instruction
680defm "" : LMULSEWSchedReads<"ReadVCompressV">;
681// 16.6. Whole Vector Register Move
682// These are already LMUL aware
683def ReadVMov1V        : SchedRead;
684def ReadVMov2V        : SchedRead;
685def ReadVMov4V        : SchedRead;
686def ReadVMov8V        : SchedRead;
687
688// Others
689def ReadVMask         : SchedRead;
690
691//===----------------------------------------------------------------------===//
692/// Define default scheduler resources for V.
693
694multiclass UnsupportedSchedV {
695let Unsupported = true in {
696
697// 3.6 Vector Byte Length vlenb
698def : WriteRes<WriteRdVLENB, []>;
699
700// 6. Configuration-Setting Instructions
701def : WriteRes<WriteVSETVLI, []>;
702def : WriteRes<WriteVSETIVLI, []>;
703def : WriteRes<WriteVSETVL, []>;
704
705// 7. Vector Loads and Stores
706defm "" : LMULWriteRes<"WriteVLDE", []>;
707defm "" : LMULWriteRes<"WriteVSTE", []>;
708defm "" : LMULWriteRes<"WriteVLDM", []>;
709defm "" : LMULWriteRes<"WriteVSTM", []>;
710defm "" : LMULWriteRes<"WriteVLDS8", []>;
711defm "" : LMULWriteRes<"WriteVLDS16", []>;
712defm "" : LMULWriteRes<"WriteVLDS32", []>;
713defm "" : LMULWriteRes<"WriteVLDS64", []>;
714defm "" : LMULWriteRes<"WriteVSTS8", []>;
715defm "" : LMULWriteRes<"WriteVSTS16", []>;
716defm "" : LMULWriteRes<"WriteVSTS32", []>;
717defm "" : LMULWriteRes<"WriteVSTS64", []>;
718defm "" : LMULWriteRes<"WriteVLDUX8", []>;
719defm "" : LMULWriteRes<"WriteVLDUX16", []>;
720defm "" : LMULWriteRes<"WriteVLDUX32", []>;
721defm "" : LMULWriteRes<"WriteVLDUX64", []>;
722defm "" : LMULWriteRes<"WriteVLDOX8", []>;
723defm "" : LMULWriteRes<"WriteVLDOX16", []>;
724defm "" : LMULWriteRes<"WriteVLDOX32", []>;
725defm "" : LMULWriteRes<"WriteVLDOX64", []>;
726defm "" : LMULWriteRes<"WriteVSTUX8", []>;
727defm "" : LMULWriteRes<"WriteVSTUX16", []>;
728defm "" : LMULWriteRes<"WriteVSTUX32", []>;
729defm "" : LMULWriteRes<"WriteVSTUX64", []>;
730defm "" : LMULWriteRes<"WriteVSTOX8", []>;
731defm "" : LMULWriteRes<"WriteVSTOX16", []>;
732defm "" : LMULWriteRes<"WriteVSTOX32", []>;
733defm "" : LMULWriteRes<"WriteVSTOX64", []>;
734defm "" : LMULWriteRes<"WriteVLDFF", []>;
735// These are already LMUL aware
736def : WriteRes<WriteVLD1R, []>;
737def : WriteRes<WriteVLD2R, []>;
738def : WriteRes<WriteVLD4R, []>;
739def : WriteRes<WriteVLD8R, []>;
740def : WriteRes<WriteVST1R, []>;
741def : WriteRes<WriteVST2R, []>;
742def : WriteRes<WriteVST4R, []>;
743def : WriteRes<WriteVST8R, []>;
744// Vector Segment Loads and Stores
745foreach nf=2-8 in {
746  foreach eew = [8, 16, 32, 64] in {
747    defm "" : LMULWriteRes <"WriteVLSEG" # nf # "e" # eew, []>;
748    defm "" : LMULWriteRes <"WriteVLSEGFF" # nf # "e" # eew, []>;
749    defm "" : LMULWriteRes <"WriteVSSEG" # nf # "e" # eew, []>;
750    defm "" : LMULWriteRes <"WriteVLSSEG" # nf # "e" # eew, []>;
751    defm "" : LMULWriteRes <"WriteVSSSEG" # nf # "e" # eew, []>;
752    defm "" : LMULWriteRes <"WriteVLUXSEG" # nf # "e" # eew, []>;
753    defm "" : LMULWriteRes <"WriteVLOXSEG" # nf # "e" # eew, []>;
754    defm "" : LMULWriteRes <"WriteVSUXSEG" # nf # "e" # eew, []>;
755    defm "" : LMULWriteRes <"WriteVSOXSEG" # nf # "e" # eew, []>;
756  }
757}
758
759// 11. Vector Integer Arithmetic Instructions
760defm "" : LMULWriteRes<"WriteVIALUV", []>;
761defm "" : LMULWriteRes<"WriteVIALUX", []>;
762defm "" : LMULWriteRes<"WriteVIALUI", []>;
763defm "" : LMULWriteResW<"WriteVIWALUV", []>;
764defm "" : LMULWriteResW<"WriteVIWALUX", []>;
765defm "" : LMULWriteResW<"WriteVIWALUI", []>;
766defm "" : LMULWriteRes<"WriteVExtV", []>;
767defm "" : LMULWriteRes<"WriteVICALUV", []>;
768defm "" : LMULWriteRes<"WriteVICALUX", []>;
769defm "" : LMULWriteRes<"WriteVICALUI", []>;
770defm "" : LMULWriteRes<"WriteVShiftV", []>;
771defm "" : LMULWriteRes<"WriteVShiftX", []>;
772defm "" : LMULWriteRes<"WriteVShiftI", []>;
773defm "" : LMULWriteResW<"WriteVNShiftV", []>;
774defm "" : LMULWriteResW<"WriteVNShiftX", []>;
775defm "" : LMULWriteResW<"WriteVNShiftI", []>;
776defm "" : LMULWriteRes<"WriteVICmpV", []>;
777defm "" : LMULWriteRes<"WriteVICmpX", []>;
778defm "" : LMULWriteRes<"WriteVICmpI", []>;
779defm "" : LMULWriteRes<"WriteVIMinMaxV", []>;
780defm "" : LMULWriteRes<"WriteVIMinMaxX", []>;
781defm "" : LMULWriteRes<"WriteVIMulV", []>;
782defm "" : LMULWriteRes<"WriteVIMulX", []>;
783defm "" : LMULSEWWriteRes<"WriteVIDivV", []>;
784defm "" : LMULSEWWriteRes<"WriteVIDivX", []>;
785defm "" : LMULWriteResW<"WriteVIWMulV", []>;
786defm "" : LMULWriteResW<"WriteVIWMulX", []>;
787defm "" : LMULWriteRes<"WriteVIMulAddV", []>;
788defm "" : LMULWriteRes<"WriteVIMulAddX", []>;
789defm "" : LMULWriteResW<"WriteVIWMulAddV", []>;
790defm "" : LMULWriteResW<"WriteVIWMulAddX", []>;
791defm "" : LMULWriteRes<"WriteVIMergeV", []>;
792defm "" : LMULWriteRes<"WriteVIMergeX", []>;
793defm "" : LMULWriteRes<"WriteVIMergeI", []>;
794defm "" : LMULWriteRes<"WriteVIMovV", []>;
795defm "" : LMULWriteRes<"WriteVIMovX", []>;
796defm "" : LMULWriteRes<"WriteVIMovI", []>;
797
798// 12. Vector Fixed-Point Arithmetic Instructions
799defm "" : LMULWriteRes<"WriteVSALUV", []>;
800defm "" : LMULWriteRes<"WriteVSALUX", []>;
801defm "" : LMULWriteRes<"WriteVSALUI", []>;
802defm "" : LMULWriteRes<"WriteVAALUV", []>;
803defm "" : LMULWriteRes<"WriteVAALUX", []>;
804defm "" : LMULWriteRes<"WriteVSMulV", []>;
805defm "" : LMULWriteRes<"WriteVSMulX", []>;
806defm "" : LMULWriteRes<"WriteVSShiftV", []>;
807defm "" : LMULWriteRes<"WriteVSShiftX", []>;
808defm "" : LMULWriteRes<"WriteVSShiftI", []>;
809defm "" : LMULWriteResW<"WriteVNClipV", []>;
810defm "" : LMULWriteResW<"WriteVNClipX", []>;
811defm "" : LMULWriteResW<"WriteVNClipI", []>;
812
813// 13. Vector Floating-Point Instructions
814defm "" : LMULWriteRes<"WriteVFALUV", []>;
815defm "" : LMULWriteRes<"WriteVFALUF", []>;
816defm "" : LMULWriteResFW<"WriteVFWALUV", []>;
817defm "" : LMULWriteResFW<"WriteVFWALUF", []>;
818defm "" : LMULWriteRes<"WriteVFMulV", []>;
819defm "" : LMULWriteRes<"WriteVFMulF", []>;
820defm "" : LMULSEWWriteResF<"WriteVFDivV", []>;
821defm "" : LMULSEWWriteResF<"WriteVFDivF", []>;
822defm "" : LMULWriteResFW<"WriteVFWMulV", []>;
823defm "" : LMULWriteResFW<"WriteVFWMulF", []>;
824defm "" : LMULWriteRes<"WriteVFMulAddV", []>;
825defm "" : LMULWriteRes<"WriteVFMulAddF", []>;
826defm "" : LMULWriteResFW<"WriteVFWMulAddV", []>;
827defm "" : LMULWriteResFW<"WriteVFWMulAddF", []>;
828defm "" : LMULSEWWriteResF<"WriteVFSqrtV", []>;
829defm "" : LMULWriteRes<"WriteVFRecpV", []>;
830defm "" : LMULWriteRes<"WriteVFMinMaxV", []>;
831defm "" : LMULWriteRes<"WriteVFMinMaxF", []>;
832defm "" : LMULWriteRes<"WriteVFSgnjV", []>;
833defm "" : LMULWriteRes<"WriteVFSgnjF", []>;
834defm "" : LMULWriteRes<"WriteVFCmpV", []>;
835defm "" : LMULWriteRes<"WriteVFCmpF", []>;
836defm "" : LMULWriteRes<"WriteVFClassV", []>;
837defm "" : LMULWriteRes<"WriteVFMergeV", []>;
838defm "" : LMULWriteRes<"WriteVFMovV", []>;
839defm "" : LMULWriteRes<"WriteVFCvtIToFV", []>;
840defm "" : LMULWriteRes<"WriteVFCvtFToIV", []>;
841defm "" : LMULWriteResW<"WriteVFWCvtIToFV", []>;
842defm "" : LMULWriteResFW<"WriteVFWCvtFToIV", []>;
843defm "" : LMULWriteResFW<"WriteVFWCvtFToFV", []>;
844defm "" : LMULWriteResFW<"WriteVFNCvtIToFV", []>;
845defm "" : LMULWriteResW<"WriteVFNCvtFToIV", []>;
846defm "" : LMULWriteResFW<"WriteVFNCvtFToFV", []>;
847
848// 14. Vector Reduction Operations
849defm "" : LMULSEWWriteRes<"WriteVIRedV_From", []>;
850defm "" : LMULSEWWriteRes<"WriteVIRedMinMaxV_From", []>;
851defm "" : LMULSEWWriteResWRed<"WriteVIWRedV_From", []>;
852defm "" : LMULSEWWriteResF<"WriteVFRedV_From", []>;
853defm "" : LMULSEWWriteResF<"WriteVFRedOV_From", []>;
854defm "" : LMULSEWWriteResF<"WriteVFRedMinMaxV_From", []>;
855defm "" : LMULSEWWriteResFWRed<"WriteVFWRedV_From", []>;
856defm "" : LMULSEWWriteResFWRed<"WriteVFWRedOV_From", []>;
857
858// 15. Vector Mask Instructions
859defm "" : LMULWriteRes<"WriteVMALUV", []>;
860defm "" : LMULWriteRes<"WriteVMPopV", []>;
861defm "" : LMULWriteRes<"WriteVMFFSV", []>;
862defm "" : LMULWriteRes<"WriteVMSFSV", []>;
863defm "" : LMULWriteRes<"WriteVMIotV", []>;
864defm "" : LMULWriteRes<"WriteVMIdxV", []>;
865
866// 16. Vector Permutation Instructions
867def : WriteRes<WriteVIMovVX, []>;
868def : WriteRes<WriteVIMovXV, []>;
869def : WriteRes<WriteVFMovVF, []>;
870def : WriteRes<WriteVFMovFV, []>;
871defm "" : LMULWriteRes<"WriteVISlideX", []>;
872defm "" : LMULWriteRes<"WriteVISlideI", []>;
873defm "" : LMULWriteRes<"WriteVISlide1X", []>;
874defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
875defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
876defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
877defm "" : LMULWriteRes<"WriteVRGatherVI", []>;
878defm "" : LMULSEWWriteRes<"WriteVCompressV", []>;
879// These are already LMUL aware
880def : WriteRes<WriteVMov1V, []>;
881def : WriteRes<WriteVMov2V, []>;
882def : WriteRes<WriteVMov4V, []>;
883def : WriteRes<WriteVMov8V, []>;
884
885// 6. Configuration-Setting Instructions
886def : ReadAdvance<ReadVSETVLI, 0>;
887def : ReadAdvance<ReadVSETVL, 0>;
888
889// 7. Vector Loads and Stores
890def : ReadAdvance<ReadVLDX, 0>;
891def : ReadAdvance<ReadVSTX, 0>;
892defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
893defm "" : LMULReadAdvance<"ReadVSTM", 0>;
894def : ReadAdvance<ReadVLDSX, 0>;
895def : ReadAdvance<ReadVSTSX, 0>;
896defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
897defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
898defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
899defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
900defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
901defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
902defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
903defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
904defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
905defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
906defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
907defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
908defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
909defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
910defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
911defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
912defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
913defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
914defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
915defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
916defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
917defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
918defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
919defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
920// These are already LMUL aware
921def : ReadAdvance<ReadVST1R, 0>;
922def : ReadAdvance<ReadVST2R, 0>;
923def : ReadAdvance<ReadVST4R, 0>;
924def : ReadAdvance<ReadVST8R, 0>;
925
926// 11. Vector Integer Arithmetic Instructions
927defm "" : LMULReadAdvance<"ReadVIALUV", 0>;
928defm "" : LMULReadAdvance<"ReadVIALUX", 0>;
929defm "" : LMULReadAdvanceW<"ReadVIWALUV", 0>;
930defm "" : LMULReadAdvanceW<"ReadVIWALUX", 0>;
931defm "" : LMULReadAdvance<"ReadVExtV", 0>;
932defm "" : LMULReadAdvance<"ReadVICALUV", 0>;
933defm "" : LMULReadAdvance<"ReadVICALUX", 0>;
934defm "" : LMULReadAdvance<"ReadVShiftV", 0>;
935defm "" : LMULReadAdvance<"ReadVShiftX", 0>;
936defm "" : LMULReadAdvanceW<"ReadVNShiftV", 0>;
937defm "" : LMULReadAdvanceW<"ReadVNShiftX", 0>;
938defm "" : LMULReadAdvance<"ReadVICmpV", 0>;
939defm "" : LMULReadAdvance<"ReadVICmpX", 0>;
940defm "" : LMULReadAdvance<"ReadVIMinMaxV", 0>;
941defm "" : LMULReadAdvance<"ReadVIMinMaxX", 0>;
942defm "" : LMULReadAdvance<"ReadVIMulV", 0>;
943defm "" : LMULReadAdvance<"ReadVIMulX", 0>;
944defm "" : LMULSEWReadAdvance<"ReadVIDivV", 0>;
945defm "" : LMULSEWReadAdvance<"ReadVIDivX", 0>;
946defm "" : LMULReadAdvanceW<"ReadVIWMulV", 0>;
947defm "" : LMULReadAdvanceW<"ReadVIWMulX", 0>;
948defm "" : LMULReadAdvance<"ReadVIMulAddV", 0>;
949defm "" : LMULReadAdvance<"ReadVIMulAddX", 0>;
950defm "" : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
951defm "" : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
952defm "" : LMULReadAdvance<"ReadVIMergeV", 0>;
953defm "" : LMULReadAdvance<"ReadVIMergeX", 0>;
954defm "" : LMULReadAdvance<"ReadVIMovV", 0>;
955defm "" : LMULReadAdvance<"ReadVIMovX", 0>;
956
957// 12. Vector Fixed-Point Arithmetic Instructions
958defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
959defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
960defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
961defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
962defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
963defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
964defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
965defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
966defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
967defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
968
969// 13. Vector Floating-Point Instructions
970defm "" : LMULReadAdvance<"ReadVFALUV", 0>;
971defm "" : LMULReadAdvance<"ReadVFALUF", 0>;
972defm "" : LMULReadAdvanceFW<"ReadVFWALUV", 0>;
973defm "" : LMULReadAdvanceFW<"ReadVFWALUF", 0>;
974defm "" : LMULReadAdvance<"ReadVFMulV", 0>;
975defm "" : LMULReadAdvance<"ReadVFMulF", 0>;
976defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
977defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
978defm "" : LMULReadAdvanceFW<"ReadVFWMulV", 0>;
979defm "" : LMULReadAdvanceFW<"ReadVFWMulF", 0>;
980defm "" : LMULReadAdvance<"ReadVFMulAddV", 0>;
981defm "" : LMULReadAdvance<"ReadVFMulAddF", 0>;
982defm "" : LMULReadAdvanceFW<"ReadVFWMulAddV", 0>;
983defm "" : LMULReadAdvanceFW<"ReadVFWMulAddF", 0>;
984defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
985defm "" : LMULReadAdvance<"ReadVFRecpV", 0>;
986defm "" : LMULReadAdvance<"ReadVFMinMaxV", 0>;
987defm "" : LMULReadAdvance<"ReadVFMinMaxF", 0>;
988defm "" : LMULReadAdvance<"ReadVFSgnjV", 0>;
989defm "" : LMULReadAdvance<"ReadVFSgnjF", 0>;
990defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
991defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
992defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
993defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
994defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
995defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
996defm "" : LMULReadAdvance<"ReadVFCvtIToFV", 0>;
997defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
998defm "" : LMULReadAdvanceW<"ReadVFWCvtIToFV", 0>;
999defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
1000defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
1001defm "" : LMULReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
1002defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
1003defm "" : LMULReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
1004
1005// 14. Vector Reduction Operations
1006def : ReadAdvance<ReadVIRedV, 0>;
1007def : ReadAdvance<ReadVIRedV0, 0>;
1008def : ReadAdvance<ReadVIWRedV, 0>;
1009def : ReadAdvance<ReadVIWRedV0, 0>;
1010def : ReadAdvance<ReadVFRedV, 0>;
1011def : ReadAdvance<ReadVFRedV0, 0>;
1012def : ReadAdvance<ReadVFRedOV, 0>;
1013def : ReadAdvance<ReadVFRedOV0, 0>;
1014def : ReadAdvance<ReadVFRedMinMaxV, 0>;
1015def : ReadAdvance<ReadVFWRedV, 0>;
1016def : ReadAdvance<ReadVFWRedV0, 0>;
1017def : ReadAdvance<ReadVFWRedOV, 0>;
1018def : ReadAdvance<ReadVFWRedOV0, 0>;
1019
1020// 15. Vector Mask Instructions
1021defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
1022defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
1023defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
1024defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
1025defm "" : LMULReadAdvance<"ReadVMIotV", 0>;
1026
1027// 16. Vector Permutation Instructions
1028def : ReadAdvance<ReadVIMovVX, 0>;
1029def : ReadAdvance<ReadVIMovXV, 0>;
1030def : ReadAdvance<ReadVIMovXX, 0>;
1031def : ReadAdvance<ReadVFMovVF, 0>;
1032def : ReadAdvance<ReadVFMovFV, 0>;
1033def : ReadAdvance<ReadVFMovFX, 0>;
1034defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
1035defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
1036defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
1037defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
1038defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
1039defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
1040defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
1041defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
1042defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
1043defm "" : LMULReadAdvance<"ReadVGatherV", 0>;
1044defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
1045// These are already LMUL aware
1046def : ReadAdvance<ReadVMov1V, 0>;
1047def : ReadAdvance<ReadVMov2V, 0>;
1048def : ReadAdvance<ReadVMov4V, 0>;
1049def : ReadAdvance<ReadVMov8V, 0>;
1050
1051// Others
1052def : ReadAdvance<ReadVMask, 0>;
1053
1054} // Unsupported
1055} // UnsupportedSchedV
1056