1//===-- RISCVSchedule.td - RISCV Scheduling Definitions ----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9/// Define scheduler resources associated with def operands. 10def WriteIALU : SchedWrite; // 32 or 64-bit integer ALU operations 11def WriteIALU32 : SchedWrite; // 32-bit integer ALU operations on RV64I 12def WriteShiftImm : SchedWrite; // 32 or 64-bit shift by immediate operations 13def WriteShiftImm32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix 14def WriteShiftReg : SchedWrite; // 32 or 64-bit shift by immediate operations 15def WriteShiftReg32 : SchedWrite; // 32-bit shift by immediate operations on RV64Ix 16def WriteIDiv : SchedWrite; // 32-bit or 64-bit divide and remainder 17def WriteIDiv32 : SchedWrite; // 32-bit divide and remainder on RV64I 18def WriteIMul : SchedWrite; // 32-bit or 64-bit multiply 19def WriteIMul32 : SchedWrite; // 32-bit multiply on RV64I 20def WriteJmp : SchedWrite; // Jump 21def WriteJal : SchedWrite; // Jump and link 22def WriteJalr : SchedWrite; // Jump and link register 23def WriteJmpReg : SchedWrite; // Jump register 24def WriteNop : SchedWrite; 25def WriteLDB : SchedWrite; // Load byte 26def WriteLDH : SchedWrite; // Load half-word 27def WriteLDW : SchedWrite; // Load word 28def WriteLDD : SchedWrite; // Load double-word 29def WriteCSR : SchedWrite; // CSR instructions 30def WriteSTB : SchedWrite; // Store byte 31def WriteSTH : SchedWrite; // Store half-word 32def WriteSTW : SchedWrite; // Store word 33def WriteSTD : SchedWrite; // Store double-word 34def WriteAtomicW : SchedWrite; //Atomic memory operation word size 35def WriteAtomicD : SchedWrite; //Atomic memory operation double word size 36def WriteAtomicLDW : SchedWrite; // Atomic load word 37def WriteAtomicLDD : SchedWrite; // Atomic load double word 38def WriteAtomicSTW : SchedWrite; // Atomic store word 39def WriteAtomicSTD : SchedWrite; // Atomic store double word 40def WriteFAdd16 : SchedWrite; // 16-bit floating point addition/subtraction 41def WriteFAdd32 : SchedWrite; // 32-bit floating point addition/subtraction 42def WriteFAdd64 : SchedWrite; // 64-bit floating point addition/subtraction 43def WriteFMul16 : SchedWrite; // 16-bit floating point multiply 44def WriteFMul32 : SchedWrite; // 32-bit floating point multiply 45def WriteFMul64 : SchedWrite; // 64-bit floating point multiply 46def WriteFMA16 : SchedWrite; // 16-bit floating point fused multiply-add 47def WriteFMA32 : SchedWrite; // 32-bit floating point fused multiply-add 48def WriteFMA64 : SchedWrite; // 64-bit floating point fused multiply-add 49def WriteFDiv16 : SchedWrite; // 16-bit floating point divide 50def WriteFDiv32 : SchedWrite; // 32-bit floating point divide 51def WriteFDiv64 : SchedWrite; // 64-bit floating point divide 52def WriteFSqrt16 : SchedWrite; // 16-bit floating point sqrt 53def WriteFSqrt32 : SchedWrite; // 32-bit floating point sqrt 54def WriteFSqrt64 : SchedWrite; // 64-bit floating point sqrt 55 56// Integer to float conversions 57def WriteFCvtI32ToF16 : SchedWrite; 58def WriteFCvtI32ToF32 : SchedWrite; 59def WriteFCvtI32ToF64 : SchedWrite; 60def WriteFCvtI64ToF16 : SchedWrite; // RV64I only 61def WriteFCvtI64ToF32 : SchedWrite; // RV64I only 62def WriteFCvtI64ToF64 : SchedWrite; // RV64I only 63 64//Float to integer conversions 65def WriteFCvtF16ToI32 : SchedWrite; 66def WriteFCvtF16ToI64 : SchedWrite; // RV64I only 67def WriteFCvtF32ToI32 : SchedWrite; 68def WriteFCvtF32ToI64 : SchedWrite; // RV64I only 69def WriteFCvtF64ToI32 : SchedWrite; 70def WriteFCvtF64ToI64 : SchedWrite; // RV64I only 71 72// Float to float conversions 73def WriteFCvtF32ToF64 : SchedWrite; 74def WriteFCvtF64ToF32 : SchedWrite; 75def WriteFCvtF16ToF32 : SchedWrite; 76def WriteFCvtF32ToF16 : SchedWrite; 77def WriteFCvtF16ToF64 : SchedWrite; 78def WriteFCvtF64ToF16 : SchedWrite; 79 80def WriteFClass16 : SchedWrite; // 16-bit floating point classify 81def WriteFClass32 : SchedWrite; // 32-bit floating point classify 82def WriteFClass64 : SchedWrite; // 64-bit floating point classify 83def WriteFCmp16 : SchedWrite; // 16-bit floating point compare 84def WriteFCmp32 : SchedWrite; // 32-bit floating point compare 85def WriteFCmp64 : SchedWrite; // 64-bit floating point compare 86def WriteFSGNJ16 : SchedWrite; // 16-bit floating point sign-injection 87def WriteFSGNJ32 : SchedWrite; // 32-bit floating point sign-injection 88def WriteFSGNJ64 : SchedWrite; // 64-bit floating point sign-injection 89def WriteFMinMax16 : SchedWrite; // 16-bit floating point min or max 90def WriteFMinMax32 : SchedWrite; // 32-bit floating point min or max 91def WriteFMinMax64 : SchedWrite; // 64-bit floating point min or max 92 93def WriteFMovF16ToI16 : SchedWrite; 94def WriteFMovI16ToF16 : SchedWrite; 95def WriteFMovF32ToI32 : SchedWrite; 96def WriteFMovI32ToF32 : SchedWrite; 97def WriteFMovF64ToI64 : SchedWrite; // RV64I only 98def WriteFMovI64ToF64 : SchedWrite; // RV64I only 99 100def WriteFLD16 : SchedWrite; // Floating point sp load 101def WriteFLD32 : SchedWrite; // Floating point sp load 102def WriteFLD64 : SchedWrite; // Floating point dp load 103def WriteFST16 : SchedWrite; // Floating point sp store 104def WriteFST32 : SchedWrite; // Floating point sp store 105def WriteFST64 : SchedWrite; // Floating point dp store 106 107// short forward branch for Bullet 108def WriteSFB : SchedWrite; 109def ReadSFB : SchedRead; 110 111/// Define scheduler resources associated with use operands. 112def ReadJmp : SchedRead; 113def ReadJalr : SchedRead; 114def ReadCSR : SchedRead; 115def ReadMemBase : SchedRead; 116def ReadFMemBase : SchedRead; 117def ReadStoreData : SchedRead; 118def ReadFStoreData : SchedRead; 119def ReadIALU : SchedRead; 120def ReadIALU32 : SchedRead; // 32-bit integer ALU operations on RV64I 121def ReadShiftImm : SchedRead; 122def ReadShiftImm32 : SchedRead; // 32-bit shift by immediate operations on RV64Ix 123def ReadShiftReg : SchedRead; 124def ReadShiftReg32 : SchedRead; // 32-bit shift by register operations on RV64Ix 125def ReadIDiv : SchedRead; 126def ReadIDiv32 : SchedRead; 127def ReadIMul : SchedRead; 128def ReadIMul32 : SchedRead; 129def ReadAtomicWA : SchedRead; 130def ReadAtomicWD : SchedRead; 131def ReadAtomicDA : SchedRead; 132def ReadAtomicDD : SchedRead; 133def ReadAtomicLDW : SchedRead; // Atomic load word 134def ReadAtomicLDD : SchedRead; // Atomic load double word 135def ReadAtomicSTW : SchedRead; // Atomic store word 136def ReadAtomicSTD : SchedRead; // Atomic store double word 137def ReadFAdd16 : SchedRead; // 16-bit floating point addition/subtraction 138def ReadFAdd32 : SchedRead; // 32-bit floating point addition/subtraction 139def ReadFAdd64 : SchedRead; // 64-bit floating point addition/subtraction 140def ReadFMul16 : SchedRead; // 16-bit floating point multiply 141def ReadFMul32 : SchedRead; // 32-bit floating point multiply 142def ReadFMul64 : SchedRead; // 64-bit floating point multiply 143def ReadFMA16 : SchedRead; // 16-bit floating point fused multiply-add 144def ReadFMA32 : SchedRead; // 32-bit floating point fused multiply-add 145def ReadFMA64 : SchedRead; // 64-bit floating point fused multiply-add 146def ReadFDiv16 : SchedRead; // 16-bit floating point divide 147def ReadFDiv32 : SchedRead; // 32-bit floating point divide 148def ReadFDiv64 : SchedRead; // 64-bit floating point divide 149def ReadFSqrt16 : SchedRead; // 16-bit floating point sqrt 150def ReadFSqrt32 : SchedRead; // 32-bit floating point sqrt 151def ReadFSqrt64 : SchedRead; // 64-bit floating point sqrt 152def ReadFCmp16 : SchedRead; 153def ReadFCmp32 : SchedRead; 154def ReadFCmp64 : SchedRead; 155def ReadFSGNJ16 : SchedRead; 156def ReadFSGNJ32 : SchedRead; 157def ReadFSGNJ64 : SchedRead; 158def ReadFMinMax16 : SchedRead; 159def ReadFMinMax32 : SchedRead; 160def ReadFMinMax64 : SchedRead; 161def ReadFCvtF16ToI32 : SchedRead; 162def ReadFCvtF16ToI64 : SchedRead; 163def ReadFCvtF32ToI32 : SchedRead; 164def ReadFCvtF32ToI64 : SchedRead; 165def ReadFCvtF64ToI32 : SchedRead; 166def ReadFCvtF64ToI64 : SchedRead; 167def ReadFCvtI32ToF16 : SchedRead; 168def ReadFCvtI32ToF32 : SchedRead; 169def ReadFCvtI32ToF64 : SchedRead; 170def ReadFCvtI64ToF16 : SchedRead; 171def ReadFCvtI64ToF32 : SchedRead; 172def ReadFCvtI64ToF64 : SchedRead; 173def ReadFMovF16ToI16 : SchedRead; 174def ReadFMovI16ToF16 : SchedRead; 175def ReadFMovF32ToI32 : SchedRead; 176def ReadFMovI32ToF32 : SchedRead; 177def ReadFMovF64ToI64 : SchedRead; 178def ReadFMovI64ToF64 : SchedRead; 179def ReadFCvtF32ToF64 : SchedRead; 180def ReadFCvtF64ToF32 : SchedRead; 181def ReadFCvtF16ToF32 : SchedRead; 182def ReadFCvtF32ToF16 : SchedRead; 183def ReadFCvtF16ToF64 : SchedRead; 184def ReadFCvtF64ToF16 : SchedRead; 185def ReadFClass16 : SchedRead; 186def ReadFClass32 : SchedRead; 187def ReadFClass64 : SchedRead; 188 189multiclass UnsupportedSchedZfh { 190let Unsupported = true in { 191def : WriteRes<WriteFAdd16, []>; 192def : WriteRes<WriteFClass16, []>; 193def : WriteRes<WriteFCvtF16ToF64, []>; 194def : WriteRes<WriteFCvtF64ToF16, []>; 195def : WriteRes<WriteFCvtI64ToF16, []>; 196def : WriteRes<WriteFCvtF32ToF16, []>; 197def : WriteRes<WriteFCvtI32ToF16, []>; 198def : WriteRes<WriteFCvtF16ToI64, []>; 199def : WriteRes<WriteFCvtF16ToF32, []>; 200def : WriteRes<WriteFCvtF16ToI32, []>; 201def : WriteRes<WriteFDiv16, []>; 202def : WriteRes<WriteFCmp16, []>; 203def : WriteRes<WriteFLD16, []>; 204def : WriteRes<WriteFMA16, []>; 205def : WriteRes<WriteFMinMax16, []>; 206def : WriteRes<WriteFMul16, []>; 207def : WriteRes<WriteFMovI16ToF16, []>; 208def : WriteRes<WriteFMovF16ToI16, []>; 209def : WriteRes<WriteFSGNJ16, []>; 210def : WriteRes<WriteFST16, []>; 211def : WriteRes<WriteFSqrt16, []>; 212 213def : ReadAdvance<ReadFAdd16, 0>; 214def : ReadAdvance<ReadFClass16, 0>; 215def : ReadAdvance<ReadFCvtF16ToF64, 0>; 216def : ReadAdvance<ReadFCvtF64ToF16, 0>; 217def : ReadAdvance<ReadFCvtI64ToF16, 0>; 218def : ReadAdvance<ReadFCvtF32ToF16, 0>; 219def : ReadAdvance<ReadFCvtI32ToF16, 0>; 220def : ReadAdvance<ReadFCvtF16ToI64, 0>; 221def : ReadAdvance<ReadFCvtF16ToF32, 0>; 222def : ReadAdvance<ReadFCvtF16ToI32, 0>; 223def : ReadAdvance<ReadFDiv16, 0>; 224def : ReadAdvance<ReadFCmp16, 0>; 225def : ReadAdvance<ReadFMA16, 0>; 226def : ReadAdvance<ReadFMinMax16, 0>; 227def : ReadAdvance<ReadFMul16, 0>; 228def : ReadAdvance<ReadFMovI16ToF16, 0>; 229def : ReadAdvance<ReadFMovF16ToI16, 0>; 230def : ReadAdvance<ReadFSGNJ16, 0>; 231def : ReadAdvance<ReadFSqrt16, 0>; 232} // Unsupported = true 233} 234 235multiclass UnsupportedSchedSFB { 236let Unsupported = true in { 237def : WriteRes<WriteSFB, []>; 238 239def : ReadAdvance<ReadSFB, 0>; 240} // Unsupported = true 241} 242 243// Include the scheduler resources for other instruction extensions. 244include "RISCVScheduleZb.td" 245include "RISCVScheduleV.td" 246