xref: /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td (revision ec0ea6efa1ad229d75c394c1a9b9cac33af2b1d3)
1//==- RISCVSchedSiFive7.td - SiFive7 Scheduling Definitions --*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10
11// SiFive7 machine model for scheduling and other instruction cost heuristics.
12def SiFive7Model : SchedMachineModel {
13  let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order.
14  let IssueWidth = 2;        // 2 micro-ops are dispatched per cycle.
15  let LoadLatency = 3;
16  let MispredictPenalty = 3;
17  let CompleteModel = 0;
18  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvamo, HasStdExtZvlsseg];
19}
20
21// The SiFive7 microarchitecure has two pipelines: A and B.
22// Pipe A can handle memory, integer alu and vector operations.
23// Pipe B can handle integer alu, control flow, integer multiply and divide,
24// and floating point computation.
25let SchedModel = SiFive7Model in {
26let BufferSize = 0 in {
27def SiFive7PipeA       : ProcResource<1>;
28def SiFive7PipeB       : ProcResource<1>;
29}
30
31let BufferSize = 1 in {
32def SiFive7IDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division
33def SiFive7FDiv        : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt
34}
35
36def SiFive7PipeAB : ProcResGroup<[SiFive7PipeA, SiFive7PipeB]>;
37
38// Branching
39def : WriteRes<WriteJmp, [SiFive7PipeB]>;
40def : WriteRes<WriteJal, [SiFive7PipeB]>;
41def : WriteRes<WriteJalr, [SiFive7PipeB]>;
42def : WriteRes<WriteJmpReg, [SiFive7PipeB]>;
43
44// Integer arithmetic and logic
45let Latency = 3 in {
46def : WriteRes<WriteIALU, [SiFive7PipeAB]>;
47def : WriteRes<WriteIALU32, [SiFive7PipeAB]>;
48def : WriteRes<WriteShiftImm, [SiFive7PipeAB]>;
49def : WriteRes<WriteShiftImm32, [SiFive7PipeAB]>;
50def : WriteRes<WriteShiftReg, [SiFive7PipeAB]>;
51def : WriteRes<WriteShiftReg32, [SiFive7PipeAB]>;
52}
53
54// Integer multiplication
55let Latency = 3 in {
56def : WriteRes<WriteIMul, [SiFive7PipeB]>;
57def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
58}
59
60// Integer division
61def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
62  let Latency = 16;
63  let ResourceCycles = [1, 15];
64}
65def : WriteRes<WriteIDiv32,  [SiFive7PipeB, SiFive7IDiv]> {
66  let Latency = 16;
67  let ResourceCycles = [1, 15];
68}
69
70// Memory
71def : WriteRes<WriteSTB, [SiFive7PipeA]>;
72def : WriteRes<WriteSTH, [SiFive7PipeA]>;
73def : WriteRes<WriteSTW, [SiFive7PipeA]>;
74def : WriteRes<WriteSTD, [SiFive7PipeA]>;
75def : WriteRes<WriteFST32, [SiFive7PipeA]>;
76def : WriteRes<WriteFST64, [SiFive7PipeA]>;
77
78let Latency = 3 in {
79def : WriteRes<WriteLDB, [SiFive7PipeA]>;
80def : WriteRes<WriteLDH, [SiFive7PipeA]>;
81def : WriteRes<WriteLDW, [SiFive7PipeA]>;
82def : WriteRes<WriteLDWU, [SiFive7PipeA]>;
83def : WriteRes<WriteLDD, [SiFive7PipeA]>;
84}
85
86let Latency = 2 in {
87def : WriteRes<WriteFLD32, [SiFive7PipeA]>;
88def : WriteRes<WriteFLD64, [SiFive7PipeA]>;
89}
90
91// Atomic memory
92def : WriteRes<WriteAtomicSTW, [SiFive7PipeA]>;
93def : WriteRes<WriteAtomicSTD, [SiFive7PipeA]>;
94
95let Latency = 3 in {
96def : WriteRes<WriteAtomicW, [SiFive7PipeA]>;
97def : WriteRes<WriteAtomicD, [SiFive7PipeA]>;
98def : WriteRes<WriteAtomicLDW, [SiFive7PipeA]>;
99def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>;
100}
101
102// Single precision.
103let Latency = 5 in {
104def : WriteRes<WriteFALU32, [SiFive7PipeB]>;
105def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
106def : WriteRes<WriteFMA32, [SiFive7PipeB]>;
107}
108let Latency = 3 in {
109def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>;
110def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>;
111}
112
113def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
114                                                         let ResourceCycles = [1, 26]; }
115def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
116                                                          let ResourceCycles = [1, 26]; }
117
118// Double precision
119let Latency = 7 in {
120def : WriteRes<WriteFALU64, [SiFive7PipeB]>;
121def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
122def : WriteRes<WriteFMA64, [SiFive7PipeB]>;
123}
124let Latency = 3 in {
125def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>;
126def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>;
127}
128
129def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
130                                                         let ResourceCycles = [1, 55]; }
131def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
132                                                          let ResourceCycles = [1, 55]; }
133
134// Conversions
135let Latency = 3 in {
136def : WriteRes<WriteFCvtI32ToF32, [SiFive7PipeB]>;
137def : WriteRes<WriteFCvtI32ToF64, [SiFive7PipeB]>;
138def : WriteRes<WriteFCvtI64ToF32, [SiFive7PipeB]>;
139def : WriteRes<WriteFCvtI64ToF64, [SiFive7PipeB]>;
140def : WriteRes<WriteFCvtF32ToI32, [SiFive7PipeB]>;
141def : WriteRes<WriteFCvtF32ToI64, [SiFive7PipeB]>;
142def : WriteRes<WriteFCvtF32ToF64, [SiFive7PipeB]>;
143def : WriteRes<WriteFCvtF64ToI32, [SiFive7PipeB]>;
144def : WriteRes<WriteFCvtF64ToI64, [SiFive7PipeB]>;
145def : WriteRes<WriteFCvtF64ToF32, [SiFive7PipeB]>;
146
147def : WriteRes<WriteFClass32, [SiFive7PipeB]>;
148def : WriteRes<WriteFClass64, [SiFive7PipeB]>;
149def : WriteRes<WriteFCmp32, [SiFive7PipeB]>;
150def : WriteRes<WriteFCmp64, [SiFive7PipeB]>;
151def : WriteRes<WriteFMovI32ToF32, [SiFive7PipeB]>;
152def : WriteRes<WriteFMovF32ToI32, [SiFive7PipeB]>;
153def : WriteRes<WriteFMovI64ToF64, [SiFive7PipeB]>;
154def : WriteRes<WriteFMovF64ToI64, [SiFive7PipeB]>;
155}
156
157// Others
158def : WriteRes<WriteCSR, [SiFive7PipeB]>;
159def : WriteRes<WriteNop, []>;
160
161def : InstRW<[WriteIALU], (instrs COPY)>;
162
163//===----------------------------------------------------------------------===//
164// Bypass and advance
165def : ReadAdvance<ReadJmp, 0>;
166def : ReadAdvance<ReadJalr, 0>;
167def : ReadAdvance<ReadCSR, 0>;
168def : ReadAdvance<ReadStoreData, 0>;
169def : ReadAdvance<ReadMemBase, 0>;
170def : ReadAdvance<ReadIALU, 0>;
171def : ReadAdvance<ReadIALU32, 0>;
172def : ReadAdvance<ReadShiftImm, 0>;
173def : ReadAdvance<ReadShiftImm32, 0>;
174def : ReadAdvance<ReadShiftReg, 0>;
175def : ReadAdvance<ReadShiftReg32, 0>;
176def : ReadAdvance<ReadIDiv, 0>;
177def : ReadAdvance<ReadIDiv32, 0>;
178def : ReadAdvance<ReadIMul, 0>;
179def : ReadAdvance<ReadIMul32, 0>;
180def : ReadAdvance<ReadAtomicWA, 0>;
181def : ReadAdvance<ReadAtomicWD, 0>;
182def : ReadAdvance<ReadAtomicDA, 0>;
183def : ReadAdvance<ReadAtomicDD, 0>;
184def : ReadAdvance<ReadAtomicLDW, 0>;
185def : ReadAdvance<ReadAtomicLDD, 0>;
186def : ReadAdvance<ReadAtomicSTW, 0>;
187def : ReadAdvance<ReadAtomicSTD, 0>;
188def : ReadAdvance<ReadFMemBase, 0>;
189def : ReadAdvance<ReadFALU32, 0>;
190def : ReadAdvance<ReadFALU64, 0>;
191def : ReadAdvance<ReadFMul32, 0>;
192def : ReadAdvance<ReadFMA32, 0>;
193def : ReadAdvance<ReadFMul64, 0>;
194def : ReadAdvance<ReadFMA64, 0>;
195def : ReadAdvance<ReadFDiv32, 0>;
196def : ReadAdvance<ReadFDiv64, 0>;
197def : ReadAdvance<ReadFSqrt32, 0>;
198def : ReadAdvance<ReadFSqrt64, 0>;
199def : ReadAdvance<ReadFCmp32, 0>;
200def : ReadAdvance<ReadFCmp64, 0>;
201def : ReadAdvance<ReadFSGNJ32, 0>;
202def : ReadAdvance<ReadFSGNJ64, 0>;
203def : ReadAdvance<ReadFMinMax32, 0>;
204def : ReadAdvance<ReadFMinMax64, 0>;
205def : ReadAdvance<ReadFCvtF32ToI32, 0>;
206def : ReadAdvance<ReadFCvtF32ToI64, 0>;
207def : ReadAdvance<ReadFCvtF64ToI32, 0>;
208def : ReadAdvance<ReadFCvtF64ToI64, 0>;
209def : ReadAdvance<ReadFCvtI32ToF32, 0>;
210def : ReadAdvance<ReadFCvtI32ToF64, 0>;
211def : ReadAdvance<ReadFCvtI64ToF32, 0>;
212def : ReadAdvance<ReadFCvtI64ToF64, 0>;
213def : ReadAdvance<ReadFCvtF32ToF64, 0>;
214def : ReadAdvance<ReadFCvtF64ToF32, 0>;
215def : ReadAdvance<ReadFMovF32ToI32, 0>;
216def : ReadAdvance<ReadFMovI32ToF32, 0>;
217def : ReadAdvance<ReadFMovF64ToI64, 0>;
218def : ReadAdvance<ReadFMovI64ToF64, 0>;
219def : ReadAdvance<ReadFClass32, 0>;
220def : ReadAdvance<ReadFClass64, 0>;
221
222//===----------------------------------------------------------------------===//
223// Unsupported extensions
224defm : UnsupportedSchedV;
225defm : UnsupportedSchedZba;
226defm : UnsupportedSchedZbb;
227defm : UnsupportedSchedZfh;
228}
229