1//==- RISCVSchedSiFive7.td - SiFive7 Scheduling Definitions --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10 11// SiFive7 machine model for scheduling and other instruction cost heuristics. 12def SiFive7Model : SchedMachineModel { 13 let MicroOpBufferSize = 0; // Explicitly set to zero since SiFive7 is in-order. 14 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle. 15 let LoadLatency = 3; 16 let MispredictPenalty = 3; 17 let CompleteModel = 0; 18 let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx, 19 HasStdExtZknd, HasStdExtZkne, HasStdExtZknh, 20 HasStdExtZksed, HasStdExtZksh, HasStdExtZkr, 21 HasVInstructions]; 22} 23 24// The SiFive7 microarchitecture has two pipelines: A and B. 25// Pipe A can handle memory, integer alu and vector operations. 26// Pipe B can handle integer alu, control flow, integer multiply and divide, 27// and floating point computation. 28let SchedModel = SiFive7Model in { 29let BufferSize = 0 in { 30def SiFive7PipeA : ProcResource<1>; 31def SiFive7PipeB : ProcResource<1>; 32} 33 34let BufferSize = 1 in { 35def SiFive7IDiv : ProcResource<1> { let Super = SiFive7PipeB; } // Int Division 36def SiFive7FDiv : ProcResource<1> { let Super = SiFive7PipeB; } // FP Division/Sqrt 37} 38 39def SiFive7PipeAB : ProcResGroup<[SiFive7PipeA, SiFive7PipeB]>; 40 41// Branching 42def : WriteRes<WriteJmp, [SiFive7PipeB]>; 43def : WriteRes<WriteJal, [SiFive7PipeB]>; 44def : WriteRes<WriteJalr, [SiFive7PipeB]>; 45def : WriteRes<WriteJmpReg, [SiFive7PipeB]>; 46 47// Integer arithmetic and logic 48let Latency = 3 in { 49def : WriteRes<WriteIALU, [SiFive7PipeAB]>; 50def : WriteRes<WriteIALU32, [SiFive7PipeAB]>; 51def : WriteRes<WriteShiftImm, [SiFive7PipeAB]>; 52def : WriteRes<WriteShiftImm32, [SiFive7PipeAB]>; 53def : WriteRes<WriteShiftReg, [SiFive7PipeAB]>; 54def : WriteRes<WriteShiftReg32, [SiFive7PipeAB]>; 55} 56 57// Integer multiplication 58let Latency = 3 in { 59def : WriteRes<WriteIMul, [SiFive7PipeB]>; 60def : WriteRes<WriteIMul32, [SiFive7PipeB]>; 61} 62 63// Integer division 64def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> { 65 let Latency = 16; 66 let ResourceCycles = [1, 15]; 67} 68def : WriteRes<WriteIDiv32, [SiFive7PipeB, SiFive7IDiv]> { 69 let Latency = 16; 70 let ResourceCycles = [1, 15]; 71} 72 73// Memory 74def : WriteRes<WriteSTB, [SiFive7PipeA]>; 75def : WriteRes<WriteSTH, [SiFive7PipeA]>; 76def : WriteRes<WriteSTW, [SiFive7PipeA]>; 77def : WriteRes<WriteSTD, [SiFive7PipeA]>; 78def : WriteRes<WriteFST32, [SiFive7PipeA]>; 79def : WriteRes<WriteFST64, [SiFive7PipeA]>; 80 81let Latency = 3 in { 82def : WriteRes<WriteLDB, [SiFive7PipeA]>; 83def : WriteRes<WriteLDH, [SiFive7PipeA]>; 84def : WriteRes<WriteLDW, [SiFive7PipeA]>; 85def : WriteRes<WriteLDWU, [SiFive7PipeA]>; 86def : WriteRes<WriteLDD, [SiFive7PipeA]>; 87} 88 89let Latency = 2 in { 90def : WriteRes<WriteFLD32, [SiFive7PipeA]>; 91def : WriteRes<WriteFLD64, [SiFive7PipeA]>; 92} 93 94// Atomic memory 95def : WriteRes<WriteAtomicSTW, [SiFive7PipeA]>; 96def : WriteRes<WriteAtomicSTD, [SiFive7PipeA]>; 97 98let Latency = 3 in { 99def : WriteRes<WriteAtomicW, [SiFive7PipeA]>; 100def : WriteRes<WriteAtomicD, [SiFive7PipeA]>; 101def : WriteRes<WriteAtomicLDW, [SiFive7PipeA]>; 102def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>; 103} 104 105// Single precision. 106let Latency = 5 in { 107def : WriteRes<WriteFALU32, [SiFive7PipeB]>; 108def : WriteRes<WriteFMul32, [SiFive7PipeB]>; 109def : WriteRes<WriteFMA32, [SiFive7PipeB]>; 110} 111let Latency = 3 in { 112def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>; 113def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>; 114} 115 116def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27; 117 let ResourceCycles = [1, 26]; } 118def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27; 119 let ResourceCycles = [1, 26]; } 120 121// Double precision 122let Latency = 7 in { 123def : WriteRes<WriteFALU64, [SiFive7PipeB]>; 124def : WriteRes<WriteFMul64, [SiFive7PipeB]>; 125def : WriteRes<WriteFMA64, [SiFive7PipeB]>; 126} 127let Latency = 3 in { 128def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>; 129def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>; 130} 131 132def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56; 133 let ResourceCycles = [1, 55]; } 134def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56; 135 let ResourceCycles = [1, 55]; } 136 137// Conversions 138let Latency = 3 in { 139def : WriteRes<WriteFCvtI32ToF32, [SiFive7PipeB]>; 140def : WriteRes<WriteFCvtI32ToF64, [SiFive7PipeB]>; 141def : WriteRes<WriteFCvtI64ToF32, [SiFive7PipeB]>; 142def : WriteRes<WriteFCvtI64ToF64, [SiFive7PipeB]>; 143def : WriteRes<WriteFCvtF32ToI32, [SiFive7PipeB]>; 144def : WriteRes<WriteFCvtF32ToI64, [SiFive7PipeB]>; 145def : WriteRes<WriteFCvtF32ToF64, [SiFive7PipeB]>; 146def : WriteRes<WriteFCvtF64ToI32, [SiFive7PipeB]>; 147def : WriteRes<WriteFCvtF64ToI64, [SiFive7PipeB]>; 148def : WriteRes<WriteFCvtF64ToF32, [SiFive7PipeB]>; 149 150def : WriteRes<WriteFClass32, [SiFive7PipeB]>; 151def : WriteRes<WriteFClass64, [SiFive7PipeB]>; 152def : WriteRes<WriteFCmp32, [SiFive7PipeB]>; 153def : WriteRes<WriteFCmp64, [SiFive7PipeB]>; 154def : WriteRes<WriteFMovI32ToF32, [SiFive7PipeB]>; 155def : WriteRes<WriteFMovF32ToI32, [SiFive7PipeB]>; 156def : WriteRes<WriteFMovI64ToF64, [SiFive7PipeB]>; 157def : WriteRes<WriteFMovF64ToI64, [SiFive7PipeB]>; 158} 159 160// Others 161def : WriteRes<WriteCSR, [SiFive7PipeB]>; 162def : WriteRes<WriteNop, []>; 163 164def : InstRW<[WriteIALU], (instrs COPY)>; 165 166//===----------------------------------------------------------------------===// 167// Bypass and advance 168def : ReadAdvance<ReadJmp, 0>; 169def : ReadAdvance<ReadJalr, 0>; 170def : ReadAdvance<ReadCSR, 0>; 171def : ReadAdvance<ReadStoreData, 0>; 172def : ReadAdvance<ReadMemBase, 0>; 173def : ReadAdvance<ReadIALU, 0>; 174def : ReadAdvance<ReadIALU32, 0>; 175def : ReadAdvance<ReadShiftImm, 0>; 176def : ReadAdvance<ReadShiftImm32, 0>; 177def : ReadAdvance<ReadShiftReg, 0>; 178def : ReadAdvance<ReadShiftReg32, 0>; 179def : ReadAdvance<ReadIDiv, 0>; 180def : ReadAdvance<ReadIDiv32, 0>; 181def : ReadAdvance<ReadIMul, 0>; 182def : ReadAdvance<ReadIMul32, 0>; 183def : ReadAdvance<ReadAtomicWA, 0>; 184def : ReadAdvance<ReadAtomicWD, 0>; 185def : ReadAdvance<ReadAtomicDA, 0>; 186def : ReadAdvance<ReadAtomicDD, 0>; 187def : ReadAdvance<ReadAtomicLDW, 0>; 188def : ReadAdvance<ReadAtomicLDD, 0>; 189def : ReadAdvance<ReadAtomicSTW, 0>; 190def : ReadAdvance<ReadAtomicSTD, 0>; 191def : ReadAdvance<ReadFMemBase, 0>; 192def : ReadAdvance<ReadFALU32, 0>; 193def : ReadAdvance<ReadFALU64, 0>; 194def : ReadAdvance<ReadFMul32, 0>; 195def : ReadAdvance<ReadFMA32, 0>; 196def : ReadAdvance<ReadFMul64, 0>; 197def : ReadAdvance<ReadFMA64, 0>; 198def : ReadAdvance<ReadFDiv32, 0>; 199def : ReadAdvance<ReadFDiv64, 0>; 200def : ReadAdvance<ReadFSqrt32, 0>; 201def : ReadAdvance<ReadFSqrt64, 0>; 202def : ReadAdvance<ReadFCmp32, 0>; 203def : ReadAdvance<ReadFCmp64, 0>; 204def : ReadAdvance<ReadFSGNJ32, 0>; 205def : ReadAdvance<ReadFSGNJ64, 0>; 206def : ReadAdvance<ReadFMinMax32, 0>; 207def : ReadAdvance<ReadFMinMax64, 0>; 208def : ReadAdvance<ReadFCvtF32ToI32, 0>; 209def : ReadAdvance<ReadFCvtF32ToI64, 0>; 210def : ReadAdvance<ReadFCvtF64ToI32, 0>; 211def : ReadAdvance<ReadFCvtF64ToI64, 0>; 212def : ReadAdvance<ReadFCvtI32ToF32, 0>; 213def : ReadAdvance<ReadFCvtI32ToF64, 0>; 214def : ReadAdvance<ReadFCvtI64ToF32, 0>; 215def : ReadAdvance<ReadFCvtI64ToF64, 0>; 216def : ReadAdvance<ReadFCvtF32ToF64, 0>; 217def : ReadAdvance<ReadFCvtF64ToF32, 0>; 218def : ReadAdvance<ReadFMovF32ToI32, 0>; 219def : ReadAdvance<ReadFMovI32ToF32, 0>; 220def : ReadAdvance<ReadFMovF64ToI64, 0>; 221def : ReadAdvance<ReadFMovI64ToF64, 0>; 222def : ReadAdvance<ReadFClass32, 0>; 223def : ReadAdvance<ReadFClass64, 0>; 224 225//===----------------------------------------------------------------------===// 226// Unsupported extensions 227defm : UnsupportedSchedV; 228defm : UnsupportedSchedZba; 229defm : UnsupportedSchedZbb; 230defm : UnsupportedSchedZbc; 231defm : UnsupportedSchedZbs; 232defm : UnsupportedSchedZbe; 233defm : UnsupportedSchedZbf; 234defm : UnsupportedSchedZbm; 235defm : UnsupportedSchedZbp; 236defm : UnsupportedSchedZbr; 237defm : UnsupportedSchedZbt; 238defm : UnsupportedSchedZfh; 239} 240